diff --git a/tests/silimate/extract_reduce.ys b/tests/silimate/extract_reduce.ys
index 6cf9880fd..888f0182a 100644
--- a/tests/silimate/extract_reduce.ys
+++ b/tests/silimate/extract_reduce.ys
@@ -39,13 +39,13 @@ module top (
   input wire [5:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4;
+  wire w0, w1, w2, w3;
 
-  assign w1 = a[0] & a[1];
-  assign w2 = a[2] & a[3];
-  assign w3 = a[4] & a[5];
-  assign w4 = w1 & w2;
-  assign x = w3 & w4;
+  assign w0 = a[0] & a[1];
+  assign w1 = a[2] & a[3];
+  assign w2 = a[4] & a[5];
+  assign w3 = w0 & w1;
+  assign x = w2 & w3;
 endmodule
 EOF
 check -assert
@@ -75,15 +75,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] & a[1];
-  assign w2 = w1 & a[2];
-  assign w3 = w2 & a[3];
-  assign x = w3 & a[4];
+  assign w0 = a[0] & a[1];
+  assign w1 = w0 & a[2];
+  assign w2 = w1 & a[3];
+  assign x = w2 & a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -116,15 +116,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] & a[1];
-  assign w2 = w1 & a[2];
-  assign w3 = w2 & a[3];
-  assign x = w3 & a[4];
+  assign w0 = a[0] & a[1];
+  assign w1 = w0 & a[2];
+  assign w2 = w1 & a[3];
+  assign x = w2 & a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -188,13 +188,13 @@ module top (
   input wire [5:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4;
+  wire w0, w1, w2, w3;
 
-  assign w1 = a[0] | a[1];
-  assign w2 = a[2] | a[3];
-  assign w3 = a[4] | a[5];
-  assign w4 = w1 | w2;
-  assign x = w3 | w4;
+  assign w0 = a[0] | a[1];
+  assign w1 = a[2] | a[3];
+  assign w2 = a[4] | a[5];
+  assign w3 = w0 | w1;
+  assign x = w2 | w3;
 endmodule
 EOF
 check -assert
@@ -224,15 +224,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] | a[1];
-  assign w2 = w1 | a[2];
-  assign w3 = w2 | a[3];
-  assign x = w3 | a[4];
+  assign w0 = a[0] | a[1];
+  assign w1 = w0 | a[2];
+  assign w2 = w1 | a[3];
+  assign x = w2 | a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -265,15 +265,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] | a[1];
-  assign w2 = w1 | a[2];
-  assign w3 = w2 | a[3];
-  assign x = w3 | a[4];
+  assign w0 = a[0] | a[1];
+  assign w1 = w0 | a[2];
+  assign w2 = w1 | a[3];
+  assign x = w2 | a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -337,13 +337,13 @@ module top (
   input wire [5:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4;
+  wire w0, w1, w2, w3;
 
-  assign w1 = a[0] ^ a[1];
-  assign w2 = a[2] ^ a[3];
-  assign w3 = a[4] ^ a[5];
-  assign w4 = w1 ^ w2;
-  assign x = w3 ^ w4;
+  assign w0 = a[0] ^ a[1];
+  assign w1 = a[2] ^ a[3];
+  assign w2 = a[4] ^ a[5];
+  assign w3 = w0 ^ w1;
+  assign x = w2 ^ w3;
 endmodule
 EOF
 check -assert
@@ -373,15 +373,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] ^ a[1];
-  assign w2 = w1 ^ a[2];
-  assign w3 = w2 ^ a[3];
-  assign x = w3 ^ a[4];
+  assign w0 = a[0] ^ a[1];
+  assign w1 = w0 ^ a[2];
+  assign w2 = w1 ^ a[3];
+  assign x = w2 ^ a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -415,15 +415,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = a[0] ^ a[1];
-  assign w2 = w1 ^ a[2];
-  assign w3 = w2 ^ a[3];
-  assign x = w3 ^ a[4];
+  assign w0 = a[0] ^ a[1];
+  assign w1 = w0 ^ a[2];
+  assign w2 = w1 ^ a[3];
+  assign x = w2 ^ a[4];
 
-  // Off-chain use of w2
-  assign y = w2;
+  // Off-chain use of w1
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -461,11 +461,11 @@ module top (
   input wire [3:0] a,
   output wire x
 );
-  wire w1, w2;
+  wire w0, w1;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign x  = sel[2] ? a[3] : w2;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign x  = sel[2] ? a[3] : w1;
 endmodule
 EOF
 check -assert
@@ -495,11 +495,11 @@ module top (
   input wire [3:0] a,
   output wire x
 );
-  wire w1, w2;
+  wire w0, w1;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : a[3];
-  assign x  = sel[2] ? w1 : w2;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : a[3];
+  assign x  = sel[2] ? w0 : w1;
 endmodule
 EOF
 check -assert
@@ -529,14 +529,14 @@ module top (
   input wire [6:0] a,
   output wire x
 );
-  wire w1, w2, w3, w4, w5;
+  wire w0, w1, w2, w3, w4;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign w3 = sel[2] ? a[3] : w2;
-  assign w4 = sel[3] ? w3 : w5;
-  assign w5 = sel[5] ? a[4] : a[5];
-  assign x  = sel[4] ? w4 : a[6];
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign w3 = sel[3] ? w2 : w4;
+  assign w4 = sel[5] ? a[4] : a[5];
+  assign x  = sel[4] ? w3 : a[6];
 endmodule
 EOF
 check -assert
@@ -575,15 +575,15 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign w3 = sel[2] ? a[3] : w2;
-  assign x  = sel[3] ? a[4] : w3;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign x  = sel[3] ? a[4] : w2;
 
   // Off-chain use of intermediate wire
-  assign y = w2;
+  assign y = w1;
 endmodule
 EOF
 check -assert
@@ -618,14 +618,14 @@ module top (
   output wire x,
   output wire y
 );
-  wire w1, w2, w3;
+  wire w0, w1, w2;
 
-  assign w1 = sel[0] ? a[1] : a[0];
-  assign w2 = sel[1] ? a[2] : w1;
-  assign w3 = sel[2] ? a[3] : w2;
-  assign x  = sel[3] ? a[4] : w3;
+  assign w0 = sel[0] ? a[1] : a[0];
+  assign w1 = sel[1] ? a[2] : w0;
+  assign w2 = sel[2] ? a[3] : w1;
+  assign x  = sel[3] ? a[4] : w2;
 
-  assign y = w2;
+  assign y = w1;
 endmodule
 EOF
 check -assert