diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index 5de08a329..d4f85c789 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -30,7 +30,9 @@ YOSYS_NAMESPACE_BEGIN
 
 typedef std::pair<Cell*, IdString> cell_port_t;
 
-
+// Since this is kernel code, we only log with yosys_xtrace set to not get
+// in the way when using `debug` to debug specific passes.q
+#define xlog(...) do { if (yosys_xtrace) log("#X [bufnorm] " __VA_ARGS__); } while (0)
 
 struct RTLIL::SigNormIndex
 {
@@ -315,6 +317,7 @@ void RTLIL::Design::sigNormalize(bool enable)
 			return;
 
 
+		xlog("leaving signorm\n");
 		for (auto module : modules()) {
 			module->connections();
 			if (module->sig_norm_index != nullptr) {
@@ -343,8 +346,7 @@ void RTLIL::Design::sigNormalize(bool enable)
 
 	if (!flagSigNormalized)
 	{
-
-
+		xlog("entering signorm\n");
 		flagSigNormalized = true;
 	}
 
@@ -507,9 +509,6 @@ void RTLIL::Module::remove(RTLIL::Cell *cell)
 
 void RTLIL::Module::bufNormalize()
 {
-	// Since this is kernel code, we only log with yosys_xtrace set to not get
-	// in the way when using `debug` to debug specific passes.q
-#define xlog(...) do { if (yosys_xtrace) log("#X [bufnorm] " __VA_ARGS__); } while (0)
 
 	if (!design->flagBufferedNormalized)
 		return;