diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index b2caae460..e6aa664f4 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -20,6 +20,7 @@
 #include "kernel/yosys.h"
 #include "kernel/sigtools.h"
 #include "kernel/gzip.h"
+#include "kernel/newcelltypes.h"
 #include "libparse.h"
 #include <string.h>
 #include <errno.h>
@@ -503,6 +504,11 @@ static void dfflibmap(RTLIL::Design *design, RTLIL::Module *module)
 
 	std::vector<RTLIL::Cell*> cell_list;
 	for (auto cell : module->cells()) {
+		auto cats = StaticCellTypes::categories;
+		if (cats.is_ff(cell->type) && !cats.is_stdcell(cell->type))
+		log_error("Wide register cell type %s is not supported.\n"
+				  "Convert netlist to gate-level first.\n", cell->type);
+
 		if (design->selected(module, cell) && cell_mappings.count(cell->type) > 0)
 			cell_list.push_back(cell);
 		if (cell->type == ID($_NOT_))
diff --git a/tests/techmap/dfflibmap_wide.ys b/tests/techmap/dfflibmap_wide.ys
new file mode 100644
index 000000000..b3b50ae14
--- /dev/null
+++ b/tests/techmap/dfflibmap_wide.ys
@@ -0,0 +1,5 @@
+read_verilog ../sim/dff.v
+proc
+logger -expect error "not supported" 1
+dfflibmap -liberty dfflibmap.lib
+logger -check-expected
\ No newline at end of file