From 80fbdf7e6a31365e3d6bcd0869ab9c76fe72c6e7 Mon Sep 17 00:00:00 2001
From: AdvaySingh1 <advay@umich.edu>
Date: Fri, 13 Feb 2026 15:33:45 -0800
Subject: [PATCH] Removed duplication of vectors and called clockgate pass post
 creating enable signals

---
 passes/silimate/sat_clockgate.cc | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

diff --git a/passes/silimate/sat_clockgate.cc b/passes/silimate/sat_clockgate.cc
index 089fb1305..3b31a9b61 100644
--- a/passes/silimate/sat_clockgate.cc
+++ b/passes/silimate/sat_clockgate.cc
@@ -89,7 +89,6 @@ struct SatClockgateWorker
 	// Get downstream signals from a register (BFS forward through combinational logic)
 	pool<SigBit> getDownstreamSignals(Cell *reg, int limit)
 	{
-		pool<SigBit> result;
 		pool<SigBit> visited;
 		std::queue<SigBit> worklist;
 		
@@ -102,12 +101,10 @@ struct SatClockgateWorker
 			}
 		}
 		
-		while (!worklist.empty() && (int)result.size() < limit) {
+		while (!worklist.empty() && (int)visited.size() < limit) {
 			SigBit bit = worklist.front();
 			worklist.pop();
 			
-			result.insert(bit);
-			
 			// Find cells driven by this signal
 			for (auto sink_cell : sig_to_sinks[bit]) {
 				// Skip registers - don't traverse through them
@@ -130,13 +127,12 @@ struct SatClockgateWorker
 			}
 		}
 		
-		return result;
+		return visited;
 	}
 	
 	// Get upstream signals feeding into given signals (BFS backward)
 	pool<SigBit> getUpstreamSignals(const pool<SigBit> &start_signals, int limit)
 	{
-		pool<SigBit> result;
 		pool<SigBit> visited;
 		std::queue<SigBit> worklist;
 		
@@ -145,12 +141,10 @@ struct SatClockgateWorker
 			visited.insert(bit);
 		}
 		
-		while (!worklist.empty() && (int)result.size() < limit) {
+		while (!worklist.empty() && (int)visited.size() < limit) {
 			SigBit bit = worklist.front();
 			worklist.pop();
 			
-			result.insert(bit);
-			
 			// Find driver cell
 			if (!sig_to_driver.count(bit))
 				continue;
@@ -176,7 +170,7 @@ struct SatClockgateWorker
 			}
 		}
 		
-		return result;
+		return visited;
 	}
 	
 	// Check if a candidate signal is a valid gating condition using SAT
@@ -543,6 +537,9 @@ struct SatClockgatePass : public Pass {
 		}
 		
 		log("Total clock gates inserted: %d\n", total_gates);
+		
+		// Convert CEs to actual clock gate cells
+		Pass::call(design, "clockgate");
 	}
 } SatClockgatePass;