From 7fef67a1413c463af027265aa5f5c514dc6ca43a Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Wed, 27 May 2026 15:09:27 +0200
Subject: [PATCH] Simplify nexus map.

---
 techlibs/lattice/dsp_map_nexus.v | 29 ++++++-----------------------
 1 file changed, 6 insertions(+), 23 deletions(-)

diff --git a/techlibs/lattice/dsp_map_nexus.v b/techlibs/lattice/dsp_map_nexus.v
index 35caacd10..61d2d96a8 100644
--- a/techlibs/lattice/dsp_map_nexus.v
+++ b/techlibs/lattice/dsp_map_nexus.v
@@ -78,7 +78,7 @@ module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
 	);
 endmodule
 
-module \$__NX_MAC18X18 (A, B, C, Y);
+module \$__NX_MAC18X18 (input [17:0] A, input [17:0] B, input [47:0] C, output [53:0] Y);
 
 	parameter A_WIDTH = 18;
 	parameter B_WIDTH = 18;
@@ -87,12 +87,6 @@ module \$__NX_MAC18X18 (A, B, C, Y);
 	parameter A_SIGNED = 0;
 	parameter B_SIGNED = 0;
 	parameter SUBTRACT = 0;
-	input [17:0] A;
-	input [17:0] B;
-	input [47:0] C;
-	output [47:0] Y;
-	wire [53:0] Z_out;
-	assign Y = Z_out[47:0];
 
 	MULTADDSUB18X18 #(
 		.REGINPUTA("BYPASS"),
@@ -105,23 +99,16 @@ module \$__NX_MAC18X18 (A, B, C, Y);
 		.C({6'b0, C}),
 		.SIGNED(A_SIGNED ? 1'b1 : 1'b0), 
 		.ADDSUB(SUBTRACT ? 1'b1 : 1'b0),
-		.Z(Z_out)
+		.Z(Y)
 	);
 endmodule
 
-module \$__NX_PREADD18X18 (A, B, C, Y, CLK);
+module \$__NX_PREADD18X18 (input [17:0] A, input [17:0] B, input [17:0] C, input CLK, output [35:0] Y);
 
 	parameter PIPELINED = 0;
 	parameter A_SIGNED = 0;
 	parameter B_SIGNED = 0;
 	parameter C_SIGNED = 0;
-	input [17:0] A;
-	input [17:0] B;
-	input [17:0] C;
-	input CLK;
-	output [47:0] Y;
-	wire [35:0] Z_out;
-	assign Y = A_SIGNED ? {{12{Z_out[35]}}, Z_out} : {12'b0, Z_out};
 
 	MULTPREADD18X18 #(
 		.REGINPUTA("BYPASS"),
@@ -136,17 +123,13 @@ module \$__NX_PREADD18X18 (A, B, C, Y, CLK);
 		.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
 		.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
 		.SIGNEDC(C_SIGNED ? 1'b1 : 1'b0),
-		.Z(Z_out)
+		.Z(Y)
 	);
 endmodule
 
-module \$__NX_MAC9X9WIDE_4LANE (A0, B0, A1, B1, A2, B2, A3, B3, Y);
+module \$__NX_MAC9X9WIDE_4LANE (input [8:0] A0, B0, A1, B1, A2, B2, A3, B3, output [53:0] Y);
 
 	parameter SIGNED = 0;
-	input [8:0] A0, B0, A1, B1, A2, B2, A3, B3;
-	output [47:0] Y;
-	wire [53:0] Z_out;
-	assign Y = Z_out[47:0];
 
 	MULTADDSUB9X9WIDE #(
 		.REGINPUTAB0("BYPASS"),
@@ -163,6 +146,6 @@ module \$__NX_MAC9X9WIDE_4LANE (A0, B0, A1, B1, A2, B2, A3, B3, Y);
 		.C(54'b0),
 		.SIGNED(SIGNED ? 1'b1 : 1'b0),
 		.ADDSUB(4'b0000),
-		.Z(Z_out)
+		.Z(Y)
 	);
 endmodule