diff --git a/tests/techmap/README.md b/tests/techmap/README.md
new file mode 100644
index 000000000..56f8b438f
--- /dev/null
+++ b/tests/techmap/README.md
@@ -0,0 +1,4 @@
+# Disabled tests
+
+- abc_state.ys: need to update to get this
+
diff --git a/tests/techmap/abc_state.ys.DISABLED b/tests/techmap/abc_state.ys.DISABLED
new file mode 100644
index 000000000..bc2a744f5
--- /dev/null
+++ b/tests/techmap/abc_state.ys.DISABLED
@@ -0,0 +1,26 @@
+read_verilog <<EOT
+module simple(I1, I2, O);
+	input wire I1;
+	input wire I2;
+	output wire O;
+
+	assign O = I1 | I2;
+endmodule
+EOT
+abc -g all
+
+design -reset
+read_verilog <<EOT
+module simple(I1, I2, O);
+	input wire I1;
+	input wire I2;
+	output wire O;
+
+	assign O = I1 | I2;
+endmodule
+EOT
+techmap
+abc -g AND
+
+select -assert-count 0 t:$_OR_
+select -assert-count 1 t:$_AND_