diff --git a/tests/silimate/mux_ornot.ys b/tests/silimate/mux_ornot.ys
index d4bba79e2..c6d153ba3 100644
--- a/tests/silimate/mux_ornot.ys
+++ b/tests/silimate/mux_ornot.ys
@@ -71,9 +71,7 @@ equiv_opt -assert opt_expr -mux_bool
 
 # Check final design has correct number of gates
 # Did not include check for not count since we have an unassigned ~s wire
-# TODO check
 design -load postopt
-write_verilog dump.v
 select -assert-count 1 t:$or
 
 design -reset