From 75a2ff3ed8f8d463ba6ceac4abb35d8957e07cc0 Mon Sep 17 00:00:00 2001
From: tangxifan <tangxifan@gmail.com>
Date: Thu, 14 May 2026 17:57:12 -0700
Subject: [PATCH] [core] debug

---
 techlibs/rapidflex/src/clock_buffer_cmd.cc | 10 +++++-----
 techlibs/rapidflex/src/rf_dsp_mad.cc       |  2 +-
 techlibs/rapidflex/src/rf_new_dsp.cc       |  4 ++--
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/techlibs/rapidflex/src/clock_buffer_cmd.cc b/techlibs/rapidflex/src/clock_buffer_cmd.cc
index 2deb9ee04..253260522 100644
--- a/techlibs/rapidflex/src/clock_buffer_cmd.cc
+++ b/techlibs/rapidflex/src/clock_buffer_cmd.cc
@@ -104,9 +104,9 @@ struct InsertClockBuffer : public Pass {
   void rewire_subckt(RTLIL::Module *module, RTLIL::Cell *cell,
                      RTLIL::IdString id_name, std::string C_input) {
     std::string C_output = C_input + "_ckbuf";
-    if (!module->wire("\\" + C_output)) {
-      auto output_wire = module->addWire("\\" + C_output, 1);
-    }
+//    if (!module->wire("\\" + C_output)) {
+//      auto output_wire = module->addWire("\\" + C_output, 1);
+//    }
     /* connect new ckbuf to the subckt */
     cell->unsetPort(id_name); // unsetPort("C")
     cell->setPort(id_name, module->wire("\\" + C_output));
@@ -186,7 +186,7 @@ struct InsertClockBuffer : public Pass {
   representing internally generated signals. When such a signal is found, it
   invokes rewire_subckt.*/
   std::set<std::string>
-  find_internal_clk_r_signal(RTLIL::Module *module, RTLIL::Design *design,
+  find_internal_clk_r_signal(RTLIL::Module *module,
                              std::map<std::string, std::string> &ckbuf_type) {
     std::set<std::string> ckbuf_info;
     /*get input ports of the top module*/
@@ -528,7 +528,7 @@ struct InsertClockBuffer : public Pass {
       if (module->name == RTLIL::escape_id(top_module_name)) {
         std::map<std::string, std::string> ckbuf_type;
         std::set<std::string> ckbuf_info =
-            find_internal_clk_r_signal(module, design, ckbuf_type);
+            find_internal_clk_r_signal(module, ckbuf_type);
         /*insert ckbuf and rewire dff */
         insert_ckbuf(module, ckbuf_info);
 
diff --git a/techlibs/rapidflex/src/rf_dsp_mad.cc b/techlibs/rapidflex/src/rf_dsp_mad.cc
index 1ccdf4a79..7f943eadb 100644
--- a/techlibs/rapidflex/src/rf_dsp_mad.cc
+++ b/techlibs/rapidflex/src/rf_dsp_mad.cc
@@ -4,7 +4,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "pmgen/rf_dsp_mad.h"
+#include "rf_dsp_mad_pm.h"
 
 static void create_rf_mad_dsp(rf_dsp_mad_pm &pm) {
   auto &st = pm.st_rf_dsp_mad;
diff --git a/techlibs/rapidflex/src/rf_new_dsp.cc b/techlibs/rapidflex/src/rf_new_dsp.cc
index aa42742e2..50d11ec05 100644
--- a/techlibs/rapidflex/src/rf_new_dsp.cc
+++ b/techlibs/rapidflex/src/rf_new_dsp.cc
@@ -4,7 +4,7 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-#include "pmgen/rf_new_dsp.h"
+#include "rf_new_dsp_pm.h"
 
 void swapinput(RTLIL::SigSpec &sigA, RTLIL::SigSpec &sigB) {
   if (GetSize(sigA) < GetSize(sigB)) {
@@ -438,4 +438,4 @@ struct RfNewDSP : public Pass {
   }
 } RfNewDsp;
 
-PRIVATE_NAMESPACE_END
\ No newline at end of file
+PRIVATE_NAMESPACE_END