diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc
index 49f84294e..3dc9d641a 100644
--- a/techlibs/fabulous/synth_fabulous.cc
+++ b/techlibs/fabulous/synth_fabulous.cc
@@ -417,7 +417,7 @@ struct SynthPass : public ScriptPass {
 		}
 
 		if (check_label("map_luts")) {
-			run(stringf("abc -lut %d -dress", lut));
+			run(stringf("abc9 -lut %d", lut));
 			run("clean");
 		}
 
diff --git a/tests/arch/fabulous/fsm.ys b/tests/arch/fabulous/fsm.ys
index b00c8a388..f20080db8 100644
--- a/tests/arch/fabulous/fsm.ys
+++ b/tests/arch/fabulous/fsm.ys
@@ -13,7 +13,6 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p
 cd fsm # Constrain all select calls below inside the top module
 
 select -assert-count 6 t:LUTFF
-select -assert-max 5 t:LUT2
-select -assert-max 4 t:LUT3
-select -assert-max 8 t:LUT4
-select -assert-none t:LUT2 t:LUT3 t:LUT4 t:LUTFF %% t:* %D
+select -assert-max 4 t:LUT2
+select -assert-max 11 t:LUT4
+select -assert-none t:LUT2 t:LUT4 t:LUTFF %% t:* %D
diff --git a/tests/arch/fabulous/logic.ys b/tests/arch/fabulous/logic.ys
index e5b4773e7..41dffaef4 100644
--- a/tests/arch/fabulous/logic.ys
+++ b/tests/arch/fabulous/logic.ys
@@ -4,7 +4,7 @@ proc
 equiv_opt -assert -map prims.v synth_fabulous -noiopad -ff $_DFF_P_ x -ff $_DLATCH_?_ x -extra-plib prims.v -cells-map cells_map.v  -arith-map arith_map.v -extra-map ff_map.v -extra-map latches_map.v # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
-select -assert-max 1 t:LUT1
-select -assert-max 6 t:LUT2
+select -assert-max 4 t:LUT1
+select -assert-max 3 t:LUT2
 select -assert-max 2 t:LUT4
 select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D