From da1ac9ae47df62301dcaed05c8679dbb3508fd10 Mon Sep 17 00:00:00 2001
From: sdjasj <89853352+sdjasj@users.noreply.github.com>
Date: Sat, 3 May 2025 17:38:16 +0800
Subject: [PATCH 1/4] cxxrtl: fix missing sign extension before shift operation
 for signed values

---
 backends/cxxrtl/runtime/cxxrtl/cxxrtl.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
index 886d033cb..9b4f5774f 100644
--- a/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
+++ b/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
@@ -1769,7 +1769,7 @@ value<BitsY> shr_uu(const value<BitsA> &a, const value<BitsB> &b) {
 template<size_t BitsY, size_t BitsA, size_t BitsB>
 CXXRTL_ALWAYS_INLINE
 value<BitsY> shr_su(const value<BitsA> &a, const value<BitsB> &b) {
-	return a.shr(b).template scast<BitsY>();
+	return a.template scast<BitsY>().shr(b);
 }
 
 template<size_t BitsY, size_t BitsA, size_t BitsB>

From 765485a375cc766e9f3e4e9c7bd245c730ad7359 Mon Sep 17 00:00:00 2001
From: "github-actions[bot]"
 <41898282+github-actions[bot]@users.noreply.github.com>
Date: Sun, 4 May 2025 00:26:28 +0000
Subject: [PATCH 2/4] Bump version

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index d2f518d88..aa3624253 100644
--- a/Makefile
+++ b/Makefile
@@ -160,7 +160,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.52+137
+YOSYS_VER := 0.52+139
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2 | cut -d'+' -f1)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'+' -f2)

From 23cb00706812465b3ff2c3ecf02ed9a3a27b40a3 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 5 May 2025 10:04:13 +1200
Subject: [PATCH 3/4] verilog_parser.y: Delete unused TOK_ID

Fixes memory leak when parameter has no value.
---
 frontends/verilog/verilog_parser.y | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
index fe86626b8..9d0956c8e 100644
--- a/frontends/verilog/verilog_parser.y
+++ b/frontends/verilog/verilog_parser.y
@@ -2249,7 +2249,8 @@ cell_parameter:
 		node->children.push_back($1);
 	} |
 	'.' TOK_ID '(' ')' {
-		// just ignore empty parameters
+		// delete unused TOK_ID
+		delete $2;
 	} |
 	'.' TOK_ID '(' expr ')' {
 		AstNode *node = new AstNode(AST_PARASET);

From 7c2b00c448ee37e9af27cf497f24d0526a57c40b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 5 May 2025 10:18:52 +1200
Subject: [PATCH 4/4] tests: Add default param test file

Just loads, fails ASAN without fix.
---
 tests/verilog/param_default.ys | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)
 create mode 100644 tests/verilog/param_default.ys

diff --git a/tests/verilog/param_default.ys b/tests/verilog/param_default.ys
new file mode 100644
index 000000000..59023c477
--- /dev/null
+++ b/tests/verilog/param_default.ys
@@ -0,0 +1,24 @@
+logger -expect-no-warnings
+read_verilog << EOF
+module bar (
+	input portname
+);
+	parameter paramname = 7;
+endmodule
+ 
+module empty (
+);
+ 	bar #() barinstance ();
+endmodule
+
+module implicit (
+);
+ 	bar #(.paramname()) barinstance (.portname());
+endmodule
+
+module explicit (
+	input a
+);
+	bar #(.paramname(3)) barinstance (.portname(a));
+endmodule
+EOF