diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index 5c7c0b532..e9dfb6977 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -57,9 +57,6 @@ struct SynthAnlogicPass : public ScriptPass
 		log("    -noflatten\n");
 		log("        do not flatten design before synthesis\n");
 		log("\n");
-		log("    -retime\n");
-		log("        run 'abc' with '-dff -D 1' options\n");
-		log("\n");
 		log("    -nolutram\n");
 		log("        do not use EG_LOGIC_DRAM16X4 cells in output netlist\n");
 		log("\n");
@@ -81,7 +78,6 @@ struct SynthAnlogicPass : public ScriptPass
 		edif_file = "";
 		json_file = "";
 		flatten = true;
-		retime = false;
 		nolutram = false;
 		nobram = false;
 	}
@@ -126,10 +122,6 @@ struct SynthAnlogicPass : public ScriptPass
 				nobram = true;
 				continue;
 			}
-			if (args[argidx] == "-retime") {
-				retime = true;
-				continue;
-			}
 			break;
 		}
 		extra_args(args, argidx, design);
@@ -193,8 +185,6 @@ struct SynthAnlogicPass : public ScriptPass
 		{
 			run("techmap -map +/techmap.v -map +/anlogic/arith_map.v");
 			run("opt -fast");
-			if (retime || help_mode)
-				run("abc -dff -D 1", "(only if -retime)");
 		}
 
 		if (check_label("map_ffs"))
@@ -207,7 +197,7 @@ struct SynthAnlogicPass : public ScriptPass
 
 		if (check_label("map_luts"))
 		{
-			run("abc -lut 4:6");
+			run("abc9 -lut 4:6");
 			run("clean");
 		}
 
diff --git a/tests/arch/anlogic/logic.ys b/tests/arch/anlogic/logic.ys
index 125ee5d0f..0c570eb17 100644
--- a/tests/arch/anlogic/logic.ys
+++ b/tests/arch/anlogic/logic.ys
@@ -5,7 +5,7 @@ equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd top # Constrain all select calls below inside the top module
 
-select -assert-count 1 t:AL_MAP_LUT1
-select -assert-count 6 t:AL_MAP_LUT2
+select -assert-count 4 t:AL_MAP_LUT1
+select -assert-count 3 t:AL_MAP_LUT2
 select -assert-count 2 t:AL_MAP_LUT4
 select -assert-none t:AL_MAP_LUT1 t:AL_MAP_LUT2 t:AL_MAP_LUT4 %% t:* %D
diff --git a/tests/arch/anlogic/mux.ys b/tests/arch/anlogic/mux.ys
index 64a04d08d..ce6dd3a52 100644
--- a/tests/arch/anlogic/mux.ys
+++ b/tests/arch/anlogic/mux.ys
@@ -26,12 +26,10 @@ proc
 equiv_opt -assert -map +/anlogic/cells_sim.v synth_anlogic # equivalency check
 design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
 cd mux8 # Constrain all select calls below inside the top module
-select -assert-max 3 t:AL_MAP_LUT3
-select -assert-max 3 t:AL_MAP_LUT4
+select -assert-max 4 t:AL_MAP_LUT4
 select -assert-max 1 t:AL_MAP_LUT5
-select -assert-max 1 t:AL_MAP_LUT6
 
-select -assert-none t:AL_MAP_LUT3 t:AL_MAP_LUT4 t:AL_MAP_LUT5 t:AL_MAP_LUT6 %% t:* %D
+select -assert-none t:AL_MAP_LUT4 t:AL_MAP_LUT5 %% t:* %D
 
 design -load read
 hierarchy -top mux16