From 6cd66aed47e69bac3e820b9d9e2150a5fa900466 Mon Sep 17 00:00:00 2001 From: abhinavputhran Date: Thu, 5 Mar 2026 17:51:01 -0500 Subject: [PATCH] setundef: rename process loop variable and respect selection in -init mode --- passes/cmds/setundef.cc | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc index 792b9b12c..ecbada2f8 100644 --- a/passes/cmds/setundef.cc +++ b/passes/cmds/setundef.cc @@ -417,6 +417,9 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; + if (!design->selected(module, wire)) + continue; + if (!wire->attributes.count(ID::init)) continue; @@ -446,6 +449,9 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; + if (!design->selected(module, wire)) + continue; + for (auto bit : sigmap(wire)) if (!ffbits.count(bit)) goto next_wire; @@ -467,6 +473,9 @@ struct SetundefPass : public Pass { if (wire->name[0] == (wire_types ? '\\' : '$')) continue; + if (!design->selected(module, wire)) + continue; + for (auto bit : sigmap(wire)) if (ffbits.count(bit)) initwires.insert(wire); @@ -505,8 +514,8 @@ struct SetundefPass : public Pass { for (auto cell : module->selected_cells()) if (!cell->get_bool_attribute(ID::xprop_decoder)) cell->rewrite_sigspecs(worker); - for (auto &it : module->selected_processes()) - it->rewrite_sigspecs(worker); + for (auto proc : module->selected_processes()) + proc->rewrite_sigspecs(worker); for (auto &it : module->connections_) { SigSpec lhs = it.first; bool selected = false;