From 6824ee065ae8b2511879aa5edaec0dfe7860fc3f Mon Sep 17 00:00:00 2001 From: Lofty Date: Mon, 10 Aug 2026 11:42:47 +0100 Subject: [PATCH] synth_nanoxplore: remove classic ABC mapping --- techlibs/nanoxplore/cells_sim.v | 10 +-------- techlibs/nanoxplore/cells_sim_u.v | 3 --- techlibs/nanoxplore/synth_nanoxplore.cc | 28 ++++++++----------------- 3 files changed, 10 insertions(+), 31 deletions(-) diff --git a/techlibs/nanoxplore/cells_sim.v b/techlibs/nanoxplore/cells_sim.v index 7453821d0..04baa027d 100644 --- a/techlibs/nanoxplore/cells_sim.v +++ b/techlibs/nanoxplore/cells_sim.v @@ -1,4 +1,3 @@ -(* abc9_lut=1 *) module NX_LUT(input I1, I2, I3, I4, output O); parameter lut_table = 16'h0000; @@ -10,7 +9,6 @@ assign O = I1 ? s3[1] : s3[0]; endmodule -(* abc9_box, lib_whitebox *) module NX_DFF(input I, CK, L, R, output reg O); parameter dff_ctxt = 1'bx; @@ -36,7 +34,6 @@ always @(posedge clock, posedge async_reset) endmodule -(* abc9_box, lib_whitebox *) module NX_DFR(input I, CK, L, R, output O); parameter data_inv = 1'b0; @@ -67,8 +64,7 @@ assign O = data_inv ? O_reg : ~O_reg; endmodule -(* abc9_box, lib_whitebox *) -module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, (* abc9_carry *) input CI, output S1, S2, S3, S4, (* abc9_carry *) output CO); +module NX_CY(input A1, A2, A3, A4, B1, B2, B3, B4, input CI, output S1, S2, S3, S4, output CO); parameter add_carry = 0; wire CI_1; @@ -175,14 +171,11 @@ module NX_IOB_O(I, C, T, IO); assign IO = C ? I : 1'bz; endmodule -(* abc9_box, lib_whitebox *) module NX_CY_1BIT(CI, A, B, S, CO); - (* abc9_carry *) input CI; input A; input B; output S; - (* abc9_carry *) output CO; parameter first = 1'b0; @@ -217,7 +210,6 @@ module NX_BFR(I, O); assign O = data_inv ? ~I : I; endmodule -(* abc9_box, lib_whitebox *) module NX_RAM(ACK, ACKC, ACKD, ACKR, BCK, BCKC, BCKD, BCKR, AI1, AI2, AI3, AI4, AI5, AI6, AI7, AI8, AI9, AI10, AI11, AI12, AI13 , AI14, AI15, AI16, AI17, AI18, AI19, AI20, AI21, AI22, AI23, AI24, BI1, BI2, BI3, BI4, BI5, BI6, BI7, BI8, BI9, BI10 , BI11, BI12, BI13, BI14, BI15, BI16, BI17, BI18, BI19, BI20, BI21, BI22, BI23, BI24, ACOR, AERR, BCOR, BERR, AO1, AO2, AO3 diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v index 1c83fb2c0..1fa6f04a6 100644 --- a/techlibs/nanoxplore/cells_sim_u.v +++ b/techlibs/nanoxplore/cells_sim_u.v @@ -1,4 +1,3 @@ -(* abc9_box, lib_whitebox *) module NX_GCK_U(SI1, SI2, CMD, SO); input CMD; input SI1; @@ -31,7 +30,6 @@ module NX_GCK_U(SI1, SI2, CMD, SO); assign SO = inv_out ? ~SO_int : SO_int; endmodule -(* abc9_box, lib_whitebox *) module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15, I16, I17, I18, I19, I20 , I21, I22, I23, I24, I25, I26, I27, I28, I29, I30, I31, I32, I33, I34, I35, I36, O1, O2, O3, O4, O5 , O6, O7, O8, O9, O10, O11, O12, O13, O14, O15, O16, O17, O18, O19, O20, O21, O22, O23, O24, O25, O26 @@ -205,7 +203,6 @@ module NX_RFB_U(WCK, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14 mem[WA] <= I[MEM_WIDTH-1:0]; endmodule -(* abc9_box, lib_whitebox *) module NX_WFG_U(R, SI, ZI, SO, ZO); input R; input SI; diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 20919bead..8eb61a9d9 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -66,9 +66,6 @@ struct SynthNanoXplorePass : public ScriptPass log(" -noflatten\n"); log(" do not flatten design before synthesis\n"); log("\n"); - log(" -abc9\n"); - log(" use new ABC9 flow (EXPERIMENTAL)\n"); - log("\n"); log(" -nocy\n"); log(" do not map adders to CY cells\n"); log("\n"); @@ -110,7 +107,7 @@ struct SynthNanoXplorePass : public ScriptPass } string top_opt, json_file, family, latches; - bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check; + bool flatten, nocy, nodffe, norfram, nobram, noiopad, no_rw_check; std::string postfix; int min_ce_use, min_srst_use; @@ -120,7 +117,6 @@ struct SynthNanoXplorePass : public ScriptPass json_file = ""; family = ""; flatten = true; - abc9 = false; nocy = false; nodffe = false; norfram = false; @@ -170,7 +166,7 @@ struct SynthNanoXplorePass : public ScriptPass continue; } if (args[argidx] == "-abc9") { - abc9 = true; + // Removed: ABC9 is the default continue; } if (args[argidx] == "-nocy") { @@ -349,19 +345,13 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("map_luts")) { - if (abc9) { - std::string abc9_opts = " -maxlut 4"; - std::string k = "synth_nanoxplore.abc9.W"; - if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); - else - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); - run("abc9" + abc9_opts); - } else { - std::string abc_args = " -dress"; - abc_args += " -lut 4"; - run("abc" + abc_args); - } + std::string abc9_opts = " -lut 4"; + std::string k = "synth_nanoxplore.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); + else + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); + run("abc9" + abc9_opts); run("techmap -map +/nanoxplore/cells_map.v t:$lut"); run("opt -fast"); run("clean");