diff --git a/docs/source/code_examples/extensions/my_cmd.cc b/docs/source/code_examples/extensions/my_cmd.cc
index 742697b6e..f68ff2d8a 100644
--- a/docs/source/code_examples/extensions/my_cmd.cc
+++ b/docs/source/code_examples/extensions/my_cmd.cc
@@ -42,7 +42,7 @@ struct Test1Pass : public Pass {
         module->addNeg(NEW_ID, a, a_inv, true);
         module->addMux(NEW_ID, a, a_inv, RTLIL::SigSpec(a, 3), y);
 
-	module->fixup_ports();
+    module->fixup_ports();
     }
 } Test1Pass;
 
diff --git a/passes/sat/recover_names.cc b/passes/sat/recover_names.cc
index e2c93df65..8430fd1ac 100644
--- a/passes/sat/recover_names.cc
+++ b/passes/sat/recover_names.cc
@@ -532,11 +532,11 @@ struct RecoverNamesWorker {
     }
 
     int popcount(equiv_cls_t cls) {
-    	int result = 0;
-    	for (unsigned i = 0; i < 8*sizeof(equiv_cls_t); i++)
-    		if ((cls >> i) & 0x1)
-    			++result;
-    	return result;
+        int result = 0;
+        for (unsigned i = 0; i < 8*sizeof(equiv_cls_t); i++)
+            if ((cls >> i) & 0x1)
+                ++result;
+        return result;
     }
 
     bool prove_equiv(RecoverModuleWorker &gold_worker, RecoverModuleWorker &gate_worker,
@@ -624,12 +624,12 @@ struct RecoverNamesWorker {
         dict<IdBit, InvBit> gate2gold;
         // Solve starting from shallowest
         for (auto cls : cls_depth) {
-        	int pop = popcount(cls.first);
-        	// Equivalence classes with only one set bit are invariably a waste of SAT time
-        	if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1))
-        		continue;
+            int pop = popcount(cls.first);
+            // Equivalence classes with only one set bit are invariably a waste of SAT time
+            if (pop == 1 || pop == (8*sizeof(equiv_cls_t) - 1))
+                continue;
 
-        	log_debug("equivalence class: %016" PRIx64 "\n", cls.first);
+            log_debug("equivalence class: %016" PRIx64 "\n", cls.first);
             const pool<IdBit> &gold_bits = cls2bits.at(cls.first).first;
             const pool<InvBit> &gate_bits = cls2bits.at(cls.first).second;
             if (gold_bits.empty() || gate_bits.empty())
@@ -691,11 +691,11 @@ struct RecoverNamesWorker {
 
 struct RecoverNamesPass : public Pass {
     RecoverNamesPass() : Pass("recover_names", "Execute a lossy mapping command and recover original netnames") { }
-	bool formatted_help() override {
-		auto *help = PrettyHelp::get_current();
-		help->set_group("passes/opt");
-		return false;
-	}
+    bool formatted_help() override {
+        auto *help = PrettyHelp::get_current();
+        help->set_group("passes/opt");
+        return false;
+    }
     void help() override
     {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/quicklogic/ql_dsp_macc.cc b/techlibs/quicklogic/ql_dsp_macc.cc
index 083dc3ff1..742564f0e 100644
--- a/techlibs/quicklogic/ql_dsp_macc.cc
+++ b/techlibs/quicklogic/ql_dsp_macc.cc
@@ -182,32 +182,32 @@ static void create_ql_macc_dsp(ql_dsp_macc_pm &pm)
 }
 
 struct QlDspMacc : public Pass {
-	QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {}
+    QlDspMacc() : Pass("ql_dsp_macc", "infer QuickLogic multiplier-accumulator DSP cells") {}
 
-	void help() override
-	{
+    void help() override
+    {
         //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
-		log("\n");
-		log("    ql_dsp_macc [selection]\n");
+        log("\n");
+        log("    ql_dsp_macc [selection]\n");
         log("\n");
         log("This pass looks for a multiply-accumulate pattern based on which it infers a\n");
         log("QuickLogic DSP cell.\n");
-		log("\n");
-	}
+        log("\n");
+    }
 
-	void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
-	{
-		log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
+    void execute(std::vector<std::string> a_Args, RTLIL::Design *a_Design) override
+    {
+        log_header(a_Design, "Executing QL_DSP_MACC pass.\n");
 
-		size_t argidx;
-		for (argidx = 1; argidx < a_Args.size(); argidx++) {
-			break;
-		}
-		extra_args(a_Args, argidx, a_Design);
+        size_t argidx;
+        for (argidx = 1; argidx < a_Args.size(); argidx++) {
+            break;
+        }
+        extra_args(a_Args, argidx, a_Design);
 
-		for (auto module : a_Design->selected_modules())
-			ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
-	}
+        for (auto module : a_Design->selected_modules())
+            ql_dsp_macc_pm(module, module->selected_cells()).run_ql_dsp_macc(create_ql_macc_dsp);
+    }
 
 } QlDspMacc;