diff --git a/techlibs/achronix/synth_achronix.cc b/techlibs/achronix/synth_achronix.cc
index 0569f4092..4df9af423 100644
--- a/techlibs/achronix/synth_achronix.cc
+++ b/techlibs/achronix/synth_achronix.cc
@@ -28,6 +28,19 @@ PRIVATE_NAMESPACE_BEGIN
 struct SynthAchronixPass : public ScriptPass {
   SynthAchronixPass() : ScriptPass("synth_achronix", "synthesis for Achronix Speedster22i FPGAs.") { }
 
+	void on_register() override
+	{
+		target_register.emplace("achronix", Target{
+			"Achronix Speedster22i",
+			{
+				{"", { // default
+					"",
+					{"+/achronix/speedster22i/cells_sim.v"}
+				}}
+			}
+		});
+	}
+
   void help() override
   {
     //   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc
index 2dff87308..f724d2340 100644
--- a/techlibs/analogdevices/synth_analogdevices.cc
+++ b/techlibs/analogdevices/synth_analogdevices.cc
@@ -34,6 +34,15 @@ struct SynthAnalogDevicesPass : public ScriptPass
 	{
 		RTLIL::constpad["synth_analogdevices.abc9.W"] = "300"; // Number with which ABC will map a 6-input gate
 								    // to one LUT6 (instead of a LUT5 + LUT2)
+		target_register.emplace("analogdevices", Target{
+			"Analog Devices",
+			{
+				{"", { // default
+					"",
+					{"+/analogdevices/cells_sim.v"}
+				}}
+			}
+		});
 	}
 
 	void help() override
diff --git a/techlibs/anlogic/synth_anlogic.cc b/techlibs/anlogic/synth_anlogic.cc
index e9dfb6977..0701898cc 100644
--- a/techlibs/anlogic/synth_anlogic.cc
+++ b/techlibs/anlogic/synth_anlogic.cc
@@ -30,6 +30,19 @@ struct SynthAnlogicPass : public ScriptPass
 {
 	SynthAnlogicPass() : ScriptPass("synth_anlogic", "synthesis for Anlogic FPGAs") { }
 
+	void on_register() override
+	{
+		target_register.emplace("anlogic", Target{
+			"Anlogic",
+			{
+				{"", { // default
+					"",
+					{"+/anlogic/cells_sim.v", "+/anlogic/eagle_bb.v"}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc
index ca50f1e37..344eeb43a 100644
--- a/techlibs/efinix/synth_efinix.cc
+++ b/techlibs/efinix/synth_efinix.cc
@@ -31,6 +31,19 @@ struct SynthEfinixPass : public ScriptPass
 {
 	SynthEfinixPass() : ScriptPass("synth_efinix", "synthesis for Efinix FPGAs") { }
 
+	void on_register() override
+	{
+		target_register.emplace("efinix", Target{
+			"Efinix",
+			{
+				{"", { // default
+					"",
+					{"+/efinix/cells_sim.v"}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/gatemate/synth_gatemate.cc b/techlibs/gatemate/synth_gatemate.cc
index 8219699fc..772ec8996 100644
--- a/techlibs/gatemate/synth_gatemate.cc
+++ b/techlibs/gatemate/synth_gatemate.cc
@@ -29,6 +29,19 @@ struct SynthGateMatePass : public ScriptPass
 {
 	SynthGateMatePass() : ScriptPass("synth_gatemate", "synthesis for Cologne Chip GateMate FPGAs") { }
 
+	void on_register() override
+	{
+		target_register.emplace("gatemate", Target{
+			"Cologne Chip GateMate",
+			{
+				{"", { // default
+					"",
+					{"+/gatemate/cells_sim.v", "+/gatemate/cells_bb.v"}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index 89ab331b4..a429ba367 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -29,6 +29,27 @@ struct SynthGowinPass : public ScriptPass
 {
 	SynthGowinPass() : ScriptPass("synth_gowin", "synthesis for Gowin FPGAs") { }
 
+	void on_register() override
+	{
+		target_register.emplace("gowin", Target{
+			"Gowin",
+			{
+				{"gw1n", {
+					"GW1N",
+					{"+/gowin/cells_sim.v", "+/gowin/cells_xtra_gw1n.v"}
+				}},
+				{"gw2a", {
+					"GW2A",
+					{"+/gowin/cells_sim.v", "+/gowin/cells_xtra_gw2a.v"}
+				}},
+				{"gw5a", {
+					"GW5A",
+					{"+/gowin/cells_sim.v", "+/gowin/cells_xtra_gw5a.v"}
+				}}
+			}
+		});
+	}
+
 	struct DSPRule {
 		int a_maxwidth;
 		int b_maxwidth;
diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc
index 3a229fbf7..e6783c425 100644
--- a/techlibs/intel/synth_intel.cc
+++ b/techlibs/intel/synth_intel.cc
@@ -29,6 +29,31 @@ PRIVATE_NAMESPACE_BEGIN
 struct SynthIntelPass : public ScriptPass {
 	SynthIntelPass() : ScriptPass("synth_intel", "synthesis for Intel (Altera) FPGAs.") { experimental(); }
 
+	void on_register() override
+	{
+		target_register.emplace("intel", Target{
+			"Intel (Altera)",
+			{
+				{"max10", {
+					"MAX 10",
+					{"+/intel/max10/cells_sim.v", "+/intel/common/m9k_bb.v", "+/intel/common/altpll_bb.v"}
+				}},
+				{"cycloneiv", {
+					"Cyclone IV",
+					{"+/intel/cycloneiv/cells_sim.v", "+/intel/common/m9k_bb.v", "+/intel/common/altpll_bb.v"}
+				}},
+				{"cycloneive", {
+					"Cyclone IVe",
+					{"+/intel/cycloneive/cells_sim.v", "+/intel/common/m9k_bb.v", "+/intel/common/altpll_bb.v"}
+				}},
+				{"cyclone10lp", {
+					"Cyclone 10LP",
+					{"+/intel/cyclone10lp/cells_sim.v", "+/intel/common/m9k_bb.v", "+/intel/common/altpll_bb.v"}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc
index a859544cf..6855060f7 100644
--- a/techlibs/intel_alm/synth_intel_alm.cc
+++ b/techlibs/intel_alm/synth_intel_alm.cc
@@ -29,6 +29,25 @@ PRIVATE_NAMESPACE_BEGIN
 struct SynthIntelALMPass : public ScriptPass {
 	SynthIntelALMPass() : ScriptPass("synth_intel_alm", "synthesis for ALM-based Intel (Altera) FPGAs.") {}
 
+	void on_register() override
+	{
+		target_register.emplace("intel_alm", Target{
+			"Intel (Altera) ALM-based",
+			{
+				{"cyclonev", {
+					"Cyclone V",
+					{ "+/intel_alm/cyclonev/cells_sim.v",
+					  "+/intel_alm/common/alm_sim.v",
+					  "+/intel_alm/common/dff_sim.v",
+					  "+/intel_alm/common/dsp_sim.v",
+					  "+/intel_alm/common/mem_sim.v",
+					  "+/intel_alm/common/misc_sim.v",
+					}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc
index 331c6ca60..160330223 100644
--- a/techlibs/microchip/synth_microchip.cc
+++ b/techlibs/microchip/synth_microchip.cc
@@ -27,6 +27,19 @@ PRIVATE_NAMESPACE_BEGIN
 struct SynthMicrochipPass : public ScriptPass {
 	SynthMicrochipPass() : ScriptPass("synth_microchip", "synthesis for Microchip FPGAs") {}
 
+	void on_register() override
+	{
+		target_register.emplace("microchip", Target{
+			"Microchip",
+			{
+				{"polarfire", {
+					"PolarFire",
+					{"+/microchip/cells_sim.v"}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc
index d6134d2d2..d2d162df4 100644
--- a/techlibs/nanoxplore/synth_nanoxplore.cc
+++ b/techlibs/nanoxplore/synth_nanoxplore.cc
@@ -34,6 +34,24 @@ struct SynthNanoXplorePass : public ScriptPass
 	void on_register() override
 	{
 		RTLIL::constpad["synth_nanoxplore.abc9.W"] = "300";
+
+		target_register.emplace("nanoxplore", Target{
+			"NanoXplore",
+			{
+				{"medium", {
+					"NG-Medium",
+					{"+/nanoxplore/cells_sim.v", "+/nanoxplore/cells_sim_m.v", "+/nanoxplore/cells_bb_m.v"}
+				}},
+				{"large", {
+					"NG-Large",
+					{"+/nanoxplore/cells_sim.v", "+/nanoxplore/cells_sim_l.v", "+/nanoxplore/cells_bb_l.v"}
+				}},
+				{"ultra", {
+					"NG-Ultra",
+					{"+/nanoxplore/cells_sim.v", "+/nanoxplore/cells_sim_u.v", "+/nanoxplore/cells_bb_u.v"}
+				}}
+			}
+		});
 	}
 
 	void help() override
diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc
index cf827fe3d..5841125e1 100644
--- a/techlibs/quicklogic/synth_quicklogic.cc
+++ b/techlibs/quicklogic/synth_quicklogic.cc
@@ -30,6 +30,28 @@ struct SynthQuickLogicPass : public ScriptPass {
 
 	SynthQuickLogicPass() : ScriptPass("synth_quicklogic", "Synthesis for QuickLogic FPGAs") {}
 
+	void on_register() override
+	{
+		target_register.emplace("quicklogic", Target{
+			"QuickLogic",
+			{
+				{"pp3", {
+					"PolarPro 3",
+					{"+/quicklogic/common/cells_sim.v", "+/quicklogic/pp3/cells_sim.v"}
+				}},
+				{"qlf_k6n10f", {
+					"K6N10f",
+					{"+/quicklogic/common/cells_sim.v",
+					 "+/quicklogic/qlf_k6n10f/cells_sim.v",
+					 "+/quicklogic/qlf_k6n10f/brams_sim.v",
+					 "+/quicklogic/qlf_k6n10f/bram_types_sim.v",
+					 "+/quicklogic/qlf_k6n10f/dsp_sim.v",
+					}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/sf2/synth_sf2.cc b/techlibs/sf2/synth_sf2.cc
index 2dd7d6267..7cf511e92 100644
--- a/techlibs/sf2/synth_sf2.cc
+++ b/techlibs/sf2/synth_sf2.cc
@@ -29,6 +29,19 @@ struct SynthSf2Pass : public ScriptPass
 {
 	SynthSf2Pass() : ScriptPass("synth_sf2", "synthesis for SmartFusion2 and IGLOO2 FPGAs") { }
 
+	void on_register() override
+	{
+		target_register.emplace("sf2", Target{
+			"Microchip SmartFusion2",
+			{
+				{"", { // default
+					"",
+					{"+/sf2/cells_sim.v"}
+				}}
+			}
+		});
+	}
+
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc
index c669c87ee..0c53d2772 100644
--- a/techlibs/xilinx/synth_xilinx.cc
+++ b/techlibs/xilinx/synth_xilinx.cc
@@ -34,6 +34,15 @@ struct SynthXilinxPass : public ScriptPass
 	{
 		RTLIL::constpad["synth_xilinx.abc9.xc7.W"] = "300"; // Number with which ABC will map a 6-input gate
 								    // to one LUT6 (instead of a LUT5 + LUT2)
+		target_register.emplace("xilinx", Target{
+			"Xilinx",
+			{
+				{"", { // default
+					"",
+					{"+/xilinx/cells_sim.v", "+/xilinx/cells_xtra.v"}
+				}}
+			}
+		});
 	}
 
 	void help() override