diff --git a/tests/abc_new/init_attr.ys b/tests/abc_new/init_attr.ys
new file mode 100644
index 000000000..f5d204308
--- /dev/null
+++ b/tests/abc_new/init_attr.ys
@@ -0,0 +1,20 @@
+# init values on flop outputs survive
+read_verilog <<EOT
+module top(input clk, a, output y);
+	reg q = 1'b1;
+	reg [1:0] r = 2'b10;
+	always @(posedge clk) begin q <= a ^ q; r <= r + {1'b0, q}; end
+	assign y = q & ^r;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+techmap
+select -assert-count 2 a:init
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-count 1 w:q a:init %i
+select -assert-count 1 w:r a:init %i
+select -assert-none t:$_*_ t:$_DFF_P_ %d
+check -assert
diff --git a/tests/abc_new/latch_boundary.ys b/tests/abc_new/latch_boundary.ys
new file mode 100644
index 000000000..d6a47ae4a
--- /dev/null
+++ b/tests/abc_new/latch_boundary.ys
@@ -0,0 +1,17 @@
+# latches stay as boundary cells
+read_verilog <<EOT
+module top(input en, input [3:0] d, output reg [3:0] q, output y);
+	always @* if (en) q = d ^ {d[2:0], d[3]};
+	assign y = ^q;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+techmap
+select -assert-count 4 t:$_DLATCH_P_
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-count 4 t:$_DLATCH_P_
+select -assert-none t:$_*_ t:$_DLATCH_P_ %d
+check -assert
diff --git a/tests/abc_new/multiclk_equiv.ys b/tests/abc_new/multiclk_equiv.ys
new file mode 100644
index 000000000..fd6525a9c
--- /dev/null
+++ b/tests/abc_new/multiclk_equiv.ys
@@ -0,0 +1,32 @@
+# two clocks, negedge, async reset
+read_verilog <<EOT
+module top(input c1, c2, rst_n, input [3:0] d, output [3:0] y);
+	reg [3:0] p, n;
+	always @(posedge c1, negedge rst_n) if (!rst_n) p <= 0; else p <= d + p;
+	always @(negedge c2) n <= p ^ d;
+	assign y = p & n;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+design -save gold
+synth -run fine:
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-count 4 t:$_DFF_PN0_
+select -assert-count 4 t:$_DFF_N_
+select -assert-none t:$_*_ t:$_DFF_* %d
+check -assert
+read_verilog openroad/cells_sim.v
+proc
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+async2sync
+equiv_make gold gate equiv
+equiv_simple -seq 5
+equiv_induct -seq 5
+equiv_status -assert
diff --git a/tests/abc_new/tribuf_boundary.ys b/tests/abc_new/tribuf_boundary.ys
new file mode 100644
index 000000000..46b74a415
--- /dev/null
+++ b/tests/abc_new/tribuf_boundary.ys
@@ -0,0 +1,18 @@
+# $_TBUF_ stay as boundary cells
+read_verilog <<EOT
+module top(input en, input [3:0] a, b, output [3:0] y, inout [3:0] io);
+	assign y = en ? a & b : 4'bz;
+	assign io = en ? a : 4'bz;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+opt
+tribuf
+techmap
+select -assert-count 8 t:$_TBUF_
+abc_new -liberty openroad/cm_test_cells.lib
+select -assert-count 8 t:$_TBUF_
+select -assert-none t:$_*_ t:$_TBUF_ %d
+check -assert