From 650c636d3955a00b783541a6f030e1cc9155f379 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Wed, 18 Feb 2026 01:12:35 -0800
Subject: [PATCH] Fixups

---
 tests/memlib/generate.py     |   8 +-
 tests/silimate/mux_andnot.ys | 222 -----------------------------------
 tests/silimate/mux_ornot.ys  | 222 -----------------------------------
 tests/unit/Makefile          |   3 +-
 4 files changed, 6 insertions(+), 449 deletions(-)
 delete mode 100644 tests/silimate/mux_andnot.ys
 delete mode 100644 tests/silimate/mux_ornot.ys

diff --git a/tests/memlib/generate.py b/tests/memlib/generate.py
index c52114aeb..46eff6b43 100644
--- a/tests/memlib/generate.py
+++ b/tests/memlib/generate.py
@@ -1428,7 +1428,7 @@ endmodule
 for (testname, 		reset_gate, 	rdwr,  clk_en, add_logic) in [
 	("no_reset", 	"", 		"old", False, 	0),
 	("gclken", 	"rst", 		"old", False, 	0),
-	("ungated", 	"ungated", 	"old", False, 	2), # muxes wren with rst
+	("ungated", 	"ungated", 	"old", False, 	1), # muxes wren with rst
 	("gclken_ce", 	"rst", 		"old", True, 	3), # AND to simulate CLK_EN
 	("grden", 	"rden && rst", 	"old", False, 	1), # selects _clken, simulates _rden
 	("grden_ce", 	"rden && rst", 	"old", True, 	4), # both of the above
@@ -1473,9 +1473,9 @@ end"""
 for (testname, 			reset_gate, 	defs, 		rdwr,  add_logic) in [
 	("wr_byte",		"", 	["USE_SRST_BLOCKING"],	"old", 0),
 	("trans_byte",		"", 	["USE_SRST_BLOCKING"],	"new", 0),
-	("wr_rst_byte",		"rst", 	["USE_SRST"],		"old", 3), # expected mux to emulate blocking
-	("rst_wr_byte",		"rst", 	["USE_SRST_BLOCKING"],	"old", 3), # should use hardware blocking, doesn't
-	("rdenrst_wr_byte", 	"rden && rst", ["USE_SRST"],	"old", 4),
+	("wr_rst_byte",		"rst", 	["USE_SRST"],		"old", 2), # expected mux to emulate blocking
+	("rst_wr_byte",		"rst", 	["USE_SRST_BLOCKING"],	"old", 2), # should use hardware blocking, doesn't
+	("rdenrst_wr_byte", 	"rden && rst", ["USE_SRST"],	"old", 3),
 ]:
 	wordsloop = "for (i=0; i<WORDS; i=i+1)"
 	if rdwr == "old":
diff --git a/tests/silimate/mux_andnot.ys b/tests/silimate/mux_andnot.ys
deleted file mode 100644
index f3bac89a1..000000000
--- a/tests/silimate/mux_andnot.ys
+++ /dev/null
@@ -1,222 +0,0 @@
-log -header "Simple positive case"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? 1'b0 : a;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$and
-select -assert-count 1 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "Case with inverted a"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? 1'b0 : ~a;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$and
-select -assert-count 2 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "Case with inverted s"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = ~s ? a : 1'b0;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-# Did not include check for not count since we have an unassigned ~s wire
-design -load postopt
-select -assert-count 1 t:$and
-
-design -reset
-log -pop
-
-
-
-log -header "Nested AND gates"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire b,
-  input wire s,
-  output wire x
-);
-  assign x = s ? 1'b0 : a & b;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 2 t:$and
-select -assert-count 1 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "Nested OR gates"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire b,
-  input wire s,
-  output wire x
-);
-  assign x = s ? 1'b0 : a | b;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$and
-select -assert-count 1 t:$not
-select -assert-count 1 t:$or
-
-design -reset
-log -pop
-
-
-
-log -header "Nested muxes"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s1,
-  input wire s2,
-  output wire x
-);
-  assign x = s1 ? 1'b0 : (s2 ? 1'b0 : a);
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 2 t:$and
-select -assert-count 2 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "With constant propagation"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? 1'b0 : a & 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$and
-select -assert-count 1 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "With multibit constant"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? 32'b0 : a;
-endmodule
-EOF
-check -assert
-
-# Runs wreduce to reduce width of the constant before applying opt_expr
-# Without this line, this test case will not pass
-# Believe it is intended behavior to not optimize constant with more than one bit
-wreduce
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$and
-select -assert-count 1 t:$not
-
-design -reset
-log -pop
\ No newline at end of file
diff --git a/tests/silimate/mux_ornot.ys b/tests/silimate/mux_ornot.ys
deleted file mode 100644
index c6d153ba3..000000000
--- a/tests/silimate/mux_ornot.ys
+++ /dev/null
@@ -1,222 +0,0 @@
-log -header "Simple positive case"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? a : 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$or
-select -assert-count 1 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "Case with inverted a"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? ~a : 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$or
-select -assert-count 2 t:$not
-
-design -reset
-log -pop
-
-
-
-log -header "Case with inverted s"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = ~s ? 1'b1 : a;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-# Did not include check for not count since we have an unassigned ~s wire
-design -load postopt
-select -assert-count 1 t:$or
-
-design -reset
-log -pop
-
-
-
-log -header "Nested AND gates"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire b,
-  input wire s,
-  output wire x
-);
-  assign x = s ? a & b : 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$and
-select -assert-count 1 t:$not
-select -assert-count 1 t:$or
-
-design -reset
-log -pop
-
-
-
-log -header "Nested OR gates"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire b,
-  input wire s,
-  output wire x
-);
-  assign x = s ? a | b : 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$not
-select -assert-count 2 t:$or
-
-design -reset
-log -pop
-
-
-
-log -header "Nested muxes"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s1,
-  input wire s2,
-  output wire x
-);
-  assign x = s1 ? (s2 ? a : 1'b1) : 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 2 t:$not
-select -assert-count 2 t:$or
-
-design -reset
-log -pop
-
-
-
-log -header "With constant propagation"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? a & 1'b1 : 1'b1;
-endmodule
-EOF
-check -assert
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$not
-select -assert-count 1 t:$or
-
-design -reset
-log -pop
-
-
-
-log -header "With multibit constant"
-log -push
-design -reset
-read_verilog <<EOF
-module top (
-  input wire a,
-  input wire s,
-  output wire x
-);
-  assign x = s ? a : 32'b1;
-endmodule
-EOF
-check -assert
-
-# Runs wreduce to reduce width of the constant before applying opt_expr
-# Without this line, this test case will not pass
-# Believe it is intended behavior to not optimize constant with more than one bit
-wreduce
-
-# Check equivalence after opt_expr
-equiv_opt -assert opt_expr -mux_bool
-
-# Check final design has correct number of gates
-design -load postopt
-select -assert-count 1 t:$not
-select -assert-count 1 t:$or
-
-design -reset
-log -pop
\ No newline at end of file
diff --git a/tests/unit/Makefile b/tests/unit/Makefile
index e8f76cba9..1a436461d 100644
--- a/tests/unit/Makefile
+++ b/tests/unit/Makefile
@@ -16,7 +16,8 @@ else
   RPATH = -Wl,-rpath=$(ROOTPATH)
 endif
 
-EXTRAFLAGS := -lyosys -pthread
+PYTHON_CONFIG := $(shell if python3-config --embed --libs > /dev/null 2>&1; then echo "python3-config --embed"; else echo "python3-config"; fi)
+EXTRAFLAGS := -lyosys -pthread $(shell $(PYTHON_CONFIG) --ldflags --libs)
 
 MAKEFILE_DIR := $(dir $(abspath $(lastword $(MAKEFILE_LIST))))
 OBJTEST := $(MAKEFILE_DIR)objtest