From 62120bda0661102ba60801a871ab5c9f336a8aa6 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Fri, 5 Sep 2025 12:34:38 +0200
Subject: [PATCH] verilog: test cases that look like SVA labels #862

---
 tests/verilog/sva-in-case-expr.ys | 10 ++++++++++
 1 file changed, 10 insertions(+)
 create mode 100644 tests/verilog/sva-in-case-expr.ys

diff --git a/tests/verilog/sva-in-case-expr.ys b/tests/verilog/sva-in-case-expr.ys
new file mode 100644
index 000000000..e326e2bfb
--- /dev/null
+++ b/tests/verilog/sva-in-case-expr.ys
@@ -0,0 +1,10 @@
+read_verilog -sv <<EOT
+module test(input wire A);
+  localparam TEST = 1;
+  always_comb begin
+    case (A)
+      TEST: assert(1);
+    endcase
+  end
+endmodule
+EOT