diff --git a/tests/verilog/sva-in-case-expr.ys b/tests/verilog/sva-in-case-expr.ys
new file mode 100644
index 000000000..e326e2bfb
--- /dev/null
+++ b/tests/verilog/sva-in-case-expr.ys
@@ -0,0 +1,10 @@
+read_verilog -sv <<EOT
+module test(input wire A);
+  localparam TEST = 1;
+  always_comb begin
+    case (A)
+      TEST: assert(1);
+    endcase
+  end
+endmodule
+EOT