From cc4c9c4eba97e8727e5236d012c516c8fc3a3b24 Mon Sep 17 00:00:00 2001
From: William Zhu <williamzhu@Williams-MacBook-Pro.local>
Date: Thu, 27 Mar 2025 12:31:37 -0700
Subject: [PATCH 1/4] first tests for opt_expand

---
 Makefile                     |   1 +
 tests/silimate/opt_expand.ys | 225 +++++++++++++++++++++++++++++++++++
 tests/silimate/run-test.sh   |   6 +
 3 files changed, 232 insertions(+)
 create mode 100644 tests/silimate/opt_expand.ys
 create mode 100755 tests/silimate/run-test.sh

diff --git a/Makefile b/Makefile
index ec01e3394..132a872e2 100644
--- a/Makefile
+++ b/Makefile
@@ -946,6 +946,7 @@ SH_TEST_DIRS += tests/blif
 SH_TEST_DIRS += tests/memfile
 SH_TEST_DIRS += tests/fmt
 # SH_TEST_DIRS += tests/cxxrtl
+SH_TEST_DIRS += tests/silimate
 ifeq ($(ENABLE_FUNCTIONAL_TESTS),1)
 SH_TEST_DIRS += tests/functional
 endif
diff --git a/tests/silimate/opt_expand.ys b/tests/silimate/opt_expand.ys
new file mode 100644
index 000000000..d56078f1e
--- /dev/null
+++ b/tests/silimate/opt_expand.ys
@@ -0,0 +1,225 @@
+log -header "Simple positive case"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  wire m;
+
+  assign m = a | b;
+  assign x = m & c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+design -reset
+log -pop
+
+
+
+log -header "No intermediate wire: (a | b) & c"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  assign x = (a | b) & c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "No intermediate wire flipped: c & (a | b)"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  assign x = c & (a | b);
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Fanout from intermediate wire"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire m,
+  output wire x
+);
+  assign m = a | b;
+  assign x = c & m;
+
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested AND gate: ((a & b) | c) & d"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  output wire x
+);
+  assign x = ((a & b) | c) & d;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 3 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Nested OR gate: ((a | b) | c) & d"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  output wire x
+);
+  assign x = ((a | b) | c) & d;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 3 t:$and
+select -assert-count 2 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "With inverter: (~a | b) & c"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  output wire x
+);
+  assign x = (~a | b) & c;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "Deeper nesting: ((a | b) & (c | d)) & e"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  input wire e,
+  output wire x
+);
+  assign x = ((a | b) & (c | d)) & e;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 4 t:$and
+select -assert-count 2 t:$or
+
+design -reset
+log -pop
+
+
+
+log -header "More inputs and nesting: ((a | b | c) & (d | e)) & f"
+log -push
+design -reset
+read_verilog <<EOF
+module top (
+  input wire a,
+  input wire b,
+  input wire c,
+  input wire d,
+  input wire e,
+  input wire f,
+  output wire x
+);
+  assign x = ((a | b | c) & (d | e)) & f;
+endmodule
+EOF
+check -assert
+equiv_opt -assert opt_expand
+design -load postopt
+select -assert-count 4 t:$and
+select -assert-count 3 t:$or
+
+design -reset
+log -pop
\ No newline at end of file
diff --git a/tests/silimate/run-test.sh b/tests/silimate/run-test.sh
new file mode 100755
index 000000000..e9698386e
--- /dev/null
+++ b/tests/silimate/run-test.sh
@@ -0,0 +1,6 @@
+#!/usr/bin/env bash
+set -e
+for x in *.ys; do
+  echo "Running $x.."
+  ../../yosys -ql ${x%.ys}.log $x
+done

From a03553b54e3acfd8aa41945e70707a4fbdc3c9f7 Mon Sep 17 00:00:00 2001
From: William Zhu <williamzhu@Williams-MacBook-Pro.local>
Date: Thu, 27 Mar 2025 12:36:15 -0700
Subject: [PATCH 2/4] added some extra comments and checks

---
 tests/silimate/opt_expand.ys | 73 ++++++++++++++++++++++++++++++++++++
 1 file changed, 73 insertions(+)

diff --git a/tests/silimate/opt_expand.ys b/tests/silimate/opt_expand.ys
index d56078f1e..e935d83aa 100644
--- a/tests/silimate/opt_expand.ys
+++ b/tests/silimate/opt_expand.ys
@@ -15,10 +15,19 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
+
 design -reset
 log -pop
 
@@ -38,7 +47,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -62,7 +79,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -89,7 +114,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 1 t:$and
 select -assert-count 1 t:$or
@@ -114,7 +147,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 2 t:$and
+select -assert-count 1 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 3 t:$and
 select -assert-count 1 t:$or
@@ -139,7 +180,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 1 t:$and
+select -assert-count 2 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 3 t:$and
 select -assert-count 2 t:$or
@@ -163,7 +212,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 1 t:$and
+select -assert-count 1 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -189,7 +246,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 2 t:$and
+select -assert-count 2 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 4 t:$and
 select -assert-count 2 t:$or
@@ -216,7 +281,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Ensure original design only has correct number of gates
+select -assert-count 2 t:$and
+select -assert-count 3 t:$or
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 4 t:$and
 select -assert-count 3 t:$or

From 3b8330c44ff2812decad7979702083958b2407e2 Mon Sep 17 00:00:00 2001
From: William Zhu <williamzhu@Williams-MacBook-Pro.local>
Date: Thu, 27 Mar 2025 12:40:21 -0700
Subject: [PATCH 3/4] reverted some extra unneccessary checks

---
 tests/silimate/opt_expand.ys | 73 ------------------------------------
 1 file changed, 73 deletions(-)

diff --git a/tests/silimate/opt_expand.ys b/tests/silimate/opt_expand.ys
index e935d83aa..d56078f1e 100644
--- a/tests/silimate/opt_expand.ys
+++ b/tests/silimate/opt_expand.ys
@@ -15,19 +15,10 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 1 t:$and
-select -assert-count 1 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
-
 design -reset
 log -pop
 
@@ -47,15 +38,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 1 t:$and
-select -assert-count 1 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -79,15 +62,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 1 t:$and
-select -assert-count 1 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -114,15 +89,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 1 t:$and
-select -assert-count 1 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 1 t:$and
 select -assert-count 1 t:$or
@@ -147,15 +114,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 2 t:$and
-select -assert-count 1 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 3 t:$and
 select -assert-count 1 t:$or
@@ -180,15 +139,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 1 t:$and
-select -assert-count 2 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 3 t:$and
 select -assert-count 2 t:$or
@@ -212,15 +163,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 1 t:$and
-select -assert-count 1 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -246,15 +189,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 2 t:$and
-select -assert-count 2 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 4 t:$and
 select -assert-count 2 t:$or
@@ -281,15 +216,7 @@ module top (
 endmodule
 EOF
 check -assert
-
-# Ensure original design only has correct number of gates
-select -assert-count 2 t:$and
-select -assert-count 3 t:$or
-
-# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
-
-# Check final design has correct number of gates
 design -load postopt
 select -assert-count 4 t:$and
 select -assert-count 3 t:$or

From d493a55025c4defe19090e0ae38cc0290a9c9101 Mon Sep 17 00:00:00 2001
From: William Zhu <williamzhu@Williams-MacBook-Pro.local>
Date: Thu, 27 Mar 2025 12:40:41 -0700
Subject: [PATCH 4/4] forgot to add some things to previous commit

---
 tests/silimate/opt_expand.ys | 37 ++++++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/tests/silimate/opt_expand.ys b/tests/silimate/opt_expand.ys
index d56078f1e..420785300 100644
--- a/tests/silimate/opt_expand.ys
+++ b/tests/silimate/opt_expand.ys
@@ -15,10 +15,15 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
+
 design -reset
 log -pop
 
@@ -38,7 +43,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -62,7 +71,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -89,7 +102,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 1 t:$and
 select -assert-count 1 t:$or
@@ -114,7 +131,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 3 t:$and
 select -assert-count 1 t:$or
@@ -139,7 +160,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 3 t:$and
 select -assert-count 2 t:$or
@@ -163,7 +188,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 2 t:$and
 select -assert-count 1 t:$or
@@ -189,7 +218,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 4 t:$and
 select -assert-count 2 t:$or
@@ -216,7 +249,11 @@ module top (
 endmodule
 EOF
 check -assert
+
+# Check equivalence after opt_expand
 equiv_opt -assert opt_expand
+
+# Check final design has correct number of gates
 design -load postopt
 select -assert-count 4 t:$and
 select -assert-count 3 t:$or