From 5e2989b44d771cbc132625a63b35219b5b21e61e Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 27 Mar 2026 08:27:52 +0100 Subject: [PATCH] wip --- tests/arch/xilinx/macc.sh | 8 ++++---- tests/arch/xilinx/tribuf.sh | 4 ++-- tests/bram/generate_mk.py | 2 +- tests/bram/run-single.sh | 4 ++-- tests/gen_tests_makefile.py | 4 ++-- tests/rtlil/roundtrip-design.sh | 5 ++--- tests/rtlil/roundtrip-text.sh | 8 +++----- tests/sdc/side-effects.sh | 2 +- tests/sdc/unknown-getter.sh | 2 +- tests/techmap/bug5495.sh | 2 +- tests/techmap/recursive_runtest.sh | 2 +- tests/tools/autotest.sh | 6 +++--- tests/various/async.sh | 10 +++++----- tests/various/chparam.sh | 8 ++++---- tests/various/clk2fflogic_effects.sh | 4 ++-- tests/various/hierarchy.sh | 6 +++--- tests/various/logger_cmd_error.sh | 2 +- tests/various/logger_fail.sh | 2 +- tests/various/plugin.sh | 4 ++-- tests/various/sv_implicit_ports.sh | 20 ++++++++++---------- tests/various/svalways.sh | 10 +++++----- tests/verilog/dynamic_range_lhs.sh | 2 +- tests/verilog/local_include.sh | 2 +- 23 files changed, 58 insertions(+), 61 deletions(-) diff --git a/tests/arch/xilinx/macc.sh b/tests/arch/xilinx/macc.sh index 58b97b646..ad4cc2396 100644 --- a/tests/arch/xilinx/macc.sh +++ b/tests/arch/xilinx/macc.sh @@ -1,6 +1,6 @@ -../../../yosys -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v -iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v +$YOSYS -qp "synth_xilinx -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v +$IVERILOG -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc -../../../yosys -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v -iverilog -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v +$YOSYS -qp "synth_xilinx -family xc6s -top macc2; rename -top macc2_uut" -o macc_uut.v macc.v +$IVERILOG -o test_macc macc_tb.v macc_uut.v macc.v ../../../techlibs/xilinx/cells_sim.v vvp -N ./test_macc diff --git a/tests/arch/xilinx/tribuf.sh b/tests/arch/xilinx/tribuf.sh index eca33e490..16b5a7fe3 100644 --- a/tests/arch/xilinx/tribuf.sh +++ b/tests/arch/xilinx/tribuf.sh @@ -1,5 +1,5 @@ -../../../yosys -f verilog -qp "synth_xilinx" ../common/tribuf.v -../../../yosys -f verilog -qp "synth_xilinx -iopad; \ +$YOSYS -f verilog -qp "synth_xilinx" ../common/tribuf.v +$YOSYS -f verilog -qp "synth_xilinx -iopad; \ select -assert-count 2 t:IBUF; \ select -assert-count 1 t:INV; \ select -assert-count 1 t:OBUFT" ../common/tribuf.v diff --git a/tests/bram/generate_mk.py b/tests/bram/generate_mk.py index 09f5c650b..f52d92416 100644 --- a/tests/bram/generate_mk.py +++ b/tests/bram/generate_mk.py @@ -320,7 +320,7 @@ def create_tests(): if i != j: gen_tests_makefile.generate_cmd_test( f"bram_{i}_{j}", - f"bash run-single.sh {i} {j}" + f"YOSYS=$(YOSYS) IVERILOG=iverilog bash run-single.sh {i} {j}" ) gen_tests_makefile.generate_custom(create_tests) diff --git a/tests/bram/run-single.sh b/tests/bram/run-single.sh index 358423f32..825adc2df 100644 --- a/tests/bram/run-single.sh +++ b/tests/bram/run-single.sh @@ -1,8 +1,8 @@ #!/usr/bin/env bash set -e -../../yosys -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ +$YOSYS -qq -f verilog -p "proc; opt; memory -nomap -bram temp/brams_${2}.txt; opt -fast -full" \ -l temp/synth_${1}_${2}.log -o temp/synth_${1}_${2}.v temp/brams_${1}.v -iverilog -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ +$IVERILOG -Dvcd_file=\"temp/tb_${1}_${2}.vcd\" -DSIMLIB_MEMDELAY=1 -o temp/tb_${1}_${2}.tb temp/brams_${1}_tb.v \ temp/brams_${1}_ref.v temp/synth_${1}_${2}.v temp/brams_${2}.v ../../techlibs/common/simlib.v temp/tb_${1}_${2}.tb > temp/tb_${1}_${2}.txt if grep -q ERROR temp/tb_${1}_${2}.txt; then diff --git a/tests/gen_tests_makefile.py b/tests/gen_tests_makefile.py index 38596f63b..289c99cf7 100644 --- a/tests/gen_tests_makefile.py +++ b/tests/gen_tests_makefile.py @@ -47,7 +47,7 @@ def generate_sv_test(sv_file, yosys_args="", commands=""): generate_target(sv_file, cmd) def generate_bash_test(sh_file, commands=""): - cmd = f"bash -v {sh_file} >{sh_file}.err 2>&1 && mv {sh_file}.err {sh_file}.log" + cmd = f"YOSYS=$(YOSYS) IVERILOG=iverilog bash -v {sh_file} >{sh_file}.err 2>&1 && mv {sh_file}.err {sh_file}.log" if commands: cmd += f"; \\\n{commands}" generate_target(sh_file, cmd) @@ -125,7 +125,7 @@ def generate_custom(callback, extra=None): callback() def generate_autotest_file(test_file, commands): - cmd = f"../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}" + cmd = f"YOSYS=$(YOSYS) IVERILOG=iverilog ../tools/autotest.sh -G -j ${{SEEDOPT}} ${{EXTRA_FLAGS}} {test_file}; \\\n{commands}" generate_target(test_file, cmd) def generate_autotest(pattern, extra_flags, cmds=""): diff --git a/tests/rtlil/roundtrip-design.sh b/tests/rtlil/roundtrip-design.sh index 018e363c7..bbbf8e7d3 100644 --- a/tests/rtlil/roundtrip-design.sh +++ b/tests/rtlil/roundtrip-design.sh @@ -1,10 +1,9 @@ set -euo pipefail -YS=../../yosys mkdir -p temp -$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" +$YOSYS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-push.il; design -push; design -pop; write_rtlil temp/roundtrip-design-pop.il" diff temp/roundtrip-design-push.il temp/roundtrip-design-pop.il -$YS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" +$YOSYS -p "read_verilog -sv everything.v; write_rtlil temp/roundtrip-design-save.il; design -save foo; design -load foo; write_rtlil temp/roundtrip-design-load.il" diff temp/roundtrip-design-save.il temp/roundtrip-design-load.il diff --git a/tests/rtlil/roundtrip-text.sh b/tests/rtlil/roundtrip-text.sh index 35417cff7..2c9fecd6b 100644 --- a/tests/rtlil/roundtrip-text.sh +++ b/tests/rtlil/roundtrip-text.sh @@ -1,6 +1,4 @@ set -euo pipefail -YS=../../yosys - mkdir -p temp # non-POSIX sed -i inconsistency workaround @@ -11,7 +9,7 @@ remove_empty_lines() { } # write_rtlil and dump are equivalent -$YS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" +$YOSYS -p "read_verilog -sv everything.v; copy alu zzz; proc zzz; dump -o temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.write.il" remove_empty_lines temp/roundtrip-text.dump.il remove_empty_lines temp/roundtrip-text.write.il # Trim first line ("Generated by Yosys ...") @@ -19,13 +17,13 @@ tail -n +2 temp/roundtrip-text.write.il > temp/roundtrip-text.write-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.write-nogen.il # Loading and writing it out again doesn't change the RTLIL -$YS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" +$YOSYS -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload.il" remove_empty_lines temp/roundtrip-text.reload.il tail -n +2 temp/roundtrip-text.reload.il > temp/roundtrip-text.reload-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-nogen.il # Hashing differences don't change the RTLIL -$YS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" +$YOSYS --hash-seed=2345678 -p "read_rtlil temp/roundtrip-text.dump.il; write_rtlil temp/roundtrip-text.reload-hash.il" remove_empty_lines temp/roundtrip-text.reload-hash.il tail -n +2 temp/roundtrip-text.reload-hash.il > temp/roundtrip-text.reload-hash-nogen.il diff temp/roundtrip-text.dump.il temp/roundtrip-text.reload-hash-nogen.il diff --git a/tests/sdc/side-effects.sh b/tests/sdc/side-effects.sh index 88d6154a1..209d75bbc 100755 --- a/tests/sdc/side-effects.sh +++ b/tests/sdc/side-effects.sh @@ -1,4 +1,4 @@ #!/usr/bin/env bash -../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something: +$YOSYS -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc side-effects.sdc' | grep 'This should print something: YOSYS_SDC_MAGIC_NODE_0' diff --git a/tests/sdc/unknown-getter.sh b/tests/sdc/unknown-getter.sh index 9038834c6..a96a16a19 100755 --- a/tests/sdc/unknown-getter.sh +++ b/tests/sdc/unknown-getter.sh @@ -2,4 +2,4 @@ set -euo pipefail -! ../../yosys -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter' +! $YOSYS -p 'read_verilog alu_sub.v; proc; hierarchy -auto-top; sdc get_foo.sdc' 2>&1 | grep 'Unknown getter' diff --git a/tests/techmap/bug5495.sh b/tests/techmap/bug5495.sh index 476727755..ac11da0c2 100755 --- a/tests/techmap/bug5495.sh +++ b/tests/techmap/bug5495.sh @@ -5,7 +5,7 @@ if ! which timeout ; then exit 0 fi -if ! timeout 10 ../../yosys bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then +if ! timeout 10 $YOSYS bug5495.v -p 'hierarchy; techmap; abc -script bug5495.abc' ; then echo "Yosys failed to complete" exit 1 fi diff --git a/tests/techmap/recursive_runtest.sh b/tests/techmap/recursive_runtest.sh index 564d678fa..7d9b0575d 100644 --- a/tests/techmap/recursive_runtest.sh +++ b/tests/techmap/recursive_runtest.sh @@ -1,3 +1,3 @@ set -e -../../yosys -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' +$YOSYS -p 'read_verilog recursive.v; hierarchy -top top; techmap -map recursive_map.v -max_iter 1; select -assert-count 2 t:sub; select -assert-count 2 t:bar' diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index e19a8d5af..bdc39ce5a 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -157,7 +157,7 @@ do fi if [ ! -f ../${bn}_tb.v ]; then - "$toolsdir"/../../yosys -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} + $YOSYS -f "$frontend $include_opts -D_AUTOTB" -b "test_autotb $autotb_opts" -o ${bn}_tb.v ${bn}_ref.${refext} else cp ../${bn}_tb.v ${bn}_tb.v fi @@ -171,7 +171,7 @@ do test_count=0 test_passes() { - "$toolsdir"/../../yosys -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" + $YOSYS -b "verilog $backend_opts" -o ${bn}_syn${test_count}.v "$@" touch ${bn}.iverilog compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v "${libs[@]}" \ @@ -201,7 +201,7 @@ do test_passes -f "$frontend $include_opts" -p "hierarchy; synth -run coarse; techmap; opt; abc -dff" ${bn}_ref.${refext} if [ -n "$firrtl2verilog" ]; then if test -z "$xfirrtl" || ! grep "$fn" "$xfirrtl" ; then - "$toolsdir"/../../yosys -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} + $YOSYS -b "firrtl" -o ${bn}_ref.fir -f "$frontend $include_opts" -p "prep; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine; pmuxtree" ${bn}_ref.${refext} $firrtl2verilog -i ${bn}_ref.fir -o ${bn}_ref.fir.v test_passes -f "$frontend $include_opts" -p "hierarchy; proc; opt -nodffe -nosdff; fsm; opt; memory; opt -full -fine" ${bn}_ref.fir.v fi diff --git a/tests/various/async.sh b/tests/various/async.sh index 9d956c1cd..08b490b4e 100644 --- a/tests/various/async.sh +++ b/tests/various/async.sh @@ -1,10 +1,10 @@ #!/usr/bin/env bash set -ex -../../yosys -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v -../../yosys -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v -../../yosys -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v -../../yosys -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v -iverilog -o async_sim -DTESTBENCH async.v async_???.v +$YOSYS -q -o async_syn.v -r uut -p 'synth; rename uut syn' async.v +$YOSYS -q -o async_prp.v -r uut -p 'prep; rename uut prp' async.v +$YOSYS -q -o async_a2s.v -r uut -p 'prep; async2sync; rename uut a2s' async.v +$YOSYS -q -o async_ffl.v -r uut -p 'prep; clk2fflogic; rename uut ffl' async.v +$IVERILOG -o async_sim -DTESTBENCH async.v async_???.v vvp -N async_sim > async.out tail async.out grep PASS async.out diff --git a/tests/various/chparam.sh b/tests/various/chparam.sh index 0c237112e..c39cfe75f 100644 --- a/tests/various/chparam.sh +++ b/tests/various/chparam.sh @@ -35,18 +35,18 @@ module top #( endmodule EOT -if ../../yosys -q -p 'verific -sv chparam1.sv'; then - ../../yosys -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ +if $YOSYS -q -p 'verific -sv chparam1.sv'; then + $YOSYS -q -p 'verific -sv chparam1.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' - ../../yosys -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ + $YOSYS -q -p 'verific -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' fi -../../yosys -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ +$YOSYS -q -p 'read_verilog -sv chparam2.sv; hierarchy -chparam X 123123123 -top top; prep -flatten' \ -p 'async2sync' \ -p 'sat -verify -prove-asserts -show-ports -set din[0] 1' \ -p 'sat -falsify -prove-asserts -show-ports -set din[0] 0' diff --git a/tests/various/clk2fflogic_effects.sh b/tests/various/clk2fflogic_effects.sh index 0d133ffdd..1bd87ab68 100755 --- a/tests/various/clk2fflogic_effects.sh +++ b/tests/various/clk2fflogic_effects.sh @@ -3,14 +3,14 @@ set -e # TODO: when sim gets native $check support, remove the -DNO_ASSERT here echo Running yosys sim -../../yosys -q -p " +$YOSYS -q -p " read_verilog -formal -DNO_ASSERT clk2fflogic_effects.sv hierarchy -top top; proc;; tee -q -o clk2fflogic_effects.sim.log sim -q -n 32 " echo Running yosys clk2fflogic sim -../../yosys -q -p " +$YOSYS -q -p " read_verilog -formal clk2fflogic_effects.sv hierarchy -top top; proc;; clk2fflogic;; diff --git a/tests/various/hierarchy.sh b/tests/various/hierarchy.sh index 9dbd1c89f..73c066975 100644 --- a/tests/various/hierarchy.sh +++ b/tests/various/hierarchy.sh @@ -4,7 +4,7 @@ set -e echo -n " TOP first - " -../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module" +$YOSYS -s - <<- EOY | grep "Automatically selected TOP as design top module" read_verilog << EOV module TOP(a, y); input a; @@ -23,7 +23,7 @@ echo -n " TOP first - " EOY echo -n " TOP last - " -../../yosys -s - <<- EOY | grep "Automatically selected TOP as design top module" +$YOSYS -s - <<- EOY | grep "Automatically selected TOP as design top module" read_verilog << EOV module aoi12(a, y); input a; @@ -42,7 +42,7 @@ echo -n " TOP last - " EOY echo -n " no explicit top - " -../../yosys -s - <<- EOY | grep "Automatically selected noTop as design top module." +$YOSYS -s - <<- EOY | grep "Automatically selected noTop as design top module." read_verilog << EOV module aoi12(a, y); input a; diff --git a/tests/various/logger_cmd_error.sh b/tests/various/logger_cmd_error.sh index dd0585965..5816e211e 100755 --- a/tests/various/logger_cmd_error.sh +++ b/tests/various/logger_cmd_error.sh @@ -2,7 +2,7 @@ trap 'echo "ERROR in logger_cmd_error.sh" >&2; exit 1' ERR -(../../yosys -v 3 -C <&1` + output=`$YOSYS -q "$@" 2>&1` if [ $? -ne 1 ]; then fail "exit code for '$desc' was not 1" fi diff --git a/tests/various/plugin.sh b/tests/various/plugin.sh index 75b4c9e56..f9055bf19 100644 --- a/tests/various/plugin.sh +++ b/tests/various/plugin.sh @@ -6,7 +6,7 @@ DATDIR=$(../../yosys-config --datdir) DATDIR=${DATDIR//\//\\\/} CXXFLAGS=${CXXFLAGS//$DATDIR/..\/..\/share} ../../yosys-config --exec --cxx ${CXXFLAGS} --ldflags -shared -o plugin.so plugin.cc -../../yosys -m ./plugin.so -p "test" | grep -q "Plugin test passed!" +$YOSYS -m ./plugin.so -p "test" | grep -q "Plugin test passed!" mkdir -p plugin_search mv plugin.so plugin_search/plugin.so -YOSYS_PLUGIN_PATH=$PWD/plugin_search ../../yosys -m plugin.so -p "test" | grep -q "Plugin test passed!" +YOSYS_PLUGIN_PATH=$PWD/plugin_search $YOSYS -m plugin.so -p "test" | grep -q "Plugin test passed!" diff --git a/tests/various/sv_implicit_ports.sh b/tests/various/sv_implicit_ports.sh index 5266fffe5..24a5fe527 100755 --- a/tests/various/sv_implicit_ports.sh +++ b/tests/various/sv_implicit_ports.sh @@ -3,7 +3,7 @@ trap 'echo "ERROR in sv_implicit_ports.sh" >&2; exit 1' ERR # Simple case -../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <&1 | grep -F "ERROR: No matching wire for implicit port connection \`b' of cell top.add_i (add)." > /dev/null # Incorrectly sized wire -((../../yosys -f "verilog -sv" -qp "hierarchy -top top" - || true) <&1 | grep -F "ERROR: Width mismatch between wire (7 bits) and port (8 bits) for implicit port connection \`b' of cell top.add_i (add)." > /dev/null # Defaults -../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <&1 | grep -F "ERROR: Width mismatch between wire (8 bits) and port (6 bits) for implicit port connection \`q' of cell top.add_i (add)." > /dev/null # Mixed implicit and explicit 1 -../../yosys -f "verilog -sv" -qp "prep -flatten -top top; select -assert-count 1 t:\$add" - <&2; exit 1' ERR # Good case -../../yosys -f "verilog -sv" -qp proc - <&1 | grep -F ":3: ERROR: syntax error, unexpected '@'" > /dev/null # Incorrect use of always_comb -((../../yosys -f "verilog -sv" -qp proc -|| true) <&1 | grep -F "ERROR: Latch inferred for signal \`\\top.\\q' from always_comb process" > /dev/null # Incorrect use of always_latch -((../../yosys -f "verilog -sv" -qp proc -|| true) <&1 | grep -F "ERROR: No latch inferred for signal \`\\top.\\q' from always_latch process" > /dev/null # Incorrect use of always_ff -((../../yosys -f "verilog -sv" -qp proc -|| true) <