From 5ac6858f26cef9bf49c8434e7fc8208530e33dba Mon Sep 17 00:00:00 2001 From: Robert O'Callahan Date: Tue, 16 Sep 2025 22:59:08 +0000 Subject: [PATCH] Remove .c_str() from log_cmd_error() and log_file_error() parameters --- backends/aiger2/aiger.cc | 2 +- backends/cxxrtl/cxxrtl_backend.cc | 4 +-- frontends/ast/ast.cc | 2 +- frontends/ast/genrtlil.cc | 4 +-- frontends/ast/simplify.cc | 2 +- frontends/rpc/rpc_frontend.cc | 14 ++++---- frontends/verific/verific.cc | 16 ++++----- frontends/verilog/const2ast.cc | 2 +- frontends/verilog/preproc.cc | 2 +- kernel/fmt.cc | 14 ++++---- kernel/gzip.cc | 6 ++-- kernel/register.cc | 10 +++--- passes/cmds/abstract.cc | 4 +-- passes/cmds/add.cc | 2 +- passes/cmds/connect.cc | 10 +++--- passes/cmds/connwrappers.cc | 4 +-- passes/cmds/copy.cc | 4 +-- passes/cmds/cover.cc | 2 +- passes/cmds/design.cc | 8 ++--- passes/cmds/exec.cc | 8 ++--- passes/cmds/glift.cc | 2 +- passes/cmds/logger.cc | 8 ++--- passes/cmds/plugin.cc | 4 +-- passes/cmds/rename.cc | 6 ++-- passes/cmds/select.cc | 14 ++++---- passes/cmds/setattr.cc | 2 +- passes/cmds/setenv.cc | 2 +- passes/cmds/show.cc | 2 +- passes/cmds/stat.cc | 4 +-- passes/cmds/tee.cc | 2 +- passes/cmds/viz.cc | 2 +- passes/equiv/equiv_add.cc | 8 ++--- passes/equiv/equiv_make.cc | 14 ++++---- passes/hierarchy/hierarchy.cc | 6 ++-- passes/hierarchy/submod.cc | 2 +- passes/opt/opt_lut.cc | 2 +- passes/opt/opt_lut_ins.cc | 2 +- passes/pmgen/test_pmgen.cc | 2 +- passes/sat/eval.cc | 16 ++++----- passes/sat/miter.cc | 14 ++++---- passes/sat/mutate.cc | 2 +- passes/sat/qbfsat.cc | 8 ++--- passes/sat/sat.cc | 44 ++++++++++++------------- passes/sat/sim.cc | 2 +- passes/techmap/abc.cc | 4 +-- passes/techmap/cellmatch.cc | 2 +- passes/techmap/constmap.cc | 4 +-- passes/techmap/extract.cc | 2 +- passes/tests/test_cell.cc | 4 +-- techlibs/fabulous/synth_fabulous.cc | 2 +- techlibs/greenpak4/synth_greenpak4.cc | 2 +- techlibs/ice40/synth_ice40.cc | 2 +- techlibs/intel/synth_intel.cc | 2 +- techlibs/lattice/synth_lattice.cc | 2 +- techlibs/microchip/synth_microchip.cc | 2 +- techlibs/nanoxplore/synth_nanoxplore.cc | 2 +- techlibs/nexus/synth_nexus.cc | 2 +- techlibs/quicklogic/synth_quicklogic.cc | 2 +- techlibs/xilinx/synth_xilinx.cc | 2 +- 59 files changed, 163 insertions(+), 163 deletions(-) diff --git a/backends/aiger2/aiger.cc b/backends/aiger2/aiger.cc index c7ed3b81f..bf7497bb5 100644 --- a/backends/aiger2/aiger.cc +++ b/backends/aiger2/aiger.cc @@ -1446,7 +1446,7 @@ struct XAiger2Backend : Backend { if (!map_filename.empty()) { writer.map_file.open(map_filename); if (!writer.map_file) - log_cmd_error("Failed to open '%s' for writing\n", map_filename.c_str()); + log_cmd_error("Failed to open '%s' for writing\n", map_filename); } design->bufNormalize(true); diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc index 9a7e1383a..48710aff8 100644 --- a/backends/cxxrtl/cxxrtl_backend.cc +++ b/backends/cxxrtl/cxxrtl_backend.cc @@ -1533,7 +1533,7 @@ struct CxxrtlWorker { } // Internal cells } else if (is_internal_cell(cell->type)) { - log_cmd_error("Unsupported internal cell `%s'.\n", cell->type.c_str()); + log_cmd_error("Unsupported internal cell `%s'.\n", cell->type); // User cells } else if (for_debug) { // Outlines are called on demand when computing the value of a debug item. Nothing to do here. @@ -3803,7 +3803,7 @@ struct CxxrtlBackend : public Backend { if (args[argidx] == "-print-output" && argidx+1 < args.size()) { worker.print_output = args[++argidx]; if (!(worker.print_output == "std::cout" || worker.print_output == "std::cerr")) { - log_cmd_error("Invalid output stream \"%s\".\n", worker.print_output.c_str()); + log_cmd_error("Invalid output stream \"%s\".\n", worker.print_output); worker.print_output = "std::cout"; } continue; diff --git a/frontends/ast/ast.cc b/frontends/ast/ast.cc index 459b50683..488775d2c 100644 --- a/frontends/ast/ast.cc +++ b/frontends/ast/ast.cc @@ -1446,7 +1446,7 @@ void AST::process(RTLIL::Design *design, AstNode *ast, bool nodisplay, bool dump if (design->has(child->str)) { RTLIL::Module *existing_mod = design->module(child->str); if (!nooverwrite && !overwrite && !existing_mod->get_blackbox_attribute()) { - log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str.c_str()); + log_file_error(*child->location.begin.filename, child->location.begin.line, "Re-definition of module `%s'!\n", child->str); } else if (nooverwrite) { log("Ignoring re-definition of module `%s' at %s.\n", child->str.c_str(), child->loc_string().c_str()); diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc index 262dda43b..5fd478ff3 100644 --- a/frontends/ast/genrtlil.cc +++ b/frontends/ast/genrtlil.cc @@ -795,7 +795,7 @@ struct AST_INTERNAL::ProcessGenerator fmt.append_literal("\n"); fmt.emit_rtlil(cell); } else if (!ast->str.empty()) { - log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str.c_str()); + log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Found unsupported invocation of system task `%s'!\n", ast->str); } break; @@ -846,7 +846,7 @@ struct AST_INTERNAL::ProcessGenerator set_src_attr(cell, ast); for (auto &attr : ast->attributes) { if (attr.second->type != AST_CONSTANT) - log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first.c_str()); + log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first); cell->attributes[attr.first] = attr.second->asAttrConst(); } cell->setParam(ID::FLAVOR, flavor); diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc index 2669f83e2..0df09030c 100644 --- a/frontends/ast/simplify.cc +++ b/frontends/ast/simplify.cc @@ -164,7 +164,7 @@ Fmt AstNode::processFormat(int stage, bool sformat_like, int default_base, size_ log_file_info(*location.begin.filename, location.begin.line, "Skipping system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); return Fmt(); } else { - log_file_error(*location.begin.filename, location.begin.line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str.c_str(), index + 1); + log_file_error(*location.begin.filename, location.begin.line, "Failed to evaluate system task `%s' with non-constant argument at position %zu.\n", str, index + 1); } args.push_back(arg); } diff --git a/frontends/rpc/rpc_frontend.cc b/frontends/rpc/rpc_frontend.cc index df64ecd2f..80a6aae6d 100644 --- a/frontends/rpc/rpc_frontend.cc +++ b/frontends/rpc/rpc_frontend.cc @@ -91,9 +91,9 @@ struct RpcServer { std::string error; Json json_response = Json::parse(response, error); if (json_response.is_null()) - log_cmd_error("parsing JSON failed: %s\n", error.c_str()); + log_cmd_error("parsing JSON failed: %s\n", error); if (json_response["error"].is_string()) - log_cmd_error("RPC frontend returned an error: %s\n", json_response["error"].string_value().c_str()); + log_cmd_error("RPC frontend returned an error: %s\n", json_response["error"].string_value()); return json_response; } @@ -111,7 +111,7 @@ struct RpcServer { } } else is_valid = false; if (!is_valid) - log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump().c_str()); + log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump()); return modules; } @@ -149,7 +149,7 @@ struct RpcServer { source = response["source"].string_value(); else is_valid = false; if (!is_valid) - log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump().c_str()); + log_cmd_error("RPC frontend returned malformed response: %s\n", response.dump()); return std::make_pair(frontend, source); } }; @@ -202,7 +202,7 @@ struct RpcModule : RTLIL::Module { } } if (!found_derived_top) - log_cmd_error("RPC frontend did not return requested module `%s`!\n", stripped_name.c_str()); + log_cmd_error("RPC frontend did not return requested module `%s`!\n", stripped_name); for (auto module : derived_design->modules()) for (auto cell : module->cells()) @@ -256,7 +256,7 @@ struct HandleRpcServer : RpcServer { do { DWORD data_written; if (!WriteFile(hsend, &data[offset], data.length() - offset, &data_written, /*lpOverlapped=*/NULL)) - log_cmd_error("WriteFile failed: %s\n", get_last_error_str().c_str()); + log_cmd_error("WriteFile failed: %s\n", get_last_error_str()); offset += data_written; } while(offset < (ssize_t)data.length()); } @@ -268,7 +268,7 @@ struct HandleRpcServer : RpcServer { data.resize(data.length() + 1024); DWORD data_read; if (!ReadFile(hrecv, &data[offset], data.length() - offset, &data_read, /*lpOverlapped=*/NULL)) - log_cmd_error("ReadFile failed: %s\n", get_last_error_str().c_str()); + log_cmd_error("ReadFile failed: %s\n", get_last_error_str()); offset += data_read; data.resize(offset); size_t term_pos = data.find('\n', offset); diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 8bb34582e..91af38ccd 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -1469,7 +1469,7 @@ void VerificImporter::import_netlist(RTLIL::Design *design, Netlist *nl, std::ma if (design->has(module_name)) { if (!nl->IsOperator() && !is_blackbox(nl)) - log_cmd_error("Re-definition of module `%s'.\n", netlist_name.c_str()); + log_cmd_error("Re-definition of module `%s'.\n", netlist_name); return; } @@ -3824,7 +3824,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_87)) - log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_87 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3849,7 +3849,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_93)) - log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_93 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3874,7 +3874,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2K)) - log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_2K mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3899,7 +3899,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2019)) - log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_2019 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3924,7 +3924,7 @@ struct VerificPass : public Pass { add_units_to_map(map, work, flag_lib); std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!vhdl_file::Analyze(filename.c_str(), work.c_str(), vhdl_file::VHDL_2008)) - log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in VHDL_2008 mode failed.\n", filename); set_units_to_blackbox(map, work, flag_lib); } verific_import_pending = true; @@ -3938,7 +3938,7 @@ struct VerificPass : public Pass { while (argidx < GetSize(args)) { std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!edif.Read(filename.c_str())) - log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in EDIF mode failed.\n", filename); } goto check_error; } @@ -3961,7 +3961,7 @@ struct VerificPass : public Pass { while (argidx < GetSize(args)) { std::string filename = frontent_rewrite(args, argidx, tmp_files); if (!synlib_file::Read(filename.c_str(), is_work_set ? work.c_str() : nullptr)) - log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename.c_str()); + log_cmd_error("Reading `%s' in LIBERTY mode failed.\n", filename); SynlibLibrary *lib = synlib_file::GetLastLibraryAnalyzed(); if (lib && flag_lib) { MapIter mi ; diff --git a/frontends/verilog/const2ast.cc b/frontends/verilog/const2ast.cc index 9b197b356..661b4ef96 100644 --- a/frontends/verilog/const2ast.cc +++ b/frontends/verilog/const2ast.cc @@ -45,7 +45,7 @@ using namespace AST; using namespace VERILOG_FRONTEND; void ConstParser::log_maybe_loc_error(std::string msg) { - log_file_error(*loc.begin.filename, loc.begin.line, "%s", msg.c_str()); + log_file_error(*loc.begin.filename, loc.begin.line, "%s", msg); } void ConstParser::log_maybe_loc_warn(std::string msg) { diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc index 8674758ab..1858edc97 100644 --- a/frontends/verilog/preproc.cc +++ b/frontends/verilog/preproc.cc @@ -741,7 +741,7 @@ read_define(const std::string &filename, defines_map.add(name, value, (state == 2) ? &args : nullptr); global_defines_cache.add(name, value, (state == 2) ? &args : nullptr); } else { - log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name.c_str()); + log_file_error(filename, 0, "Invalid name for macro definition: >>%s<<.\n", name); } } diff --git a/kernel/fmt.cc b/kernel/fmt.cc index 6e9f2924a..200e7e5ce 100644 --- a/kernel/fmt.cc +++ b/kernel/fmt.cc @@ -401,11 +401,11 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik part = {}; } if (++i == fmt.size()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); } if (++arg == args.end()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with fewer arguments than the format specifiers in argument %zu require.\n", task_name, fmtarg - args.begin() + 1); } part.sig = arg->sig; part.signed_ = arg->signed_; @@ -420,7 +420,7 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik } else break; } if (i == fmt.size()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); } bool has_leading_zero = false, has_width = false; @@ -465,15 +465,15 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik if (!has_width && !has_leading_zero) part.width = 20; } else { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is not $time or $realtime.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with format character `%c' in argument %zu, but the argument is not $time or $realtime.\n", task_name, fmt[i], fmtarg - args.begin() + 1); } } else { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name.c_str(), fmt[i], fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with unrecognized format character `%c' in argument %zu.\n", task_name, fmt[i], fmtarg - args.begin() + 1); } break; } if (i == fmt.size()) { - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with incomplete format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); } if (part.padding == '\0') { @@ -486,7 +486,7 @@ void Fmt::parse_verilog(const std::vector &args, bool sformat_lik } if (part.type == FmtPart::INTEGER && part.base != 10 && part.sign != FmtPart::MINUS) - log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name.c_str(), fmtarg - args.begin() + 1); + log_file_error(fmtarg->filename, fmtarg->first_line, "System task `%s' called with invalid format specifier in argument %zu.\n", task_name, fmtarg - args.begin() + 1); if (part.base != 10) part.signed_ = false; diff --git a/kernel/gzip.cc b/kernel/gzip.cc index d19c06579..433c35902 100644 --- a/kernel/gzip.cc +++ b/kernel/gzip.cc @@ -103,11 +103,11 @@ gzip_istream::ibuf::~ibuf() { // Never returns nullptr or failed state istream* std::istream* uncompressed(const std::string filename, std::ios_base::openmode mode) { if (!check_file_exists(filename)) - log_cmd_error("File `%s' not found or is a directory\n", filename.c_str()); + log_cmd_error("File `%s' not found or is a directory\n", filename); std::ifstream* f = new std::ifstream(); f->open(filename, mode); if (f->fail()) - log_cmd_error("Can't open input file `%s' for reading: %s\n", filename.c_str(), strerror(errno)); + log_cmd_error("Can't open input file `%s' for reading: %s\n", filename, strerror(errno)); // Check for gzip magic unsigned char magic[3]; int n = 0; @@ -131,7 +131,7 @@ std::istream* uncompressed(const std::string filename, std::ios_base::openmode m log_assert(ok && "Failed to open gzipped file.\n"); return s; #else - log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename.c_str()); + log_cmd_error("File `%s' is a gzip file, but Yosys is compiled without zlib.\n", filename); #endif // YOSYS_ENABLE_ZLIB } else { f->clear(); diff --git a/kernel/register.cc b/kernel/register.cc index 4afd7ada3..36e312968 100644 --- a/kernel/register.cc +++ b/kernel/register.cc @@ -262,7 +262,7 @@ void Pass::call(RTLIL::Design *design, std::vector args) } if (pass_register.count(args[0]) == 0) - log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0].c_str()); + log_cmd_error("No such command: %s (type 'help' for a command overview)\n", args[0]); if (pass_register[args[0]]->experimental_flag) log_experimental(args[0]); @@ -521,7 +521,7 @@ void Frontend::frontend_call(RTLIL::Design *design, std::istream *f, std::string if (args.size() == 0) return; if (frontend_register.count(args[0]) == 0) - log_cmd_error("No such frontend: %s\n", args[0].c_str()); + log_cmd_error("No such frontend: %s\n", args[0]); if (f != NULL) { auto state = frontend_register[args[0]]->pre_execute(); @@ -596,7 +596,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectoropen(filename)) { delete gf; - log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", filename, strerror(errno)); } yosys_output_files.insert(filename); f = gf; @@ -609,7 +609,7 @@ void Backend::extra_args(std::ostream *&f, std::string &filename, std::vectorfail()) { delete ff; - log_cmd_error("Can't open output file `%s' for writing: %s\n", filename.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", filename, strerror(errno)); } f = ff; } @@ -641,7 +641,7 @@ void Backend::backend_call(RTLIL::Design *design, std::ostream *f, std::string f if (args.size() == 0) return; if (backend_register.count(args[0]) == 0) - log_cmd_error("No such backend: %s\n", args[0].c_str()); + log_cmd_error("No such backend: %s\n", args[0]); size_t orig_sel_stack_pos = design->selection_stack.size(); diff --git a/passes/cmds/abstract.cc b/passes/cmds/abstract.cc index e475ba71c..88f07a5aa 100644 --- a/passes/cmds/abstract.cc +++ b/passes/cmds/abstract.cc @@ -53,7 +53,7 @@ struct Slice { } static void syntax_error(const std::string &slice) { - log_cmd_error("Invalid slice '%s', expected ':' or ''", slice.c_str()); + log_cmd_error("Invalid slice '%s', expected ':' or ''", slice); } std::string to_string() const { @@ -494,7 +494,7 @@ struct AbstractPass : public Pass { case Enable::ActiveHigh: { Wire *enable_wire = mod->wire("\\" + enable_name); if (!enable_wire) - log_cmd_error("Enable wire %s not found in module %s\n", enable_name.c_str(), mod->name.c_str()); + log_cmd_error("Enable wire %s not found in module %s\n", enable_name, mod->name); if (GetSize(enable_wire) != 1) log_cmd_error("Enable wire %s must have width 1 but has width %d in module %s\n", enable_name.c_str(), GetSize(enable_wire), mod->name.c_str()); diff --git a/passes/cmds/add.cc b/passes/cmds/add.cc index 0d395f043..1011a093c 100644 --- a/passes/cmds/add.cc +++ b/passes/cmds/add.cc @@ -77,7 +77,7 @@ static void add_wire(RTLIL::Design *design, RTLIL::Module *module, std::string n wire = nullptr; if (wire == nullptr) - log_cmd_error("Found incompatible object with same name in module %s!\n", module->name.c_str()); + log_cmd_error("Found incompatible object with same name in module %s!\n", module->name); log("Module %s already has such an object.\n", module->name); } diff --git a/passes/cmds/connect.cc b/passes/cmds/connect.cc index 65292ef92..c6d3320ea 100644 --- a/passes/cmds/connect.cc +++ b/passes/cmds/connect.cc @@ -150,9 +150,9 @@ struct ConnectPass : public Pass { RTLIL::SigSpec sig_lhs, sig_rhs; if (!RTLIL::SigSpec::parse_sel(sig_lhs, design, module, set_lhs)) - log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs.c_str()); + log_cmd_error("Failed to parse set lhs expression `%s'.\n", set_lhs); if (!RTLIL::SigSpec::parse_rhs(sig_lhs, sig_rhs, module, set_rhs)) - log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs.c_str()); + log_cmd_error("Failed to parse set rhs expression `%s'.\n", set_rhs); sigmap.apply(sig_lhs); sigmap.apply(sig_rhs); @@ -173,7 +173,7 @@ struct ConnectPass : public Pass { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, unset_expr)) - log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr.c_str()); + log_cmd_error("Failed to parse unset expression `%s'.\n", unset_expr); sigmap.apply(sig); unset_drivers(design, module, sigmap, sig); @@ -185,11 +185,11 @@ struct ConnectPass : public Pass { log_cmd_error("Can't use -port together with -nounset.\n"); if (module->cell(RTLIL::escape_id(port_cell)) == nullptr) - log_cmd_error("Can't find cell %s.\n", port_cell.c_str()); + log_cmd_error("Can't find cell %s.\n", port_cell); RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, port_expr)) - log_cmd_error("Failed to parse port expression `%s'.\n", port_expr.c_str()); + log_cmd_error("Failed to parse port expression `%s'.\n", port_expr); if (!flag_assert) { module->cell(RTLIL::escape_id(port_cell))->setPort(RTLIL::escape_id(port_port), sigmap(sig)); diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc index dbe23ccf1..5677c666d 100644 --- a/passes/cmds/connwrappers.cc +++ b/passes/cmds/connwrappers.cc @@ -42,7 +42,7 @@ struct ConnwrappersWorker decl_celltypes.insert(key.first); if (decls.count(key)) - log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str()); + log_cmd_error("Duplicate port decl: %s %s\n", celltype, portname); portdecl_t decl; decl.widthparam = RTLIL::escape_id(widthparam); @@ -57,7 +57,7 @@ struct ConnwrappersWorker decl_celltypes.insert(key.first); if (decls.count(key)) - log_cmd_error("Duplicate port decl: %s %s\n", celltype.c_str(), portname.c_str()); + log_cmd_error("Duplicate port decl: %s %s\n", celltype, portname); portdecl_t decl; decl.widthparam = RTLIL::escape_id(widthparam); diff --git a/passes/cmds/copy.cc b/passes/cmds/copy.cc index e3fb3a0e6..5a5835a43 100644 --- a/passes/cmds/copy.cc +++ b/passes/cmds/copy.cc @@ -45,10 +45,10 @@ struct CopyPass : public Pass { std::string trg_name = RTLIL::escape_id(args[2]); if (design->module(src_name) == nullptr) - log_cmd_error("Can't find source module %s.\n", src_name.c_str()); + log_cmd_error("Can't find source module %s.\n", src_name); if (design->module(trg_name) != nullptr) - log_cmd_error("Target module name %s already exists.\n", trg_name.c_str()); + log_cmd_error("Target module name %s already exists.\n", trg_name); RTLIL::Module *new_mod = design->module(src_name)->clone(); new_mod->name = trg_name; diff --git a/passes/cmds/cover.cc b/passes/cmds/cover.cc index bab00c287..7f217329c 100644 --- a/passes/cmds/cover.cc +++ b/passes/cmds/cover.cc @@ -118,7 +118,7 @@ struct CoverPass : public Pass { if (f == NULL) { for (auto f : out_files) fclose(f); - log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx].c_str()); + log_cmd_error("Can't create file %s%s.\n", args[argidx-1] == "-d" ? "in directory " : "", args[argidx]); } out_files.push_back(f); continue; diff --git a/passes/cmds/design.cc b/passes/cmds/design.cc index 59cd39c98..ddbd98bfd 100644 --- a/passes/cmds/design.cc +++ b/passes/cmds/design.cc @@ -165,13 +165,13 @@ struct DesignPass : public Pass { got_mode = true; load_name = args[++argidx]; if (saved_designs.count(load_name) == 0) - log_cmd_error("No saved design '%s' found!\n", load_name.c_str()); + log_cmd_error("No saved design '%s' found!\n", load_name); continue; } if (!got_mode && args[argidx] == "-copy-from" && argidx+1 < args.size()) { got_mode = true; if (saved_designs.count(args[++argidx]) == 0) - log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str()); + log_cmd_error("No saved design '%s' found!\n", args[argidx]); copy_from_design = saved_designs.at(args[argidx]); copy_to_design = design; continue; @@ -188,7 +188,7 @@ struct DesignPass : public Pass { got_mode = true; import_mode = true; if (saved_designs.count(args[++argidx]) == 0) - log_cmd_error("No saved design '%s' found!\n", args[argidx].c_str()); + log_cmd_error("No saved design '%s' found!\n", args[argidx]); copy_from_design = saved_designs.at(args[argidx]); copy_to_design = design; as_name = args[argidx]; @@ -202,7 +202,7 @@ struct DesignPass : public Pass { got_mode = true; delete_name = args[++argidx]; if (saved_designs.count(delete_name) == 0) - log_cmd_error("No saved design '%s' found!\n", delete_name.c_str()); + log_cmd_error("No saved design '%s' found!\n", delete_name); continue; } break; diff --git a/passes/cmds/exec.cc b/passes/cmds/exec.cc index b346fc95d..ff1ef11ff 100644 --- a/passes/cmds/exec.cc +++ b/passes/cmds/exec.cc @@ -127,7 +127,7 @@ struct ExecPass : public Pass { x.re = YS_REGEX_COMPILE(args[argidx]); expect_stdout.push_back(x); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + log_cmd_error("Error in regex expression '%s' !\n", args[argidx]); } } else if (args[argidx] == "-not-expect-stdout") { flag_expect_stdout = true; @@ -142,11 +142,11 @@ struct ExecPass : public Pass { x.polarity = false; expect_stdout.push_back(x); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", args[argidx].c_str()); + log_cmd_error("Error in regex expression '%s' !\n", args[argidx]); } } else - log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx].c_str()); + log_cmd_error("Unknown option \"%s\" or \"--\" doesn\'t precede command.\n", args[argidx]); } } @@ -201,7 +201,7 @@ struct ExecPass : public Pass { if (flag_expect_stdout) for (auto &x : expect_stdout) if (x.polarity ^ x.matched) - log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str.c_str()); + log_cmd_error("Command stdout did%s have a line matching given regex \"%s\".\n", (x.polarity? " not" : ""), x.str); log_pop(); } diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc index d7264d392..d906c241d 100644 --- a/passes/cmds/glift.cc +++ b/passes/cmds/glift.cc @@ -184,7 +184,7 @@ private: for(auto &cell : module->cells().to_vector()) { if (!cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_), ID($_XOR_), ID($_XNOR_), ID($_MUX_), ID($_NMUX_), ID($_NOT_), ID($anyconst), ID($allconst), ID($assume), ID($assert)) && module->design->module(cell->type) == nullptr) { - log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type.c_str()); + log_cmd_error("Unsupported cell type \"%s\" found. Run `techmap` first.\n", cell->type); } if (cell->type.in(ID($_AND_), ID($_NAND_), ID($_OR_), ID($_NOR_))) { const unsigned int A = 0, B = 1, Y = 2; diff --git a/passes/cmds/logger.cc b/passes/cmds/logger.cc index 37240bb7e..cab4ab81c 100644 --- a/passes/cmds/logger.cc +++ b/passes/cmds/logger.cc @@ -112,7 +112,7 @@ struct LoggerPass : public Pass { log_warn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } @@ -124,7 +124,7 @@ struct LoggerPass : public Pass { log_nowarn_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } @@ -136,7 +136,7 @@ struct LoggerPass : public Pass { log_werror_regexes.push_back(YS_REGEX_COMPILE(pattern)); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } @@ -188,7 +188,7 @@ struct LoggerPass : public Pass { else log_abort(); } catch (const std::regex_error& e) { - log_cmd_error("Error in regex expression '%s' !\n", pattern.c_str()); + log_cmd_error("Error in regex expression '%s' !\n", pattern); } continue; } diff --git a/passes/cmds/plugin.cc b/passes/cmds/plugin.cc index 6c7921d53..afa830552 100644 --- a/passes/cmds/plugin.cc +++ b/passes/cmds/plugin.cc @@ -70,7 +70,7 @@ void load_plugin(std::string filename, std::vector aliases) if(module_p == NULL) { PyErr_Print(); - log_cmd_error("Can't load python module `%s'\n", full_path.filename().c_str()); + log_cmd_error("Can't load python module `%s'\n", full_path.filename()); return; } loaded_python_plugins[orig_filename] = module_p; @@ -100,7 +100,7 @@ void load_plugin(std::string filename, std::vector aliases) } if (hdl == NULL) - log_cmd_error("Can't load module `%s': %s\n", filename.c_str(), dlerror()); + log_cmd_error("Can't load module `%s': %s\n", filename, dlerror()); loaded_plugins[orig_filename] = hdl; Pass::init_register(); diff --git a/passes/cmds/rename.cc b/passes/cmds/rename.cc index c4bb7135e..078ffb769 100644 --- a/passes/cmds/rename.cc +++ b/passes/cmds/rename.cc @@ -31,7 +31,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: to_name = RTLIL::escape_id(to_name); if (module->count_id(to_name)) - log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name.c_str(), module->name.c_str()); + log_cmd_error("There is already an object `%s' in module `%s'.\n", to_name, module->name); RTLIL::Wire *wire_to_rename = module->wire(from_name); RTLIL::Cell *cell_to_rename = module->cell(from_name); @@ -55,7 +55,7 @@ static void rename_in_module(RTLIL::Module *module, std::string from_name, std:: return; } - log_cmd_error("Object `%s' not found!\n", from_name.c_str()); + log_cmd_error("Object `%s' not found!\n", from_name); } static std::string derive_name_from_src(const std::string &src, int counter) @@ -632,7 +632,7 @@ struct RenamePass : public Pass { log("Renaming module %s to %s.\n", module_to_rename->name, to_name); design->rename(module_to_rename, to_name); } else - log_cmd_error("Object `%s' not found!\n", from_name.c_str()); + log_cmd_error("Object `%s' not found!\n", from_name); } } } diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 7fcf5cfcd..469e36ef1 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -592,7 +592,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char while (pos < int(arg.size())) { if (arg[pos] != ':' || pos+1 == int(arg.size())) - log_cmd_error("Syntax error in expand operator '%s'.\n", arg.c_str()); + log_cmd_error("Syntax error in expand operator '%s'.\n", arg); pos++; if (arg[pos] == '+' || arg[pos] == '-') { expand_rule_t rule; @@ -617,7 +617,7 @@ static void select_op_expand(RTLIL::Design *design, const std::string &arg, char for (auto i2 : i1.second) limits.insert(i2); } else - log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str).c_str()); + log_cmd_error("Selection %s is not defined!\n", RTLIL::unescape_id(str)); } else limits.insert(RTLIL::escape_id(str)); } @@ -804,7 +804,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp log_cmd_error("Must have at least one element on the stack for operator %%coe.\n"); select_op_expand(design, arg, 'o', true); } else - log_cmd_error("Unknown selection operator '%s'.\n", arg.c_str()); + log_cmd_error("Unknown selection operator '%s'.\n", arg); if (work_stack.size() >= 1) select_filter_active_mod(design, work_stack.back()); return; @@ -815,7 +815,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp if (design->selection_vars.count(set_name) > 0) work_stack.push_back(design->selection_vars[set_name]); else - log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str()); + log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name)); select_filter_active_mod(design, work_stack.back()); return; } @@ -934,7 +934,7 @@ static void select_stmt(RTLIL::Design *design, std::string arg, bool disable_emp if (arg_memb.compare(2, 1, "@") == 0) { std::string set_name = RTLIL::escape_id(arg_memb.substr(3)); if (!design->selection_vars.count(set_name)) - log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name).c_str()); + log_cmd_error("Selection @%s is not defined!\n", RTLIL::unescape_id(set_name)); auto &muster = design->selection_vars[set_name]; for (auto cell : mod->cells()) @@ -1428,7 +1428,7 @@ struct SelectPass : public Pass { continue; } if (arg.size() > 0 && arg[0] == '-') - log_cmd_error("Unknown option %s.\n", arg.c_str()); + log_cmd_error("Unknown option %s.\n", arg); bool disable_empty_warning = count_mode || assert_none || assert_any || (assert_modcount != -1) || (assert_count != -1) || (assert_max != -1) || (assert_min != -1); select_stmt(design, arg, disable_empty_warning); @@ -1762,7 +1762,7 @@ struct CdPass : public Pass { return; } - log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname).c_str()); + log_cmd_error("No such module `%s' found!\n", RTLIL::unescape_id(modname)); } } CdPass; diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc index f590c2fa9..25d8fd34c 100644 --- a/passes/cmds/setattr.cc +++ b/passes/cmds/setattr.cc @@ -39,7 +39,7 @@ struct setunset_t } else { RTLIL::SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, nullptr, set_value)) - log_cmd_error("Can't decode value '%s'!\n", set_value.c_str()); + log_cmd_error("Can't decode value '%s'!\n", set_value); value = sig_value.as_const(); } } diff --git a/passes/cmds/setenv.cc b/passes/cmds/setenv.cc index 850d7c961..90eeab702 100644 --- a/passes/cmds/setenv.cc +++ b/passes/cmds/setenv.cc @@ -52,7 +52,7 @@ struct SetenvPass : public Pass { _putenv_s(name.c_str(), value.c_str()); #else if (setenv(name.c_str(), value.c_str(), 1)) - log_cmd_error("Invalid name \"%s\".\n", name.c_str()); + log_cmd_error("Invalid name \"%s\".\n", name); #endif } diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc index c2d446162..d0d9c0f85 100644 --- a/passes/cmds/show.cc +++ b/passes/cmds/show.cc @@ -926,7 +926,7 @@ struct ShowPass : public Pass { if (f == nullptr) { for (auto lib : libs) delete lib; - log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); + log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file); } ShowWorker worker(f, design, libs, colorSeed, flag_width, flag_wireshape, flag_signed, flag_stretch, flag_enum, flag_abbreviate, flag_notitle, flag_href, color_selections, label_selections, colorattr); fclose(f); diff --git a/passes/cmds/stat.cc b/passes/cmds/stat.cc index 1b9e6106c..6e46ab5e2 100644 --- a/passes/cmds/stat.cc +++ b/passes/cmds/stat.cc @@ -949,7 +949,7 @@ struct StatPass : public Pass { } if (args[argidx] == "-top" && argidx + 1 < args.size()) { if (design->module(RTLIL::escape_id(args[argidx + 1])) == nullptr) - log_cmd_error("Can't find module %s.\n", args[argidx + 1].c_str()); + log_cmd_error("Can't find module %s.\n", args[argidx + 1]); top_mod = design->module(RTLIL::escape_id(args[++argidx])); continue; } @@ -969,7 +969,7 @@ struct StatPass : public Pass { log_header(design, "Printing statistics.\n"); if (techname != "" && techname != "xilinx" && techname != "cmos" && !json_mode) - log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); + log_cmd_error("Unsupported technology: '%s'\n", techname); if (json_mode) { log("{\n"); diff --git a/passes/cmds/tee.cc b/passes/cmds/tee.cc index fbd42e311..cef94b9ce 100644 --- a/passes/cmds/tee.cc +++ b/passes/cmds/tee.cc @@ -83,7 +83,7 @@ struct TeePass : public Pass { if (f == NULL) { for (auto cf : files_to_close) fclose(cf); - log_cmd_error("Can't create file %s.\n", args[argidx].c_str()); + log_cmd_error("Can't create file %s.\n", args[argidx]); } log_files.push_back(f); files_to_close.push_back(f); diff --git a/passes/cmds/viz.cc b/passes/cmds/viz.cc index fd45d6ba0..e3b09d029 100644 --- a/passes/cmds/viz.cc +++ b/passes/cmds/viz.cc @@ -994,7 +994,7 @@ struct VizPass : public Pass { if (f != nullptr) return; f = fopen(dot_file.c_str(), "w"); if (f == nullptr) - log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file.c_str()); + log_cmd_error("Can't open dot file `%s' for writing.\n", dot_file); }; for (auto module : modlist) { VizWorker worker(module, config); diff --git a/passes/equiv/equiv_add.cc b/passes/equiv/equiv_add.cc index 1bcd4a887..4deef6e32 100644 --- a/passes/equiv/equiv_add.cc +++ b/passes/equiv/equiv_add.cc @@ -64,7 +64,7 @@ struct EquivAddPass : public Pass { log_warning("Can't find gold cell '%s'.\n", args[2].c_str()); return; } - log_cmd_error("Can't find gold cell '%s'.\n", args[2].c_str()); + log_cmd_error("Can't find gold cell '%s'.\n", args[2]); } if (gate_cell == nullptr) { @@ -72,7 +72,7 @@ struct EquivAddPass : public Pass { log_warning("Can't find gate cell '%s'.\n", args[3].c_str()); return; } - log_cmd_error("Can't find gate cell '%s'.\n", args[3].c_str()); + log_cmd_error("Can't find gate cell '%s'.\n", args[3]); } for (auto conn : gold_cell->connections()) @@ -129,7 +129,7 @@ struct EquivAddPass : public Pass { log_warning("Error in gate signal: %s\n", args[2].c_str()); return; } - log_cmd_error("Error in gate signal: %s\n", args[2].c_str()); + log_cmd_error("Error in gate signal: %s\n", args[2]); } if (!SigSpec::parse_rhs(gate_signal, gold_signal, module, args[1])) { @@ -137,7 +137,7 @@ struct EquivAddPass : public Pass { log_warning("Error in gold signal: %s\n", args[1].c_str()); return; } - log_cmd_error("Error in gold signal: %s\n", args[1].c_str()); + log_cmd_error("Error in gold signal: %s\n", args[1]); } log_assert(GetSize(gold_signal) == GetSize(gate_signal)); diff --git a/passes/equiv/equiv_make.cc b/passes/equiv/equiv_make.cc index e15e510be..bae7452f7 100644 --- a/passes/equiv/equiv_make.cc +++ b/passes/equiv/equiv_make.cc @@ -47,7 +47,7 @@ struct EquivMakeWorker { std::ifstream f(fn); if (f.fail()) - log_cmd_error("Can't open blacklist file '%s'!\n", fn.c_str()); + log_cmd_error("Can't open blacklist file '%s'!\n", fn); string line, token; while (std::getline(f, line)) { @@ -67,7 +67,7 @@ struct EquivMakeWorker { std::ifstream f(fn); if (f.fail()) - log_cmd_error("Can't open encfile '%s'!\n", fn.c_str()); + log_cmd_error("Can't open encfile '%s'!\n", fn); dict *ed = nullptr; string line, token; @@ -81,7 +81,7 @@ struct EquivMakeWorker IdString modname = RTLIL::escape_id(next_token(line)); IdString signame = RTLIL::escape_id(next_token(line)); if (encdata.count(signame)) - log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame.c_str(), fn.c_str()); + log_cmd_error("Re-definition of signal '%s' in encfile '%s'!\n", signame, fn); encdata[signame] = dict(); ed = &encdata[signame]; continue; @@ -94,7 +94,7 @@ struct EquivMakeWorker continue; } - log_cmd_error("Syntax error in encfile '%s'!\n", fn.c_str()); + log_cmd_error("Syntax error in encfile '%s'!\n", fn); } } } @@ -492,13 +492,13 @@ struct EquivMakePass : public Pass { worker.equiv_mod = design->module(RTLIL::escape_id(args[argidx+2])); if (worker.gold_mod == nullptr) - log_cmd_error("Can't find gold module %s.\n", args[argidx].c_str()); + log_cmd_error("Can't find gold module %s.\n", args[argidx]); if (worker.gate_mod == nullptr) - log_cmd_error("Can't find gate module %s.\n", args[argidx+1].c_str()); + log_cmd_error("Can't find gate module %s.\n", args[argidx+1]); if (worker.equiv_mod != nullptr) - log_cmd_error("Equiv module %s already exists.\n", args[argidx+2].c_str()); + log_cmd_error("Equiv module %s already exists.\n", args[argidx+2]); if (worker.gold_mod->has_memories() || worker.gold_mod->has_processes()) log_cmd_error("Gold module contains memories or processes. Run 'memory' or 'proc' respectively.\n"); diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 6fec628c2..f670d1fd2 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -957,7 +957,7 @@ struct HierarchyPass : public Pass { for (auto ¶ : parameters) { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) - log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); + log_cmd_error("Can't decode value '%s'!\n", para.second); top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); } } @@ -991,7 +991,7 @@ struct HierarchyPass : public Pass { } #endif if (top_mod == NULL) - log_cmd_error("Module `%s' not found!\n", load_top_mod.c_str()); + log_cmd_error("Module `%s' not found!\n", load_top_mod); } else { #ifdef YOSYS_ENABLE_VERIFIC if (verific_import_pending) @@ -1045,7 +1045,7 @@ struct HierarchyPass : public Pass { for (auto ¶ : parameters) { SigSpec sig_value; if (!RTLIL::SigSpec::parse(sig_value, NULL, para.second)) - log_cmd_error("Can't decode value '%s'!\n", para.second.c_str()); + log_cmd_error("Can't decode value '%s'!\n", para.second); top_parameters[RTLIL::escape_id(para.first)] = sig_value.as_const(); } diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc index 486d21920..f979e7acc 100644 --- a/passes/hierarchy/submod.cc +++ b/passes/hierarchy/submod.cc @@ -408,7 +408,7 @@ struct SubmodPass : public Pass { RTLIL::Module *module = nullptr; for (auto mod : design->selected_modules()) { if (module != nullptr) - log_cmd_error("More than one module selected: %s %s\n", module->name.c_str(), mod->name.c_str()); + log_cmd_error("More than one module selected: %s %s\n", module->name, mod->name); module = mod; } if (module == nullptr) diff --git a/passes/opt/opt_lut.cc b/passes/opt/opt_lut.cc index 248c3dfe9..37ae38225 100644 --- a/passes/opt/opt_lut.cc +++ b/passes/opt/opt_lut.cc @@ -555,7 +555,7 @@ struct OptLutPass : public Pass { { std::string tech = args[++argidx]; if (tech != "ice40") - log_cmd_error("Unsupported -tech argument: %s\n", tech.c_str()); + log_cmd_error("Unsupported -tech argument: %s\n", tech); dlogic = {{ ID(SB_CARRY), diff --git a/passes/opt/opt_lut_ins.cc b/passes/opt/opt_lut_ins.cc index 9e471c3de..fa8eb563b 100644 --- a/passes/opt/opt_lut_ins.cc +++ b/passes/opt/opt_lut_ins.cc @@ -59,7 +59,7 @@ struct OptLutInsPass : public Pass { extra_args(args, argidx, design); if (techname != "" && techname != "xilinx" && techname != "lattice" && techname != "ecp5" && techname != "gowin") - log_cmd_error("Unsupported technology: '%s'\n", techname.c_str()); + log_cmd_error("Unsupported technology: '%s'\n", techname); for (auto module : design->selected_modules()) { diff --git a/passes/pmgen/test_pmgen.cc b/passes/pmgen/test_pmgen.cc index 892500850..f6d6a3f93 100644 --- a/passes/pmgen/test_pmgen.cc +++ b/passes/pmgen/test_pmgen.cc @@ -238,7 +238,7 @@ struct TestPmgenPass : public Pass { if (pattern == "xilinx_srl.variable") return GENERATE_PATTERN(xilinx_srl_pm, variable); - log_cmd_error("Unknown pattern: %s\n", pattern.c_str()); + log_cmd_error("Unknown pattern: %s\n", pattern); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc index f71e8124b..b0eaaca22 100644 --- a/passes/sat/eval.cc +++ b/passes/sat/eval.cc @@ -94,11 +94,11 @@ struct BruteForceEquivChecker continue; if (mod2->wire(w->name) == nullptr) - log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name.c_str()); + log_cmd_error("Port %s in module 1 has no counterpart in module 2!\n", w->name); RTLIL::Wire *w2 = mod2->wire(w->name); if (w->width != w2->width || w->port_input != w2->port_input || w->port_output != w2->port_output) - log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name.c_str()); + log_cmd_error("Port %s in module 1 does not match its counterpart in module 2!\n", w->name); if (w->port_input) { mod1_inputs.append(w); @@ -454,11 +454,11 @@ struct EvalPass : public Pass { for (auto &it : sets) { RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, it.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", it.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, it.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", it.second); if (!rhs.is_fully_const()) - log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second.c_str()); + log_cmd_error("Right-hand-side set expression `%s' is not constant.\n", it.second); if (lhs.size() != rhs.size()) log_cmd_error("Set expression with different lhs and rhs sizes: %s (%s, %d bits) vs. %s (%s, %d bits)\n", it.first.c_str(), log_signal(lhs), lhs.size(), it.second.c_str(), log_signal(rhs), rhs.size()); @@ -476,7 +476,7 @@ struct EvalPass : public Pass { for (auto &it : shows) { RTLIL::SigSpec signal, value, undef; if (!RTLIL::SigSpec::parse_sel(signal, design, module, it)) - log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); + log_cmd_error("Failed to parse show expression `%s'.\n", it); value = signal; if (set_undef) { while (!ce.eval(value, undef)) { @@ -502,14 +502,14 @@ struct EvalPass : public Pass { for (auto &it : shows) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, it)) - log_cmd_error("Failed to parse show expression `%s'.\n", it.c_str()); + log_cmd_error("Failed to parse show expression `%s'.\n", it); signal.append(sig); } for (auto &it : tables) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, it)) - log_cmd_error("Failed to parse table expression `%s'.\n", it.c_str()); + log_cmd_error("Failed to parse table expression `%s'.\n", it); tabsigs.append(sig); } diff --git a/passes/sat/miter.cc b/passes/sat/miter.cc index 9bcf25547..55a41909d 100644 --- a/passes/sat/miter.cc +++ b/passes/sat/miter.cc @@ -76,11 +76,11 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: RTLIL::IdString miter_name = RTLIL::escape_id(args[argidx++]); if (design->module(gold_name) == nullptr) - log_cmd_error("Can't find gold module %s!\n", gold_name.c_str()); + log_cmd_error("Can't find gold module %s!\n", gold_name); if (design->module(gate_name) == nullptr) - log_cmd_error("Can't find gate module %s!\n", gate_name.c_str()); + log_cmd_error("Can't find gate module %s!\n", gate_name); if (design->module(miter_name) != nullptr) - log_cmd_error("There is already a module %s!\n", miter_name.c_str()); + log_cmd_error("There is already a module %s!\n", miter_name); RTLIL::Module *gold_module = design->module(gold_name); RTLIL::Module *gate_module = design->module(gate_name); @@ -105,7 +105,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: goto match_gold_port_error; continue; match_gold_port_error: - log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name.c_str()); + log_cmd_error("No matching port in gate module was found for %s!\n", gold_wire->name); } for (auto gate_wire : gate_module->wires()) { @@ -125,7 +125,7 @@ void create_miter_equiv(struct Pass *that, std::vector args, RTLIL: goto match_gate_port_error; continue; match_gate_port_error: - log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name.c_str()); + log_cmd_error("No matching port in gold module was found for %s!\n", gate_wire->name); } log("Creating miter cell \"%s\" with gold cell \"%s\" and gate cell \"%s\".\n", RTLIL::id2cstr(miter_name), RTLIL::id2cstr(gold_name), RTLIL::id2cstr(gate_name)); @@ -322,9 +322,9 @@ void create_miter_assert(struct Pass *that, std::vector args, RTLIL IdString miter_name = argidx < args.size() ? RTLIL::escape_id(args[argidx++]) : ""; if (design->module(module_name) == nullptr) - log_cmd_error("Can't find module %s!\n", module_name.c_str()); + log_cmd_error("Can't find module %s!\n", module_name); if (!miter_name.empty() && design->module(miter_name) != nullptr) - log_cmd_error("There is already a module %s!\n", miter_name.c_str()); + log_cmd_error("There is already a module %s!\n", miter_name); Module *module = design->module(module_name); diff --git a/passes/sat/mutate.cc b/passes/sat/mutate.cc index 58d932f20..79ffcd88d 100644 --- a/passes/sat/mutate.cc +++ b/passes/sat/mutate.cc @@ -989,7 +989,7 @@ struct MutatePass : public Pass { return; } - log_cmd_error("Invalid mode: %s\n", opts.mode.c_str()); + log_cmd_error("Invalid mode: %s\n", opts.mode); } } MutatePass; diff --git a/passes/sat/qbfsat.cc b/passes/sat/qbfsat.cc index 20cee7956..ad28884f7 100644 --- a/passes/sat/qbfsat.cc +++ b/passes/sat/qbfsat.cc @@ -87,7 +87,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { if (!std::regex_search(buf, bit_m, hole_bit_assn_regex)) { bit_assn = false; if (!std::regex_search(buf, m, hole_assn_regex)) - log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf.c_str()); + log_cmd_error("solution file is not formatted correctly: \"%s\"\n", buf); } std::string hole_loc = bit_assn? bit_m[1].str() : m[1].str(); @@ -108,7 +108,7 @@ void specialize_from_file(RTLIL::Module *module, const std::string &file) { pool hole_loc_pool(locs.begin(), locs.end()); auto hole_cell_it = anyconst_loc_to_cell.find(hole_loc_pool); if (hole_cell_it == anyconst_loc_to_cell.end()) - log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf.c_str()); + log_cmd_error("cannot find matching wire name or $anyconst cell location for hole spec \"%s\"\n", buf); RTLIL::Cell *hole_cell = hole_cell_it->second; hole_sigbit = hole_cell->getPort(ID::Y)[hole_bit]; @@ -420,7 +420,7 @@ QbfSolveOptions parse_args(const std::vector &args) { else if (args[opt.argidx+1] == "cvc5") opt.solver = opt.Solver::CVC5; else - log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1].c_str()); + log_cmd_error("Unknown solver \"%s\".\n", args[opt.argidx+1]); opt.argidx++; } continue; @@ -457,7 +457,7 @@ QbfSolveOptions parse_args(const std::vector &args) { opt.oflag = opt.OptimizationLevel::O2; break; default: - log_cmd_error("unknown argument %s\n", args[opt.argidx].c_str()); + log_cmd_error("unknown argument %s\n", args[opt.argidx]); } continue; } diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc index 5216390da..90b85d709 100644 --- a/passes/sat/sat.cc +++ b/passes/sat/sat.cc @@ -106,9 +106,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -127,9 +127,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -148,7 +148,7 @@ struct SatHelper RTLIL::SigSpec lhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s); show_signal_pool.add(sigmap(lhs)); log("Import unset-constraint for this timestep: %s\n", log_signal(lhs)); @@ -167,28 +167,28 @@ struct SatHelper for (auto &s : sets_def) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].insert(sig); } for (auto &s : sets_any_undef) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[1].insert(sig); } for (auto &s : sets_all_undef) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[2].insert(sig); } for (auto &s : sets_def_at[timestep]) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].insert(sig); sets_def_undef[1].erase(sig); sets_def_undef[2].erase(sig); @@ -197,7 +197,7 @@ struct SatHelper for (auto &s : sets_any_undef_at[timestep]) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].erase(sig); sets_def_undef[1].insert(sig); sets_def_undef[2].erase(sig); @@ -206,7 +206,7 @@ struct SatHelper for (auto &s : sets_all_undef_at[timestep]) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse set-def expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse set-def expression `%s'.\n", s); sets_def_undef[0].erase(sig); sets_def_undef[1].erase(sig); sets_def_undef[2].insert(sig); @@ -295,9 +295,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs set expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs set expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -362,9 +362,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs proof expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs proof expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -390,9 +390,9 @@ struct SatHelper RTLIL::SigSpec lhs, rhs; if (!RTLIL::SigSpec::parse_sel(lhs, design, module, s.first)) - log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first.c_str()); + log_cmd_error("Failed to parse lhs proof-x expression `%s'.\n", s.first); if (!RTLIL::SigSpec::parse_rhs(lhs, rhs, module, s.second)) - log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second.c_str()); + log_cmd_error("Failed to parse rhs proof-x expression `%s'.\n", s.second); show_signal_pool.add(sigmap(lhs)); show_signal_pool.add(sigmap(rhs)); @@ -540,7 +540,7 @@ struct SatHelper for (auto &s : shows) { RTLIL::SigSpec sig; if (!RTLIL::SigSpec::parse_sel(sig, design, module, s)) - log_cmd_error("Failed to parse show expression `%s'.\n", s.c_str()); + log_cmd_error("Failed to parse show expression `%s'.\n", s); log("Import show expression: %s\n", log_signal(sig)); modelSig.append(sig); } @@ -670,7 +670,7 @@ struct SatHelper rewrite_filename(vcd_file_name); FILE *f = fopen(vcd_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", vcd_file_name, strerror(errno)); log("Dumping SAT model to VCD file %s\n", vcd_file_name); @@ -775,7 +775,7 @@ struct SatHelper rewrite_filename(json_file_name); FILE *f = fopen(json_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", json_file_name, strerror(errno)); log("Dumping SAT model to WaveJSON file '%s'.\n", json_file_name); @@ -1535,7 +1535,7 @@ struct SatPass : public Pass { rewrite_filename(cnf_file_name); FILE *f = fopen(cnf_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name, strerror(errno)); log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); @@ -1639,7 +1639,7 @@ struct SatPass : public Pass { rewrite_filename(cnf_file_name); FILE *f = fopen(cnf_file_name.c_str(), "w"); if (!f) - log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name.c_str(), strerror(errno)); + log_cmd_error("Can't open output file `%s' for writing: %s\n", cnf_file_name, strerror(errno)); log("Dumping CNF to file `%s'.\n", cnf_file_name); cnf_file_name.clear(); diff --git a/passes/sat/sim.cc b/passes/sat/sim.cc index aadea328f..56b207a58 100644 --- a/passes/sat/sim.cc +++ b/passes/sat/sim.cc @@ -2887,7 +2887,7 @@ struct SimPass : public Pass { } else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".yw") == 0) { worker.run_cosim_yw_witness(top_mod, append); } else { - log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str()); + log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename); } } diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc index c5bdd6ecf..9cd02b455 100644 --- a/passes/techmap/abc.cc +++ b/passes/techmap/abc.cc @@ -988,7 +988,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module } if (dff_mode && clk_sig.empty()) - log_cmd_error("Clock domain %s not found.\n", clk_str.c_str()); + log_cmd_error("Clock domain %s not found.\n", clk_str); const AbcConfig &config = run_abc.config; if (config.cleanup) @@ -2322,7 +2322,7 @@ struct AbcPass : public Pass { if (g_arg_from_cmd) cmd_error(args, g_argidx, stringf("Unsupported gate type: %s", g)); else - log_cmd_error("Unsupported gate type: %s", g.c_str()); + log_cmd_error("Unsupported gate type: %s", g); ok_gate: gate_list.push_back(g); ok_alias: diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc index a2a4c4b2c..ce1a75193 100644 --- a/passes/techmap/cellmatch.cc +++ b/passes/techmap/cellmatch.cc @@ -173,7 +173,7 @@ struct CellmatchPass : Pass { derive_luts = true; } else if (args[argidx] == "-lib" && argidx + 1 < args.size()) { if (!saved_designs.count(args[++argidx])) - log_cmd_error("No design '%s' found!\n", args[argidx].c_str()); + log_cmd_error("No design '%s' found!\n", args[argidx]); lib = saved_designs.at(args[argidx]); } else { break; diff --git a/passes/techmap/constmap.cc b/passes/techmap/constmap.cc index f0757403d..6d18b8494 100644 --- a/passes/techmap/constmap.cc +++ b/passes/techmap/constmap.cc @@ -82,7 +82,7 @@ struct ConstmapPass : public Pass { } } if (!has_port) - log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype.c_str(), cell_portname.c_str()); + log_cmd_error("Cell type '%s' does not have port '%s'.\n", celltype, cell_portname); bool has_param = false; for (auto &p : existing->avail_parameters){ @@ -91,7 +91,7 @@ struct ConstmapPass : public Pass { } if (!has_param) - log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype.c_str(), cell_paramname.c_str()); + log_cmd_error("Cell type '%s' does not have parameter '%s'.\n", celltype, cell_paramname); } diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc index 6527b683e..7461e21d8 100644 --- a/passes/techmap/extract.cc +++ b/passes/techmap/extract.cc @@ -605,7 +605,7 @@ struct ExtractPass : public Pass { f.open(filename.c_str()); if (f.fail()) { delete map; - log_cmd_error("Can't open map file `%s'.\n", filename.c_str()); + log_cmd_error("Can't open map file `%s'.\n", filename); } Frontend::frontend_call(map, &f, filename, (filename.size() > 3 && filename.compare(filename.size()-3, std::string::npos, ".il") == 0 ? "rtlil" : "verilog")); f.close(); diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc index 75a63b2e0..f882aa356 100644 --- a/passes/tests/test_cell.cc +++ b/passes/tests/test_cell.cc @@ -958,7 +958,7 @@ struct TestCellPass : public Pass { if (args[argidx] == "-vlog" && argidx+1 < GetSize(args)) { vlog_file.open(args[++argidx], std::ios_base::trunc); if (!vlog_file.is_open()) - log_cmd_error("Failed to open output file `%s'.\n", args[argidx].c_str()); + log_cmd_error("Failed to open output file `%s'.\n", args[argidx]); continue; } if (args[argidx] == "-bloat" && argidx+1 < GetSize(args)) { @@ -1079,7 +1079,7 @@ struct TestCellPass : public Pass { for (; argidx < GetSize(args); argidx++) { if (args[argidx].rfind("-", 0) == 0) - log_cmd_error("Unexpected option: %s\n", args[argidx].c_str()); + log_cmd_error("Unexpected option: %s\n", args[argidx]); if (args[argidx] == "all") { for (auto &it : cell_types) diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 0e6553fa1..3b95ff91e 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -236,7 +236,7 @@ struct SynthPass : public ScriptPass if (args[argidx] == "-carry") { carry_mode = args[++argidx]; if (carry_mode != "none" && carry_mode != "ha") - log_cmd_error("Unsupported carry style: %s\n", carry_mode.c_str()); + log_cmd_error("Unsupported carry style: %s\n", carry_mode); continue; } if (args[argidx] == "-noflatten") { diff --git a/techlibs/greenpak4/synth_greenpak4.cc b/techlibs/greenpak4/synth_greenpak4.cc index 99fe45dc4..fa52ecfc6 100644 --- a/techlibs/greenpak4/synth_greenpak4.cc +++ b/techlibs/greenpak4/synth_greenpak4.cc @@ -123,7 +123,7 @@ struct SynthGreenPAK4Pass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (part != "SLG46140V" && part != "SLG46620V" && part != "SLG46621V") - log_cmd_error("Invalid part name: '%s'\n", part.c_str()); + log_cmd_error("Invalid part name: '%s'\n", part); log_header(design, "Executing SYNTH_GREENPAK4 pass.\n"); log_push(); diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index d433c0408..0a4144451 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -265,7 +265,7 @@ struct SynthIce40Pass : public ScriptPass if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") - log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str()); + log_cmd_error("Invalid or no device specified: '%s'\n", device_opt); if (abc9 && retime) log_cmd_error("-retime option not currently compatible with -abc9!\n"); diff --git a/techlibs/intel/synth_intel.cc b/techlibs/intel/synth_intel.cc index af0717235..d3202d5cb 100644 --- a/techlibs/intel/synth_intel.cc +++ b/techlibs/intel/synth_intel.cc @@ -174,7 +174,7 @@ struct SynthIntelPass : public ScriptPass { family_opt != "cycloneiv" && family_opt != "cycloneive" && family_opt != "cyclone10lp") - log_cmd_error("Invalid or no family specified: '%s'\n", family_opt.c_str()); + log_cmd_error("Invalid or no family specified: '%s'\n", family_opt); log_header(design, "Executing SYNTH_INTEL pass.\n"); log_push(); diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index e1df20dd7..b13c22518 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -306,7 +306,7 @@ struct SynthLatticePass : public ScriptPass family == "lifmd" || family == "lifmdf") {*/ } else - log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Lattice -family setting: '%s'.\n", family); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); diff --git a/techlibs/microchip/synth_microchip.cc b/techlibs/microchip/synth_microchip.cc index 77cedcd1f..e1d3c393a 100644 --- a/techlibs/microchip/synth_microchip.cc +++ b/techlibs/microchip/synth_microchip.cc @@ -234,7 +234,7 @@ struct SynthMicrochipPass : public ScriptPass { if (family == "polarfire") { lut_size = 4; } else { - log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Microchip -family setting: '%s'.\n", family); } if (!design->full_selection()) diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index a8f4a05d1..3445ea1be 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -218,7 +218,7 @@ struct SynthNanoXplorePass : public ScriptPass } else if (family == "large") { postfix = "_l"; } else - log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid NanoXplore -family setting: '%s'.\n", family); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); diff --git a/techlibs/nexus/synth_nexus.cc b/techlibs/nexus/synth_nexus.cc index 83abd156a..c0df06a21 100644 --- a/techlibs/nexus/synth_nexus.cc +++ b/techlibs/nexus/synth_nexus.cc @@ -249,7 +249,7 @@ struct SynthNexusPass : public ScriptPass { if (family != "lifcl" && family != "lfd2nx") - log_cmd_error("Invalid Nexus -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Nexus -family setting: '%s'.\n", family); if (check_label("begin")) { diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 84f9c48a7..ade6f944c 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -176,7 +176,7 @@ struct SynthQuickLogicPass : public ScriptPass { log_cmd_error("This command only operates on fully selected designs!\n"); if (family != "pp3" && family != "qlf_k6n10f") - log_cmd_error("Invalid family specified: '%s'\n", family.c_str()); + log_cmd_error("Invalid family specified: '%s'\n", family); if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n"); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 4e422c5cd..20b8c98c3 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -310,7 +310,7 @@ struct SynthXilinxPass : public ScriptPass lut_size = 4; widelut_size = 6; } else - log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family.c_str()); + log_cmd_error("Invalid Xilinx -family setting: '%s'.\n", family); if (widemux != 0 && lut_size != 6) log_cmd_error("-widemux is not currently supported for LUT4-based architectures.\n");