diff --git a/tests/abc_new/openroad/macro_logic.ys b/tests/abc_new/openroad/macro_logic.ys
new file mode 100644
index 000000000..86862c701
--- /dev/null
+++ b/tests/abc_new/openroad/macro_logic.ys
@@ -0,0 +1,30 @@
+# https://github.com/The-OpenROAD-Project/OpenROAD/blob/80443953721b0134bed51bbab17a633a575098a6/src/syn/test/macro_test_cells.lib
+
+# logic around a memory macro with bus pins
+read_liberty -lib macro_test_cells.lib
+read_verilog <<EOT
+module top(input clk, we, ce, input [8:0] addr, input [7:0] wd, output [7:0] rd, output p);
+	wire [7:0] q;
+	fakeram_512x8 i_memory (.clk(clk), .we_in(we & ce), .ce_in(ce), .addr_in(addr ^ {9{we}}), .wd_in(wd + 8'd3), .rd_out(q));
+	assign rd = q ^ wd;
+	assign p = ^q;
+endmodule
+EOT
+
+hierarchy -top top
+proc
+design -save gold
+techmap
+abc_new -liberty cm_test_cells.lib
+select -assert-count 1 t:fakeram_512x8
+select -assert-none t:$_*_
+check -assert
+read_verilog cells_sim.v
+flatten
+opt_clean
+design -stash gate
+design -copy-from gold -as gold top
+design -copy-from gate -as gate top
+equiv_make gold gate equiv
+equiv_simple
+equiv_status -assert
diff --git a/tests/abc_new/openroad/macro_test_cells.lib b/tests/abc_new/openroad/macro_test_cells.lib
new file mode 100644
index 000000000..d9f3d6b46
--- /dev/null
+++ b/tests/abc_new/openroad/macro_test_cells.lib
@@ -0,0 +1,68 @@
+/* https://github.com/The-OpenROAD-Project/OpenROAD/blob/80443953721b0134bed51bbab17a633a575098a6/src/syn/test/macro_test_cells.lib */
+library(macro_test) {
+  delay_model : table_lookup;
+  time_unit : "1ns";
+  voltage_unit : "1V";
+  current_unit : "1mA";
+  capacitive_load_unit(1, pf);
+  type (fakeram_512x8_DATA) {
+    base_type : array ;
+    data_type : bit ;
+    bit_width : 8;
+    bit_from : 7;
+    bit_to : 0 ;
+    downto : true ;
+  }
+  type (fakeram_512x8_ADDRESS) {
+    base_type : array ;
+    data_type : bit ;
+    bit_width : 9;
+    bit_from : 8;
+    bit_to : 0 ;
+    downto : true ;
+  }
+  cell(fakeram_512x8) {
+    area : 171.993;
+    interface_timing : true;
+    memory() {
+      type : ram;
+      address_width : 9;
+      word_width : 8;
+    }
+    pin(clk) {
+      direction : input;
+      capacitance : 0.025;
+      clock : true;
+    }
+    bus(rd_out) {
+      bus_type : fakeram_512x8_DATA;
+      direction : output;
+      max_capacitance : 0.500;
+      memory_read() {
+        address : addr_in;
+      }
+    }
+    pin(we_in) {
+      direction : input;
+      capacitance : 0.005;
+    }
+    pin(ce_in) {
+      direction : input;
+      capacitance : 0.005;
+    }
+    bus(addr_in) {
+      bus_type : fakeram_512x8_ADDRESS;
+      direction : input;
+      capacitance : 0.005;
+    }
+    bus(wd_in) {
+      bus_type : fakeram_512x8_DATA;
+      memory_write() {
+        address : addr_in;
+        clocked_on : "clk";
+      }
+      direction : input;
+      capacitance : 0.005;
+    }
+  }
+}