From 34b5c6d0622f395b569543fa5c166a304253b535 Mon Sep 17 00:00:00 2001 From: phsauter Date: Thu, 13 Jun 2024 22:40:12 +0200 Subject: [PATCH 01/16] peepopt: avoid shift-amount underflow --- passes/pmgen/peepopt_shiftadd.pmg | 5 ++++- tests/opt/bug4413.ys | 15 +++++++++++++++ 2 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 tests/opt/bug4413.ys diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg index e690ff651..875559790 100644 --- a/passes/pmgen/peepopt_shiftadd.pmg +++ b/passes/pmgen/peepopt_shiftadd.pmg @@ -66,7 +66,8 @@ match add define offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A)) // checking some value boundaries as well: - // data[...-c +:W1] is fine for +/-var (pad at LSB, all data still accessible) + // data[...-c +:W1] is fine for any signed var (pad at LSB, all data still accessible) + // unsigned shift may underflow (eg var-3 with var<3) -> cannot be converted // data[...+c +:W1] is only fine for +var(add) and var unsigned // (+c cuts lower C bits, making them inaccessible, a signed var could try to access them) // either its an add or the variable port is A (it must be positive) @@ -74,6 +75,8 @@ match add // -> data[var+c +:W1] (with var signed) is illegal filter !(!offset_negative && varport_signed) + // -> data >> (var-c) (with var unsigned) is illegal + filter !(offset_negative && !varport_signed) // state-variables are assigned at the end only: // shift the log2scale offset in-front of add to get true value: (var+c)< (var<> shift2; +endmodule + +EOT + +equiv_opt -assert peepopt From 74e504330a75afe43117d8ef4ee350f9d6000c74 Mon Sep 17 00:00:00 2001 From: Philippe Sauter Date: Fri, 14 Jun 2024 13:01:18 +0200 Subject: [PATCH 02/16] peepopt: fix sign check in shiftadd --- passes/pmgen/peepopt_shiftadd.pmg | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/passes/pmgen/peepopt_shiftadd.pmg b/passes/pmgen/peepopt_shiftadd.pmg index 875559790..161effe43 100644 --- a/passes/pmgen/peepopt_shiftadd.pmg +++ b/passes/pmgen/peepopt_shiftadd.pmg @@ -63,7 +63,8 @@ match add define constport_signed param(add, !varport_A ? \A_SIGNED : \B_SIGNED).as_bool() define varport_signed param(add, varport_A ? \A_SIGNED : \B_SIGNED).as_bool(); - define offset_negative ((port(add, constport).bits().back() == State::S1) ^ (is_sub && varport_A)) + define const_negative (constport_signed && (port(add, constport).bits().back() == State::S1)) + define offset_negative ((is_sub && varport_A) ^ const_negative) // checking some value boundaries as well: // data[...-c +:W1] is fine for any signed var (pad at LSB, all data still accessible) From 7e341429651d4efa38d829250631d63cb79840ce Mon Sep 17 00:00:00 2001 From: Roland Coeurjoly Date: Tue, 30 Jul 2024 22:47:30 +0200 Subject: [PATCH 03/16] Run nix build also on macos. Build with more logs --- .github/workflows/extra-builds.yml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/.github/workflows/extra-builds.yml b/.github/workflows/extra-builds.yml index d7c6e13ff..1a00d0163 100644 --- a/.github/workflows/extra-builds.yml +++ b/.github/workflows/extra-builds.yml @@ -86,7 +86,11 @@ jobs: name: "Build nix flake" needs: pre_job if: needs.pre_job.outputs.should_skip != 'true' - runs-on: ubuntu-latest + runs-on: ${{ matrix.os }} + strategy: + matrix: + os: [ubuntu-latest, macos-latest] + fail-fast: false steps: - uses: actions/checkout@v4 with: @@ -94,4 +98,4 @@ jobs: - uses: cachix/install-nix-action@v26 with: install_url: https://releases.nixos.org/nix/nix-2.18.1/install - - run: nix build .?submodules=1 + - run: nix build .?submodules=1 -L From d7091777704b725f9072b84651a3d5c6c79843b2 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Thu, 15 Aug 2024 09:34:23 +1200 Subject: [PATCH 04/16] test-compile: Downgrade to focal --- .github/workflows/test-compile.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test-compile.yml b/.github/workflows/test-compile.yml index a892c91ce..089e65ca7 100644 --- a/.github/workflows/test-compile.yml +++ b/.github/workflows/test-compile.yml @@ -40,8 +40,8 @@ jobs: - os: macos-13 compiler: 'clang' # oldest clang not available on ubuntu-latest - - os: ubuntu-22.04 - compiler: 'clang-11' + - os: ubuntu-20.04 + compiler: 'clang-10' fail-fast: false steps: - name: Checkout Yosys From 1eaf4e0790d0336e0c30bfd3341629c68c86d544 Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Thu, 15 Aug 2024 00:17:57 +0000 Subject: [PATCH 05/16] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 343fa50ef..a2803ed59 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.44+9 +YOSYS_VER := 0.44+16 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From 3b63ab07ae289397573d32f2851cd78aedeeea94 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 16 Aug 2024 10:43:51 +1200 Subject: [PATCH 06/16] docs: Build RTD artifacts directly Use rtds-action instead of yosys-cmd-ref repo. Add rtds_action to docs configuration. Add `.readthedocs.yaml`. Update `DOCS_USAGE_` make target to be able to use pre-generated executables without forcing a remake. --- .github/workflows/test-verific.yml | 71 ++++++++++++++++++++---------- .readthedocs.yaml | 19 ++++++++ Makefile | 8 ++-- docs/source/conf.py | 8 +++- docs/source/requirements.txt | 1 + 5 files changed, 78 insertions(+), 29 deletions(-) create mode 100644 .readthedocs.yaml diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index e08f7bd2e..d89634009 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -47,30 +47,6 @@ jobs: run: | make install DESTDIR=${GITHUB_WORKSPACE}/.local PREFIX= - - name: Checkout Documentation - if: ${{ github.ref == 'refs/heads/main' }} - uses: actions/checkout@v4 - with: - path: 'yosys-cmd-ref' - repository: 'YosysHQ-Docs/yosys-cmd-ref' - fetch-depth: 0 - token: ${{ secrets.CI_DOCS_UPDATE_PAT }} - persist-credentials: true - - - name: Update documentation - if: ${{ github.ref == 'refs/heads/main' }} - run: | - make docs - rm -rf docs/build - cd yosys-cmd-ref - rm -rf * - git checkout README.md - cp -R ../docs/* . - rm -rf util/__pycache__ - git add -A . - git diff-index --quiet HEAD || git commit -m "Update" - git push - - name: Checkout SBY uses: actions/checkout@v4 with: @@ -94,3 +70,50 @@ jobs: if: ${{ github.ref == 'refs/heads/main' }} run: | make -C sby run_ci + + prepare-docs: + name: Generate docs artifact + needs: pre_job, test-verific + if: needs.pre_job.outputs.should_skip != 'true' + runs-on: [self-hosted, linux, x64] + steps: + - name: Checkout Yosys + uses: actions/checkout@v4 + with: + persist-credentials: false + submodules: true + - name: Runtime environment + run: | + echo "procs=$(nproc)" >> $GITHUB_ENV + + - name: Build Yosys + run: | + make config-clang + echo "ENABLE_VERIFIC := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf + echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf + echo "ENABLE_CCACHE := 1" >> Makefile.conf + make -j${{ env.procs }} ENABLE_LTO=1 + + - name: Prepare docs + shell: bash + run: + make docs/source/cmd/abc.rst docs/gen_examples docs/gen_images docs/guidelines docs/usage docs/reqs TARGETS= EXTRA_TARGETS= + + - name: Upload artifact + uses: actions/upload-artifact@v4 + with: + name: cmd-ref-${{ github.sha }} + path: | + docs/source/cmd + docs/source/generated + docs/source/_images + docs/source/code_examples + + - name: Trigger RTDs build + uses: dfm/rtds-action@v1.1.0 + with: + webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }} + webhook_token: ${{ secrets.RTDS_WEBHOOK_TOKEN }} + commit_ref: ${{ github.ref }} diff --git a/.readthedocs.yaml b/.readthedocs.yaml new file mode 100644 index 000000000..cb700dc1c --- /dev/null +++ b/.readthedocs.yaml @@ -0,0 +1,19 @@ +# .readthedocs.yaml +# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details + +version: 2 + +build: + os: ubuntu-22.04 + tools: + python: '3.12' + +formats: + - pdf + +sphinx: + configuration: docs/source/conf.py + +python: + install: + - requirements: docs/source/requirements.txt diff --git a/Makefile b/Makefile index a2803ed59..44c77eeaa 100644 --- a/Makefile +++ b/Makefile @@ -984,8 +984,8 @@ docs/guidelines docs/source/generated: # some commands return an error and print the usage text to stderr define DOC_USAGE_STDERR -docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated - -$(Q) ./$$< --help 2> $$@ +docs/source/generated/$(1): $(TARGETS) docs/source/generated + -$(Q) ./$(PROGRAM_PREFIX)$(1) --help 2> $$@ endef DOCS_USAGE_STDERR := yosys-config yosys-filterlib @@ -998,8 +998,8 @@ $(foreach usage,$(DOCS_USAGE_STDERR),$(eval $(call DOC_USAGE_STDERR,$(usage)))) # others print to stdout define DOC_USAGE_STDOUT -docs/source/generated/$(1): $(PROGRAM_PREFIX)$(1) docs/source/generated - $(Q) ./$$< --help > $$@ +docs/source/generated/$(1): $(TARGETS) docs/source/generated + $(Q) ./$(PROGRAM_PREFIX)$(1) --help > $$@ endef DOCS_USAGE_STDOUT := yosys yosys-smtbmc yosys-witness $(foreach usage,$(DOCS_USAGE_STDOUT),$(eval $(call DOC_USAGE_STDOUT,$(usage)))) diff --git a/docs/source/conf.py b/docs/source/conf.py index 2fdd43a31..23efe2b43 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -41,7 +41,13 @@ html_static_path = ['_static', "_images"] pygments_style = 'colorful' highlight_language = 'none' -extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex'] +extensions = ['sphinx.ext.autosectionlabel', 'sphinxcontrib.bibtex', 'rtds_action'] + +# rtds_action +rtds_action_github_repo = "YosysHQ/yosys" +rtds_action_path = "." +rtds_action_artifact_prefix = "cmd-ref-" +rtds_action_github_token = os.environ["GITHUB_TOKEN"] # Ensure that autosectionlabel will produce unique names autosectionlabel_prefix_document = True diff --git a/docs/source/requirements.txt b/docs/source/requirements.txt index 74c8dd090..dbba55832 100644 --- a/docs/source/requirements.txt +++ b/docs/source/requirements.txt @@ -1,2 +1,3 @@ furo sphinxcontrib-bibtex +rtds-action From 7bd3c7b968432896771d2294103bd7a8b88487d7 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Fri, 16 Aug 2024 10:43:51 +1200 Subject: [PATCH 07/16] Fix test-verific.yml --- .github/workflows/test-verific.yml | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index d89634009..b76718c21 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -3,7 +3,7 @@ name: Build and run tests with Verific (Linux) on: [push, pull_request] jobs: - pre_job: + pre-job: runs-on: ubuntu-latest outputs: should_skip: ${{ steps.skip_check.outputs.should_skip }} @@ -20,8 +20,8 @@ jobs: skip_after_successful_duplicate: 'false' test-verific: - needs: pre_job - if: needs.pre_job.outputs.should_skip != 'true' + needs: pre-job + if: needs.pre-job.outputs.should_skip != 'true' runs-on: [self-hosted, linux, x64] steps: - name: Checkout Yosys @@ -73,8 +73,8 @@ jobs: prepare-docs: name: Generate docs artifact - needs: pre_job, test-verific - if: needs.pre_job.outputs.should_skip != 'true' + needs: [pre-job, test-verific] + if: needs.pre-job.outputs.should_skip != 'true' runs-on: [self-hosted, linux, x64] steps: - name: Checkout Yosys From 3dd32d741ac74914e4839de5b36dc58979cca8e3 Mon Sep 17 00:00:00 2001 From: KrystalDelusion <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 5 Aug 2024 11:20:05 +1200 Subject: [PATCH 08/16] Stop unconditionally building abc _What are the reasons/motivation for this change?_ abc builds unconditional because `check-git-abc` is a phony prerequisite and therefore always runs, and since it always runs it will always trigger abc to rebuild. _Explain how this is achieved._ Convert `check-git-abc` to an order-only prerequisite. It still runs as before, but no longer triggers yosys-abc to rebuild when it does. _If applicable, please suggest to reviewers how they can test the change._ --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index a2803ed59..5594a605a 100644 --- a/Makefile +++ b/Makefile @@ -807,7 +807,7 @@ check-git-abc: exit 1; \ fi -abc/abc$(EXE) abc/libabc.a: check-git-abc +abc/abc$(EXE) abc/libabc.a: | check-git-abc $(P) $(Q) mkdir -p abc && $(MAKE) -C $(PROGRAM_PREFIX)abc -f "$(realpath $(YOSYS_SRC)/abc/Makefile)" ABCSRC="$(realpath $(YOSYS_SRC)/abc/)" $(S) $(ABCMKARGS) $(if $(filter %.a,$@),PROG="abc",PROG="abc$(EXE)") MSG_PREFIX="$(eval P_OFFSET = 5)$(call P_SHOW)$(eval P_OFFSET = 10) ABC: " $(if $(filter %.a,$@),libabc.a) From 5fb3c0b1d982eebc3b996c4fa4e42ed98030440d Mon Sep 17 00:00:00 2001 From: "github-actions[bot]" <41898282+github-actions[bot]@users.noreply.github.com> Date: Sat, 17 Aug 2024 00:17:44 +0000 Subject: [PATCH 09/16] Bump version --- Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Makefile b/Makefile index 5594a605a..556d1726e 100644 --- a/Makefile +++ b/Makefile @@ -153,7 +153,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.44+16 +YOSYS_VER := 0.44+20 # Note: We arrange for .gitcommit to contain the (short) commit hash in # tarballs generated with git-archive(1) using .gitattributes. The git repo From d80d4dc51c2deebbd26b9eab6af00298e979c957 Mon Sep 17 00:00:00 2001 From: Saish Karole <72208314+NachtSpyder04@users.noreply.github.com> Date: Sat, 17 Aug 2024 15:47:00 +0530 Subject: [PATCH 10/16] [Docs]:Add new cell type help messages (#1) * add shift operators description * update shift operations' descriptions, add desciptions for add, sub, logic_*, tribuf, mux, demux, concat, pow and comparison operators --- techlibs/common/simlib.v | 141 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index 7dc03da6d..de7726582 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -371,6 +371,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $shl (A, B, Y) +//- +//- A logical shift-left operation. This corresponds to the Verilog '<<' operator. +//- module \$shl (A, B, Y); parameter A_SIGNED = 0; @@ -395,6 +401,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $shr (A, B, Y) +//- +//- A logical shift-right operation. This corresponds to the Verilog '>>' operator. +//- module \$shr (A, B, Y); parameter A_SIGNED = 0; @@ -419,6 +431,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $sshl (A, B, Y) +//- +//- An arithmatic shift-left operation. This corresponds to the Verilog '<<<' operator. +//- module \$sshl (A, B, Y); parameter A_SIGNED = 0; @@ -443,6 +461,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $sshr (A, B, Y) +//- +//- An arithmatic shift-right operation. This corresponds to the Verilog '>>>' operator. +//- module \$sshr (A, B, Y); parameter A_SIGNED = 0; @@ -639,6 +663,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $lt (A, B, Y) +//- +//- A less-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<' operator. +//- module \$lt (A, B, Y); parameter A_SIGNED = 0; @@ -663,6 +693,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $le (A, B, Y) +//- +//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<=' operator. +//- module \$le (A, B, Y); parameter A_SIGNED = 0; @@ -687,6 +723,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $eq (A, B, Y) +//- +//- An equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '==' operator. +//- module \$eq (A, B, Y); parameter A_SIGNED = 0; @@ -711,6 +753,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $ne (A, B, Y) +//- +//- An inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!=' operator. +//- module \$ne (A, B, Y); parameter A_SIGNED = 0; @@ -735,6 +783,13 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $eqx (A, B, Y) +//- +//- An exact equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '===' operator. +//- Unlike equality comparison that can give 'x' as output, an exact equality comparison will strictly give '0' or '1' as output. +//- module \$eqx (A, B, Y); parameter A_SIGNED = 0; @@ -759,6 +814,13 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $nex (A, B, Y) +//- +//- An exact inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!==' operator. +//- Unlike inequality comparison that can give 'x' as output, an exact inequality comparison will strictly give '0' or '1' as output. +//- module \$nex (A, B, Y); parameter A_SIGNED = 0; @@ -783,6 +845,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $ge (A, B, Y) +//- +//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>=' operator. +//- module \$ge (A, B, Y); parameter A_SIGNED = 0; @@ -807,6 +875,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $gt (A, B, Y) +//- +//- A greater-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>' operator. +//- module \$gt (A, B, Y); parameter A_SIGNED = 0; @@ -831,6 +905,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $add (A, B, Y) +//- +//- Addition of inputs 'A' and 'B'. This corresponds to the Verilog '+' operator. +//- module \$add (A, B, Y); parameter A_SIGNED = 0; @@ -855,6 +935,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $sub (A, B, Y) +//- +//- Subtraction between inputs 'A' and 'B'. This corresponds to the Verilog '-' operator. +//- module \$sub (A, B, Y); parameter A_SIGNED = 0; @@ -879,6 +965,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $mul (A, B, Y) +//- +//- Multiplication of inputs 'A' and 'B'. This corresponds to the Verilog '*' operator. +//- module \$mul (A, B, Y); parameter A_SIGNED = 0; @@ -1191,6 +1283,13 @@ endgenerate endmodule // -------------------------------------------------------- + +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $pow (A, B, Y) +//- +//- Exponentiation of inputs (Y = A ** B). This corresponds to the Verilog '**' operator. +//- `ifndef SIMLIB_NOPOW module \$pow (A, B, Y); @@ -1222,6 +1321,12 @@ endmodule `endif // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $logic_not (A, Y) +//- +//- A logical inverter. This corresponds to the Verilog unary prefix '!' operator. +//- module \$logic_not (A, Y); parameter A_SIGNED = 0; @@ -1243,6 +1348,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $logic_and (A, B, Y) +//- +//- A logical AND. This corresponds to the Verilog '&&' operator. +//- module \$logic_and (A, B, Y); parameter A_SIGNED = 0; @@ -1267,6 +1378,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $logic_or (A, B, Y) +//- +//- A logical OR. This corresponds to the Verilog '||' operator. +//- module \$logic_or (A, B, Y); parameter A_SIGNED = 0; @@ -1306,6 +1423,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $concat (A, B, Y) +//- +//- Concatenation of inputs into a single output ( Y = {B, A} ). +//- module \$concat (A, B, Y); parameter A_WIDTH = 0; @@ -1321,6 +1444,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $mux (A, B, S, Y) +//- +//- Multiplexer i.e selecting inputs based on select signal. +//- module \$mux (A, B, S, Y); parameter WIDTH = 0; @@ -1396,6 +1525,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $demux (A, S, Y) +//- +//- Demultiplexer i.e routing single input to several outputs based on select signal. +//- module \$demux (A, S, Y); parameter WIDTH = 1; @@ -1460,6 +1595,12 @@ endmodule // -------------------------------------------------------- +// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| +//- +//- $tribuf (A, EN, Y) +//- +//- A tri-state buffer. This buffer conditionally passes the input to the output based on the enable signal. +//- module \$tribuf (A, EN, Y); parameter WIDTH = 0; From 34aabd56cca445996d332343b06a29fadd78d534 Mon Sep 17 00:00:00 2001 From: Saish Karole <72208314+NachtSpyder04@users.noreply.github.com> Date: Sun, 18 Aug 2024 20:12:53 +0530 Subject: [PATCH 11/16] Apply suggestions from code review MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Martin PoviĊĦer --- techlibs/common/simlib.v | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index de7726582..e035e92c4 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -1288,7 +1288,7 @@ endmodule //- //- $pow (A, B, Y) //- -//- Exponentiation of inputs (Y = A ** B). This corresponds to the Verilog '**' operator. +//- Exponentiation of an input (Y = A ** B). This corresponds to the Verilog '**' operator. //- `ifndef SIMLIB_NOPOW @@ -1448,7 +1448,7 @@ endmodule //- //- $mux (A, B, S, Y) //- -//- Multiplexer i.e selecting inputs based on select signal. +//- Multiplexer i.e selecting between two inputs based on select signal. //- module \$mux (A, B, S, Y); @@ -1529,7 +1529,7 @@ endmodule //- //- $demux (A, S, Y) //- -//- Demultiplexer i.e routing single input to several outputs based on select signal. +//- Demultiplexer i.e routing single input to several outputs based on select signal. Unselected outputs are driven to zero. //- module \$demux (A, S, Y); @@ -1599,7 +1599,7 @@ endmodule //- //- $tribuf (A, EN, Y) //- -//- A tri-state buffer. This buffer conditionally passes the input to the output based on the enable signal. +//- A tri-state buffer. This buffer conditionally drives the output with the value of the input based on the enable signal. //- module \$tribuf (A, EN, Y); From aa60255e0e3750207bfcab8b3545f81e1cefa202 Mon Sep 17 00:00:00 2001 From: NachtSpyder04 Date: Sun, 18 Aug 2024 20:27:35 +0530 Subject: [PATCH 12/16] update help messages that went beyond line length limit --- techlibs/common/simlib.v | 52 +++++++++++++++++++++++++++------------- 1 file changed, 35 insertions(+), 17 deletions(-) diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index e035e92c4..5bbad34f6 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -435,7 +435,8 @@ endmodule //- //- $sshl (A, B, Y) //- -//- An arithmatic shift-left operation. This corresponds to the Verilog '<<<' operator. +//- An arithmatic shift-left operation. +//- This corresponds to the Verilog '<<<' operator. //- module \$sshl (A, B, Y); @@ -465,7 +466,8 @@ endmodule //- //- $sshr (A, B, Y) //- -//- An arithmatic shift-right operation. This corresponds to the Verilog '>>>' operator. +//- An arithmatic shift-right operation. +//- This corresponds to the Verilog '>>>' operator. //- module \$sshr (A, B, Y); @@ -667,7 +669,8 @@ endmodule //- //- $lt (A, B, Y) //- -//- A less-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<' operator. +//- A less-than comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '<' operator. //- module \$lt (A, B, Y); @@ -697,7 +700,8 @@ endmodule //- //- $le (A, B, Y) //- -//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '<=' operator. +//- A less-than-or-equal-to comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '<=' operator. //- module \$le (A, B, Y); @@ -727,7 +731,8 @@ endmodule //- //- $eq (A, B, Y) //- -//- An equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '==' operator. +//- An equality comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '==' operator. //- module \$eq (A, B, Y); @@ -757,7 +762,8 @@ endmodule //- //- $ne (A, B, Y) //- -//- An inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!=' operator. +//- An inequality comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '!=' operator. //- module \$ne (A, B, Y); @@ -787,8 +793,10 @@ endmodule //- //- $eqx (A, B, Y) //- -//- An exact equality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '===' operator. -//- Unlike equality comparison that can give 'x' as output, an exact equality comparison will strictly give '0' or '1' as output. +//- An exact equality comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '===' operator. +//- Unlike equality comparison that can give 'x' as output, +//- an exact equality comparison will strictly give '0' or '1' as output. //- module \$eqx (A, B, Y); @@ -818,8 +826,10 @@ endmodule //- //- $nex (A, B, Y) //- -//- An exact inequality comparison between inputs 'A' and 'B'. This corresponds to the Verilog '!==' operator. -//- Unlike inequality comparison that can give 'x' as output, an exact inequality comparison will strictly give '0' or '1' as output. +//- An exact inequality comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '!==' operator. +//- Unlike inequality comparison that can give 'x' as output, +//- an exact inequality comparison will strictly give '0' or '1' as output. //- module \$nex (A, B, Y); @@ -849,7 +859,8 @@ endmodule //- //- $ge (A, B, Y) //- -//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>=' operator. +//- A greater-than-or-equal-to comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '>=' operator. //- module \$ge (A, B, Y); @@ -879,7 +890,8 @@ endmodule //- //- $gt (A, B, Y) //- -//- A greater-than comparison between inputs 'A' and 'B'. This corresponds to the Verilog '>' operator. +//- A greater-than comparison between inputs 'A' and 'B'. +//- This corresponds to the Verilog '>' operator. //- module \$gt (A, B, Y); @@ -939,7 +951,8 @@ endmodule //- //- $sub (A, B, Y) //- -//- Subtraction between inputs 'A' and 'B'. This corresponds to the Verilog '-' operator. +//- Subtraction between inputs 'A' and 'B'. +//- This corresponds to the Verilog '-' operator. //- module \$sub (A, B, Y); @@ -969,7 +982,8 @@ endmodule //- //- $mul (A, B, Y) //- -//- Multiplication of inputs 'A' and 'B'. This corresponds to the Verilog '*' operator. +//- Multiplication of inputs 'A' and 'B'. +//- This corresponds to the Verilog '*' operator. //- module \$mul (A, B, Y); @@ -1288,7 +1302,8 @@ endmodule //- //- $pow (A, B, Y) //- -//- Exponentiation of an input (Y = A ** B). This corresponds to the Verilog '**' operator. +//- Exponentiation of an input (Y = A ** B). +//- This corresponds to the Verilog '**' operator. //- `ifndef SIMLIB_NOPOW @@ -1529,7 +1544,8 @@ endmodule //- //- $demux (A, S, Y) //- -//- Demultiplexer i.e routing single input to several outputs based on select signal. Unselected outputs are driven to zero. +//- Demultiplexer i.e routing single input to several outputs based on select signal. +//- Unselected outputs are driven to zero. //- module \$demux (A, S, Y); @@ -1599,7 +1615,9 @@ endmodule //- //- $tribuf (A, EN, Y) //- -//- A tri-state buffer. This buffer conditionally drives the output with the value of the input based on the enable signal. +//- A tri-state buffer. +//- This buffer conditionally drives the output with the value of the input +//- based on the enable signal. //- module \$tribuf (A, EN, Y); From d1b767ea8b453fc234928b12653d1cc2c2d69a19 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?David=20Lanzend=C3=B6rfer?= Date: Sat, 17 Aug 2024 01:15:37 +0100 Subject: [PATCH 13/16] Adding missing to Gowin tech files Without OSER4_MEM, IDES4_MEM and DQS the synthesis of my Rocket Chip design for my Sipeed Tang FPGA fails. --- techlibs/gowin/cells_sim.v | 52 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/techlibs/gowin/cells_sim.v b/techlibs/gowin/cells_sim.v index 3edf6c8fc..96121a881 100644 --- a/techlibs/gowin/cells_sim.v +++ b/techlibs/gowin/cells_sim.v @@ -618,6 +618,21 @@ module OSER4(D3, D2, D1, D0, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0); parameter HWL = "false"; endmodule +module OSER4_MEM (Q0, Q1, D0, D1, D2, D3, TX0, TX1, PCLK, FCLK, TCLK, RESET) ; + parameter GSREN = ""; + parameter LSREN = ""; + parameter HWL = ""; + parameter TCLK_SOURCE = ""; + parameter TXCLK_POL = ""; + + input D0, D1, D2, D3; + input TX0, TX1; + input PCLK, FCLK, TCLK, RESET; + output Q0, Q1; + + parameter ID = ""; +endmodule + module OSER8(D7, D6, D5, D4, D3, D2, D1, D0, TX3, TX2, TX1, TX0, FCLK, PCLK, RESET, Q1, Q0); output Q1; output Q0; @@ -729,6 +744,21 @@ RESET, CALIB, D); parameter LSREN = "true"; endmodule +module IDES4_MEM (Q0, Q1, Q2, Q3, D, WADDR, +RADDR, CALIB, PCLK, FCLK, ICLK, RESET) ; +parameter GSREN = ""; +parameter LSREN = ""; + +input D, ICLK, FCLK, PCLK; +input [2:0] WADDR; +input [2:0] RADDR; +input CALIB, RESET; + +output Q0,Q1,Q2,Q3; + +parameter ID = ""; +endmodule + module IDES8(Q7, Q6, Q5, Q4, Q3, Q2, Q1, Q0, FCLK, PCLK, RESET, CALIB, D); input D; @@ -842,6 +872,28 @@ module IDDRC(D, CLK, CLEAR, Q0, Q1); parameter Q1_INIT = 1'b0; endmodule +module DQS(DQSR90, DQSW0, DQSW270, RPOINT, WPOINT, RVALID, RBURST, RFLAG, +WFLAG, DQSIN, DLLSTEP, WSTEP, READ, RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, +HOLD, RCLKSEL, PCLK, FCLK, RESET) ; + input DQSIN,PCLK,FCLK,RESET; + input [3:0] READ; + input [2:0] RCLKSEL; + input [7:0] DLLSTEP; + input [7:0] WSTEP; + input RLOADN, RMOVE, RDIR, WLOADN, WMOVE, WDIR, HOLD; + + output DQSR90, DQSW0, DQSW270; + output [2:0] RPOINT, WPOINT; + output RVALID,RBURST, RFLAG, WFLAG; + + parameter FIFO_MODE_SEL = ""; + parameter RD_PNTR = ""; + parameter DQS_MODE = ""; + parameter HWL = ""; + parameter GSREN = ""; + parameter ID = ""; +endmodule + (* blackbox *) module ODDR(D0, D1, TX, CLK, Q0, Q1); input D0; From 8773cf77214824de688f7b155c10bc650393510b Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 19 Aug 2024 21:24:48 +1200 Subject: [PATCH 14/16] test-verific: Use fast runner --- .github/workflows/test-verific.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index b76718c21..fc3c3dacf 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -22,7 +22,7 @@ jobs: test-verific: needs: pre-job if: needs.pre-job.outputs.should_skip != 'true' - runs-on: [self-hosted, linux, x64] + runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys uses: actions/checkout@v4 @@ -75,7 +75,7 @@ jobs: name: Generate docs artifact needs: [pre-job, test-verific] if: needs.pre-job.outputs.should_skip != 'true' - runs-on: [self-hosted, linux, x64] + runs-on: [self-hosted, linux, x64, fast] steps: - name: Checkout Yosys uses: actions/checkout@v4 From 6df0c3d9ec9fa735535dc983e5f5e2559768bc40 Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Mon, 19 Aug 2024 21:25:51 +1200 Subject: [PATCH 15/16] docs: Fix synth_flow generation --- docs/source/code_examples/synth_flow/Makefile | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/docs/source/code_examples/synth_flow/Makefile b/docs/source/code_examples/synth_flow/Makefile index cc5a34b26..7db1c12f4 100644 --- a/docs/source/code_examples/synth_flow/Makefile +++ b/docs/source/code_examples/synth_flow/Makefile @@ -1,13 +1,13 @@ -TARGETS += proc_01 proc_02 proc_03 -TARGETS += memory_01 memory_02 -TARGETS += techmap_01 +DOT_TARGETS += proc_01 proc_02 proc_03 +DOT_TARGETS += memory_01 memory_02 +DOT_TARGETS += techmap_01 PROGRAM_PREFIX := YOSYS ?= ../../../../$(PROGRAM_PREFIX)yosys -DOTS = $(addsuffix .dot,$(TARGETS)) +DOTS = $(addsuffix .dot,$(DOT_TARGETS)) .PHONY: all dots all: dots From 7d779c64a35a07bb521c355f67fe48437d2b177a Mon Sep 17 00:00:00 2001 From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com> Date: Tue, 20 Aug 2024 04:26:16 +1200 Subject: [PATCH 16/16] docs: Only trigger RTDs on main --- .github/workflows/test-verific.yml | 1 + 1 file changed, 1 insertion(+) diff --git a/.github/workflows/test-verific.yml b/.github/workflows/test-verific.yml index fc3c3dacf..627a70d47 100644 --- a/.github/workflows/test-verific.yml +++ b/.github/workflows/test-verific.yml @@ -112,6 +112,7 @@ jobs: docs/source/code_examples - name: Trigger RTDs build + if: ${{ github.ref == 'refs/heads/main' }} uses: dfm/rtds-action@v1.1.0 with: webhook_url: ${{ secrets.RTDS_WEBHOOK_URL }}