From 556a19c611f212b351dbb825514682f284eec31e Mon Sep 17 00:00:00 2001
From: Alan Hu <56959002+ALAN-Hu-1999@users.noreply.github.com>
Date: Sun, 7 Jun 2026 11:44:44 -0700
Subject: [PATCH] Fix meminit enable for initialized memories

---
 frontends/ast/simplify.cc  | 14 +++++++++++---
 tests/various/issue5853.ys | 16 ++++++++++++++++
 2 files changed, 27 insertions(+), 3 deletions(-)
 create mode 100644 tests/various/issue5853.ys

diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 95dca27d8..90dc2145b 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -3687,14 +3687,22 @@ skip_dynamic_range_lvalue_expansion:;
 		}
 		if (assign_data)
 			newNode->children.push_back(std::move(assign_data));
+
+		std::unique_ptr<AstNode> meminit_en = nullptr;
+		if (current_always->type == AST_INITIAL && assign_en && assign_en->children[1]->isConst())
+			meminit_en = assign_en->children[1]->clone();
+
 		if (assign_en)
 			newNode->children.push_back(std::move(assign_en));
 
 		std::unique_ptr<AstNode> wrnode;
-		if (current_always->type == AST_INITIAL)
-			wrnode = std::make_unique<AstNode>(location, AST_MEMINIT, std::move(node_addr), std::move(node_data), std::move(node_en), mkconst_int(location, 1, false));
-		else
+		if (current_always->type == AST_INITIAL) {
+			if (!meminit_en)
+				meminit_en = std::move(node_en);
+			wrnode = std::make_unique<AstNode>(location, AST_MEMINIT, std::move(node_addr), std::move(node_data), std::move(meminit_en), mkconst_int(location, 1, false));
+		} else {
 			wrnode = std::make_unique<AstNode>(location, AST_MEMWR, std::move(node_addr), std::move(node_data), std::move(node_en));
+		}
 		wrnode->str = children[0]->str;
 		wrnode->id2ast = children[0]->id2ast;
 		wrnode->location = location;
diff --git a/tests/various/issue5853.ys b/tests/various/issue5853.ys
new file mode 100644
index 000000000..9d16aa232
--- /dev/null
+++ b/tests/various/issue5853.ys
@@ -0,0 +1,16 @@
+read_verilog <<EOT
+module top(output [31:0] y);
+  reg [31:0] mem [0:3];
+
+  initial begin
+    mem[0] = 32'h00000000;
+    mem[1] = 32'h11111111;
+    mem[2] = 32'h22222222;
+    mem[3] = 32'h33333333;
+  end
+
+  assign y = mem[0];
+endmodule
+EOT
+
+write_verilog