From 547a7156596e0978b14614309bd842909e42881a Mon Sep 17 00:00:00 2001 From: "Emil J. Tywoniak" Date: Tue, 10 Mar 2026 14:09:31 +0100 Subject: [PATCH] tests: adjust to input_port and init behavior (sketchy) --- tests/opt/opt_expr_more.ys | 8 ++++---- tests/opt/opt_expr_or.ys | 16 ++++++++-------- tests/opt/opt_expr_xnor.ys | 2 +- tests/opt/opt_expr_xor.ys | 8 ++++---- 4 files changed, 17 insertions(+), 17 deletions(-) diff --git a/tests/opt/opt_expr_more.ys b/tests/opt/opt_expr_more.ys index 795ae89c4..20b4e0130 100644 --- a/tests/opt/opt_expr_more.ys +++ b/tests/opt/opt_expr_more.ys @@ -50,7 +50,7 @@ opt_expr -fine # The division by zero should be removed select -assert-count 0 t:$div # No cells should be left as it's replaced with constant undef -select -assert-none t:* +select -assert-none t:* t:$input_port %d design -reset read_verilog <