diff --git a/tests/opt/opt_expr_more.ys b/tests/opt/opt_expr_more.ys index 795ae89c4..20b4e0130 100644 --- a/tests/opt/opt_expr_more.ys +++ b/tests/opt/opt_expr_more.ys @@ -50,7 +50,7 @@ opt_expr -fine # The division by zero should be removed select -assert-count 0 t:$div # No cells should be left as it's replaced with constant undef -select -assert-none t:* +select -assert-none t:* t:$input_port %d design -reset read_verilog <