From aba5b279c6ea3c7ef0867f43d2f7d8dc23d9f440 Mon Sep 17 00:00:00 2001 From: George Haworth Date: Fri, 17 Apr 2026 02:10:05 +0300 Subject: [PATCH] Fix RAMB36E1/E2 SDP parity port mapping typo DIPBDIP/DINPBDINP condition checked PORT_W_WIDTH == 71, which never matches any valid SDP width. Should be 72, matching the DIBDI/DINBDIN condition on the line above. This caused data bits 68-69 to be silently overwritten with copies of bits 64-65 on every write. Affects both xc6v (RAMB36E1, Artix-7/Kintex-7/Virtex-7) and xcu (RAMB36E2, UltraScale/UltraScale+) mapping templates. The RAMB18E1/E2 equivalents correctly use == 36. --- techlibs/xilinx/brams_xc6v_map.v | 2 +- techlibs/xilinx/brams_xcu_map.v | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/xilinx/brams_xc6v_map.v b/techlibs/xilinx/brams_xc6v_map.v index b2698a3aa..dfd6dfc9e 100644 --- a/techlibs/xilinx/brams_xc6v_map.v +++ b/techlibs/xilinx/brams_xc6v_map.v @@ -275,7 +275,7 @@ end else if (OPTION_MODE == "FULL") begin .DIADI(DI[31:0]), .DIBDI(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]), .DIPADIP(DIP[3:0]), - .DIPBDIP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]), + .DIPBDIP(PORT_W_WIDTH == 72 ? DIP[7:4] : DIP[3:0]), ); end diff --git a/techlibs/xilinx/brams_xcu_map.v b/techlibs/xilinx/brams_xcu_map.v index d48c21a59..01ee8a953 100644 --- a/techlibs/xilinx/brams_xcu_map.v +++ b/techlibs/xilinx/brams_xcu_map.v @@ -215,7 +215,7 @@ end else if (OPTION_MODE == "FULL") begin .DINADIN(DI[31:0]), .DINBDIN(PORT_W_WIDTH == 72 ? DI[63:32] : DI[31:0]), .DINPADINP(DIP[3:0]), - .DINPBDINP(PORT_W_WIDTH == 71 ? DIP[7:4] : DIP[3:0]), + .DINPBDINP(PORT_W_WIDTH == 72 ? DIP[7:4] : DIP[3:0]), ); end