From 4a69969df498d20e849f677fde51a0740cb70892 Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Thu, 6 Nov 2025 07:50:59 -0800
Subject: [PATCH] Fixup parameters

---
 passes/techmap/abc.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 46bd8b2ab..dd1fcc3db 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1492,6 +1492,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
 					cell->setPort(name, module->wire(remapped_name));
 				}
+				cell->fixup_parameters();
 				design->select(module, cell);
 				continue;
 			}
@@ -1513,6 +1514,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
 					cell->setPort(name, module->wire(remapped_name));
 				}
+				cell->fixup_parameters();
 				design->select(module, cell);
 				continue;
 			}
@@ -1530,6 +1532,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
 					cell->setPort(name, module->wire(remapped_name));
 				}
+				cell->fixup_parameters();
 				design->select(module, cell);
 				continue;
 			}