From 44bab117d7adb1bf13e6d078f5c4ca015d490414 Mon Sep 17 00:00:00 2001 From: Lofty Date: Wed, 22 Jul 2026 13:09:15 +0100 Subject: [PATCH] synth_ice40: remove classic ABC mapping --- .../macro_commands/synth_ice40.ys | 3 - techlibs/ice40/synth_ice40.cc | 69 +++++-------------- tests/arch/ice40/bug1598.ys | 2 +- tests/arch/ice40/bug1626.ys | 2 +- 4 files changed, 21 insertions(+), 55 deletions(-) diff --git a/docs/source/code_examples/macro_commands/synth_ice40.ys b/docs/source/code_examples/macro_commands/synth_ice40.ys index fba5b66b8..45e570a4b 100644 --- a/docs/source/code_examples/macro_commands/synth_ice40.ys +++ b/docs/source/code_examples/macro_commands/synth_ice40.ys @@ -54,7 +54,6 @@ map_gates: ice40_wrapcarry techmap opt -fast - abc -dff -D 1 ice40_opt map_ffs: @@ -65,8 +64,6 @@ map_ffs: ice40_opt -full map_luts: - abc - ice40_opt check techmap simplemap diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 68db38c51..30c331e17 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -45,8 +45,8 @@ struct SynthIce40Pass : public ScriptPass log("This command runs synthesis for iCE40 FPGAs.\n"); log("\n"); log(" -device < hx | lp | u >\n"); - log(" relevant only for '-abc9' flow, optimise timing for the specified\n"); - log(" device. default: hx\n"); + log(" optimise timing for the specified device. default: hx\n"); + log(" (irrelevant if -noabc)\n"); log("\n"); log(" -top \n"); log(" use the specified module as top module\n"); @@ -72,10 +72,7 @@ struct SynthIce40Pass : public ScriptPass log(" do not flatten design before synthesis\n"); log("\n"); log(" -dff\n"); - log(" run 'abc'/'abc9' with -dff option\n"); - log("\n"); - log(" -retime\n"); - log(" run 'abc' with '-dff -D 1' options\n"); + log(" run 'abc9' with -dff option\n"); log("\n"); log(" -nocarry\n"); log(" do not use SB_CARRY cells in output netlist\n"); @@ -97,18 +94,12 @@ struct SynthIce40Pass : public ScriptPass log(" use iCE40 UltraPlus DSP cells for large arithmetic\n"); log("\n"); log(" -noabc\n"); - log(" use built-in Yosys LUT techmapping instead of abc\n"); - log("\n"); - log(" -abc2\n"); - log(" run two passes of 'abc' for slightly improved logic density\n"); + log(" use built-in Yosys LUT techmapping instead of abc9\n"); log("\n"); log(" -vpr\n"); log(" generate an output netlist (and BLIF file) suitable for VPR\n"); log(" (this feature is experimental and incomplete)\n"); log("\n"); - log(" -noabc9\n"); - log(" disable use of new ABC9 flow\n"); - log("\n"); log(" -no-rw-check\n"); log(" marks all recognized read ports as \"return don't-care value on\n"); log(" read/write collision\" (same result as setting the no_rw_check\n"); @@ -127,7 +118,7 @@ struct SynthIce40Pass : public ScriptPass } string top_opt, blif_file, edif_file, json_file, device_opt, latches; - bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, no_rw_check; + bool nocarry, nodffe, nobram, spram, dsp, flatten, noabc, vpr, dff, no_rw_check; int min_ce_use; void clear_flags() override @@ -143,11 +134,8 @@ struct SynthIce40Pass : public ScriptPass spram = false; dsp = false; flatten = true; - retime = false; noabc = false; - abc2 = false; vpr = false; - abc9 = true; device_opt = "hx"; no_rw_check = false; latches = "error"; @@ -194,7 +182,7 @@ struct SynthIce40Pass : public ScriptPass continue; } if (args[argidx] == "-retime") { - retime = true; + // removed, retiming is not supported with ABC9 continue; } if (args[argidx] == "-relut") { @@ -229,20 +217,16 @@ struct SynthIce40Pass : public ScriptPass noabc = true; continue; } - if (args[argidx] == "-abc2") { - abc2 = true; - continue; - } if (args[argidx] == "-vpr") { vpr = true; continue; } if (args[argidx] == "-abc9") { - // removed, ABC9 is on by default. + // removed, ABC9 is used if not -noabc continue; } if (args[argidx] == "-noabc9") { - abc9 = false; + // removed, ABC9 is used if not -noabc continue; } if (args[argidx] == "-dff") { @@ -272,11 +256,6 @@ struct SynthIce40Pass : public ScriptPass if (latches != "info" && latches != "warn" && latches != "error") log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); - if (abc9 && retime) - log_cmd_error("-retime option not currently compatible with -abc9!\n"); - if (abc9 && noabc) - log_cmd_error("-abc9 is incompatible with -noabc!\n"); - log_header(design, "Executing SYNTH_ICE40 pass.\n"); log_push(); @@ -384,8 +363,6 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/techmap.v -map +/ice40/arith_map.v"); } run("opt -fast"); - if (retime || help_mode) - run("abc -dff -D 1", "(only if -retime)"); run("ice40_opt"); } @@ -403,10 +380,6 @@ struct SynthIce40Pass : public ScriptPass if (check_label("map_luts")) { - if (abc2 || help_mode) { - run("abc", " (only if -abc2)"); - run("ice40_opt", "(only if -abc2)"); - } if (latches == "error" || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap -map +/ice40/latches_map.v"); @@ -416,22 +389,18 @@ struct SynthIce40Pass : public ScriptPass run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)"); } if (!noabc) { - if (abc9) { - run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v"); - std::string abc9_opts; - std::string k = "synth_ice40.abc9.W"; - if (active_design && active_design->scratchpad.count(k)) - abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); - else { - k = stringf("synth_ice40.abc9.%s.W", device_opt); - abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); - } - if (dff) - abc9_opts += " -dff"; - run("abc9 " + abc9_opts); + run("read_verilog " + define + " -icells -lib -specify +/ice40/abc9_model.v"); + std::string abc9_opts; + std::string k = "synth_ice40.abc9.W"; + if (active_design && active_design->scratchpad.count(k)) + abc9_opts += stringf(" -W %s", active_design->scratchpad_get_string(k)); + else { + k = stringf("synth_ice40.abc9.%s.W", device_opt); + abc9_opts += stringf(" -W %s", RTLIL::constpad.at(k)); } - else - run(stringf("abc -dress -lut 4 %s", dff ? "-dff" : ""), "(skip if -noabc)"); + if (dff) + abc9_opts += " -dff"; + run("abc9 " + abc9_opts); } run("ice40_wrapcarry -unwrap"); run("techmap -map +/ice40/ff_map.v"); diff --git a/tests/arch/ice40/bug1598.ys b/tests/arch/ice40/bug1598.ys index 6ea04b6fd..cd5a72d4c 100644 --- a/tests/arch/ice40/bug1598.ys +++ b/tests/arch/ice40/bug1598.ys @@ -13,4 +13,4 @@ module led_blink ( endmodule EOT proc -equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 -abc9 +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 diff --git a/tests/arch/ice40/bug1626.ys b/tests/arch/ice40/bug1626.ys index 92ce8eec9..21629491a 100644 --- a/tests/arch/ice40/bug1626.ys +++ b/tests/arch/ice40/bug1626.ys @@ -214,4 +214,4 @@ module \ahb_async_sram_halfwidth end EOT -synth_ice40 -abc2 -abc9 +synth_ice40