diff --git a/CHANGELOG b/CHANGELOG index bdf30260e..537c5682d 100644 --- a/CHANGELOG +++ b/CHANGELOG @@ -2,9 +2,25 @@ List of major changes and improvements between releases ======================================================= -Yosys 0.53 .. Yosys 0.54-dev +Yosys 0.54 .. Yosys 0.55-dev -------------------------- +Yosys 0.53 .. Yosys 0.54 +-------------------------- + * New commands and options + - Added "-genlib" option to "abc_new" and "abc9_exe" passes. + - Added "-verbose" and "-quiet" options to "libcache" pass. + - Added "-no-sort" option to "write_aiger" pass. + + * Various + - Added "muldiv_c" peepopt. + - Accept (and ignore) SystemVerilog unique/priority if. + - "read_verilog" copy inout ports in and out of functions/tasks. + - Enable single-bit vector wires in RTLIL. + + * Xilinx support + - Single-port URAM mapping to support memories 2048 x 144b + Yosys 0.52 .. Yosys 0.53 -------------------------- * New commands and options diff --git a/Makefile b/Makefile index 72cd20000..e872b5b17 100644 --- a/Makefile +++ b/Makefile @@ -176,7 +176,7 @@ ifeq ($(OS), Haiku) CXXFLAGS += -D_DEFAULT_SOURCE endif -YOSYS_VER := 0.53+98 +YOSYS_VER := 0.54+0 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1) YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2) YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3) @@ -199,7 +199,7 @@ endif OBJS = kernel/version_$(GIT_REV).o bumpversion: - sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline 53c22ab.. | wc -l`/;" Makefile + sed -i "/^YOSYS_VER := / s/+[0-9][0-9]*$$/+`git log --oneline db72ec3.. | wc -l`/;" Makefile ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1 ABC_USE_NAMESPACE=abc VERBOSE=$(Q) diff --git a/docs/source/conf.py b/docs/source/conf.py index bfcb28730..100605336 100644 --- a/docs/source/conf.py +++ b/docs/source/conf.py @@ -6,7 +6,7 @@ import os project = 'YosysHQ Yosys' author = 'YosysHQ GmbH' copyright ='2025 YosysHQ GmbH' -yosys_ver = "0.53" +yosys_ver = "0.54" # select HTML theme html_theme = 'furo-ys' diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc index 49bd63aae..cec897165 100644 --- a/frontends/verific/verific.cc +++ b/frontends/verific/verific.cc @@ -3595,6 +3595,14 @@ struct VerificPass : public Pass { // WARNING: instantiating unknown module 'XYZ' (VERI-1063) Message::SetMessageType("VERI-1063", VERIFIC_ERROR); + // Downgrade warnings about things that are normal + // VERIFIC-WARNING [VERI-1209] foo.sv:98: expression size 7 truncated to fit in target size 6 + Message::SetMessageType("VERI-1209", VERIFIC_INFO); + // VERIFIC-WARNING [VERI-1142] foo.sv:55: system task 'display' is ignored for synthesis + Message::SetMessageType("VERI-1142", VERIFIC_INFO); + // VERIFIC-WARNING [VERI-2418] foo.svh:503: parameter 'all_cfgs_gp' declared inside package 'bp_common_pkg' shall be treated as localparam + Message::SetMessageType("VERI-2418", VERIFIC_INFO); + // https://github.com/YosysHQ/yosys/issues/1055 RuntimeFlags::SetVar("veri_elaborate_top_level_modules_having_interface_ports", 1) ; #endif @@ -3659,6 +3667,9 @@ struct VerificPass : public Pass { } else if (Strings::compare(args[argidx].c_str(), "warnings")) { Message::SetAllMessageType(VERIFIC_WARNING, new_type); } else if (Strings::compare(args[argidx].c_str(), "infos")) { + Message::SetMessageType("VERI-1209", new_type); + Message::SetMessageType("VERI-1142", new_type); + Message::SetMessageType("VERI-2418", new_type); Message::SetAllMessageType(VERIFIC_INFO, new_type); } else if (Strings::compare(args[argidx].c_str(), "comments")) { Message::SetAllMessageType(VERIFIC_COMMENT, new_type); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 11c8a5af7..bf19c6aef 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -2425,7 +2425,14 @@ void RTLIL::Module::check() // assertion check below to make sure that there are no // cases where a cell has a blackbox attribute since // that is deprecated + #ifdef __GNUC__ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wdeprecated-declarations" + #endif log_assert(!it.second->get_blackbox_attribute()); + #ifdef __GNUC__ + #pragma GCC diagnostic pop + #endif } } diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc index 79a6b14ff..cb801589d 100644 --- a/passes/hierarchy/hierarchy.cc +++ b/passes/hierarchy/hierarchy.cc @@ -1452,7 +1452,7 @@ struct HierarchyPass : public Pass { bool resize_widths = !keep_portwidths && GetSize(w) != GetSize(conn.second); if (resize_widths && verific_mod && boxed_params) - log_warning("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n", + log_debug("Ignoring width mismatch on %s.%s.%s from verific, is port width parametrizable?\n", log_id(module), log_id(cell), log_id(conn.first) ); else if (resize_widths) { diff --git a/passes/proc/proc_arst.cc b/passes/proc/proc_arst.cc index f01682957..3cd3f6fe4 100644 --- a/passes/proc/proc_arst.cc +++ b/passes/proc/proc_arst.cc @@ -288,43 +288,40 @@ struct ProcArstPass : public Pass { extra_args(args, argidx, design); pool delete_initattr_wires; - for (auto mod : design->modules()) - if (design->selected(mod)) { - SigMap assign_map(mod); - for (auto &proc_it : mod->processes) { - if (!design->selected(mod, proc_it.second)) - continue; - proc_arst(mod, proc_it.second, assign_map); - if (global_arst.empty() || mod->wire(global_arst) == nullptr) - continue; - std::vector arst_actions; - for (auto sync : proc_it.second->syncs) - if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) - for (auto &act : sync->actions) { - RTLIL::SigSpec arst_sig, arst_val; - for (auto &chunk : act.first.chunks()) - if (chunk.wire && chunk.wire->attributes.count(ID::init)) { - RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init); - value.extend_u0(chunk.wire->width, false); - arst_sig.append(chunk); - arst_val.append(value.extract(chunk.offset, chunk.width)); - delete_initattr_wires.insert(chunk.wire); - } - if (arst_sig.size()) { - log("Added global reset to process %s: %s <- %s\n", - proc_it.first.c_str(), log_signal(arst_sig), log_signal(arst_val)); - arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); + for (auto mod : design->all_selected_modules()) { + SigMap assign_map(mod); + for (auto proc : mod->selected_processes()) { + proc_arst(mod, proc, assign_map); + if (global_arst.empty() || mod->wire(global_arst) == nullptr) + continue; + std::vector arst_actions; + for (auto sync : proc->syncs) + if (sync->type == RTLIL::SyncType::STp || sync->type == RTLIL::SyncType::STn) + for (auto &act : sync->actions) { + RTLIL::SigSpec arst_sig, arst_val; + for (auto &chunk : act.first.chunks()) + if (chunk.wire && chunk.wire->attributes.count(ID::init)) { + RTLIL::SigSpec value = chunk.wire->attributes.at(ID::init); + value.extend_u0(chunk.wire->width, false); + arst_sig.append(chunk); + arst_val.append(value.extract(chunk.offset, chunk.width)); + delete_initattr_wires.insert(chunk.wire); } + if (arst_sig.size()) { + log("Added global reset to process %s: %s <- %s\n", + proc->name.c_str(), log_signal(arst_sig), log_signal(arst_val)); + arst_actions.push_back(RTLIL::SigSig(arst_sig, arst_val)); } - if (!arst_actions.empty()) { - RTLIL::SyncRule *sync = new RTLIL::SyncRule; - sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; - sync->signal = mod->wire(global_arst); - sync->actions = arst_actions; - proc_it.second->syncs.push_back(sync); - } + } + if (!arst_actions.empty()) { + RTLIL::SyncRule *sync = new RTLIL::SyncRule; + sync->type = global_arst_neg ? RTLIL::SyncType::ST0 : RTLIL::SyncType::ST1; + sync->signal = mod->wire(global_arst); + sync->actions = arst_actions; + proc->syncs.push_back(sync); } } + } for (auto wire : delete_initattr_wires) wire->attributes.erase(ID::init); diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc index 95cb0e88c..b8bd74f50 100644 --- a/passes/proc/proc_clean.cc +++ b/passes/proc/proc_clean.cc @@ -208,19 +208,15 @@ struct ProcCleanPass : public Pass { } extra_args(args, argidx, design); - for (auto mod : design->modules()) { + for (auto mod : design->all_selected_modules()) { std::vector delme; - if (!design->selected(mod)) - continue; - for (auto &proc_it : mod->processes) { - if (!design->selected(mod, proc_it.second)) - continue; - proc_clean(mod, proc_it.second, total_count, quiet); - if (proc_it.second->syncs.size() == 0 && proc_it.second->root_case.switches.size() == 0 && - proc_it.second->root_case.actions.size() == 0) { + for (auto proc : mod->selected_processes()) { + proc_clean(mod, proc, total_count, quiet); + if (proc->syncs.size() == 0 && proc->root_case.switches.size() == 0 && + proc->root_case.actions.size() == 0) { if (!quiet) - log("Removing empty process `%s.%s'.\n", log_id(mod), proc_it.second->name.c_str()); - delme.push_back(proc_it.second); + log("Removing empty process `%s.%s'.\n", log_id(mod), proc->name.c_str()); + delme.push_back(proc); } } for (auto proc : delme) { diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index d094abf1b..7e3c56552 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -306,13 +306,11 @@ struct ProcDffPass : public Pass { extra_args(args, 1, design); - for (auto mod : design->modules()) - if (design->selected(mod)) { - ConstEval ce(mod); - for (auto &proc_it : mod->processes) - if (design->selected(mod, proc_it.second)) - proc_dff(mod, proc_it.second, ce); - } + for (auto mod : design->all_selected_modules()) { + ConstEval ce(mod); + for (auto proc : mod->selected_processes()) + proc_dff(mod, proc, ce); + } } } ProcDffPass; diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index e038a202c..f170dbf36 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -463,11 +463,10 @@ struct ProcDlatchPass : public Pass { extra_args(args, 1, design); - for (auto module : design->selected_modules()) { - proc_dlatch_db_t db(module); - for (auto &proc_it : module->processes) - if (design->selected(module, proc_it.second)) - proc_dlatch(db, proc_it.second); + for (auto mod : design->all_selected_modules()) { + proc_dlatch_db_t db(mod); + for (auto proc : mod->selected_processes()) + proc_dlatch(db, proc); db.fixup_muxes(); } } diff --git a/passes/proc/proc_init.cc b/passes/proc/proc_init.cc index 86e704852..817ced404 100644 --- a/passes/proc/proc_init.cc +++ b/passes/proc/proc_init.cc @@ -91,13 +91,11 @@ struct ProcInitPass : public Pass { extra_args(args, 1, design); - for (auto mod : design->modules()) - if (design->selected(mod)) { - SigMap sigmap(mod); - for (auto &proc_it : mod->processes) - if (design->selected(mod, proc_it.second)) - proc_init(mod, sigmap, proc_it.second); - } + for (auto mod : design->all_selected_modules()) { + SigMap sigmap(mod); + for (auto proc : mod->selected_processes()) + proc_init(mod, sigmap, proc); + } } } ProcInitPass; diff --git a/passes/proc/proc_memwr.cc b/passes/proc/proc_memwr.cc index 58bf9fdd3..88aea39bb 100644 --- a/passes/proc/proc_memwr.cc +++ b/passes/proc/proc_memwr.cc @@ -99,9 +99,9 @@ struct ProcMemWrPass : public Pass { extra_args(args, 1, design); - for (auto module : design->selected_modules()) { + for (auto mod : design->all_selected_modules()) { dict next_port_id; - for (auto cell : module->cells()) { + for (auto cell : mod->cells()) { if (cell->type.in(ID($memwr), ID($memwr_v2))) { bool is_compat = cell->type == ID($memwr); IdString memid = cell->parameters.at(ID::MEMID).decode_string(); @@ -110,9 +110,8 @@ struct ProcMemWrPass : public Pass { next_port_id[memid] = port_id + 1; } } - for (auto &proc_it : module->processes) - if (design->selected(module, proc_it.second)) - proc_memwr(module, proc_it.second, next_port_id); + for (auto proc : mod->selected_processes()) + proc_memwr(mod, proc, next_port_id); } } } ProcMemWrPass; diff --git a/passes/proc/proc_mux.cc b/passes/proc/proc_mux.cc index 2f539c960..61e7f4960 100644 --- a/passes/proc/proc_mux.cc +++ b/passes/proc/proc_mux.cc @@ -468,11 +468,9 @@ struct ProcMuxPass : public Pass { } extra_args(args, argidx, design); - for (auto mod : design->modules()) - if (design->selected(mod)) - for (auto &proc_it : mod->processes) - if (design->selected(mod, proc_it.second)) - proc_mux(mod, proc_it.second, ifxmode); + for (auto mod : design->all_selected_modules()) + for (auto proc : mod->selected_processes()) + proc_mux(mod, proc, ifxmode); } } ProcMuxPass; diff --git a/passes/proc/proc_prune.cc b/passes/proc/proc_prune.cc index 3433557ee..08903d93f 100644 --- a/passes/proc/proc_prune.cc +++ b/passes/proc/proc_prune.cc @@ -127,15 +127,10 @@ struct ProcPrunePass : public Pass { extra_args(args, 1, design); - for (auto mod : design->modules()) { - if (!design->selected(mod)) - continue; + for (auto mod : design->all_selected_modules()) { PruneWorker worker(mod); - for (auto &proc_it : mod->processes) { - if (!design->selected(mod, proc_it.second)) - continue; - worker.do_process(proc_it.second); - } + for (auto proc : mod->selected_processes()) + worker.do_process(proc); total_removed_count += worker.removed_count; total_promoted_count += worker.promoted_count; } diff --git a/passes/proc/proc_rmdead.cc b/passes/proc/proc_rmdead.cc index 2ec11415a..8f5eda085 100644 --- a/passes/proc/proc_rmdead.cc +++ b/passes/proc/proc_rmdead.cc @@ -147,21 +147,17 @@ struct ProcRmdeadPass : public Pass { extra_args(args, 1, design); int total_counter = 0; - for (auto mod : design->modules()) { - if (!design->selected(mod)) - continue; - for (auto &proc_it : mod->processes) { - if (!design->selected(mod, proc_it.second)) - continue; + for (auto mod : design->all_selected_modules()) { + for (auto proc : mod->selected_processes()) { int counter = 0, full_case_counter = 0; - for (auto switch_it : proc_it.second->root_case.switches) + for (auto switch_it : proc->root_case.switches) proc_rmdead(switch_it, counter, full_case_counter); if (counter > 0) log("Removed %d dead cases from process %s in module %s.\n", counter, - log_id(proc_it.first), log_id(mod)); + log_id(proc), log_id(mod)); if (full_case_counter > 0) log("Marked %d switch rules as full_case in process %s in module %s.\n", - full_case_counter, log_id(proc_it.first), log_id(mod)); + full_case_counter, log_id(proc), log_id(mod)); total_counter += counter; } } diff --git a/passes/proc/proc_rom.cc b/passes/proc/proc_rom.cc index 5f8e47ceb..d3b781e60 100644 --- a/passes/proc/proc_rom.cc +++ b/passes/proc/proc_rom.cc @@ -243,15 +243,10 @@ struct ProcRomPass : public Pass { extra_args(args, 1, design); - for (auto mod : design->modules()) { - if (!design->selected(mod)) - continue; + for (auto mod : design->all_selected_modules()) { RomWorker worker(mod); - for (auto &proc_it : mod->processes) { - if (!design->selected(mod, proc_it.second)) - continue; - worker.do_process(proc_it.second); - } + for (auto proc : mod->selected_processes()) + worker.do_process(proc); total_count += worker.count; } diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index 6cb569b5a..ee0a903c2 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -123,7 +123,7 @@ void check(RTLIL::Design *design, bool dff_mode) log_error("Module '%s' with (* abc9_flop *) is a blackbox.\n", log_id(derived_type)); if (derived_module->has_processes()) - Pass::call_on_module(design, derived_module, "proc"); + Pass::call_on_module(design, derived_module, "proc -noopt"); bool found = false; for (auto derived_cell : derived_module->cells()) { @@ -204,7 +204,7 @@ void prep_hier(RTLIL::Design *design, bool dff_mode) if (!unmap_design->module(derived_type)) { if (derived_module->has_processes()) - Pass::call_on_module(design, derived_module, "proc"); + Pass::call_on_module(design, derived_module, "proc -noopt"); if (derived_module->get_bool_attribute(ID::abc9_flop)) { for (auto derived_cell : derived_module->cells()) @@ -834,7 +834,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) holes_cell = holes_module->addCell(NEW_ID, cell->type); if (box_module->has_processes()) - Pass::call_on_module(design, box_module, "proc"); + Pass::call_on_module(design, box_module, "proc -noopt"); int box_inputs = 0; for (auto port_name : box_ports.at(cell->type)) {