diff --git a/Makefile b/Makefile
index 7c7122a8e..3af7de86b 100644
--- a/Makefile
+++ b/Makefile
@@ -18,8 +18,6 @@ ENABLE_GHDL := 0
 ENABLE_VERIFIC := 1
 ENABLE_VERIFIC_EDIF := 0
 ENABLE_VERIFIC_LIBERTY := 0
-# ENABLE_VERIFIC_YOSYSHQ := 0
-# ENABLE_VERIFIC_SILIMATE := 1
 DISABLE_VERIFIC_EXTENSIONS := 1
 DISABLE_VERIFIC_VHDL := 1
 ENABLE_COVER := 0
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 405cf3ff8..ca978857f 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -1195,9 +1195,6 @@ bool VerificImporter::import_netlist_instance_cells(Instance *inst, RTLIL::IdStr
 
 	if (inst->Type() == OPER_WIDE_CASE_SELECT_BOX)
 	{
-		// SILIMATE: WARN FOR THIS CASE BECAUSE YOSYS CAN DO WHATEVER IT WANTS
-		log_warning("Using OPER_WIDE_CASE_SELECT_BOX! This could result in long chains of logic...\n");
-
 		RTLIL::SigSpec sig_out_val = operatorInport(inst, "out_value");
 		RTLIL::SigSpec sig_select = operatorInport(inst, "select");
 		RTLIL::SigSpec sig_select_values = operatorInportCase(inst, "select_values");
@@ -2776,9 +2773,6 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			log("    Removing buffers for %s.\n", nl.first.c_str());
 			nl.second->RemoveBuffers();
 
-			log("    Optimizing priority selectors for %s.\n", nl.first.c_str());
-			nl.second->OptimizePrioSelectors();
-
 			log("    Balancing timing for %s.\n", nl.first.c_str());
 			unsigned result = nl.second->BalanceTiming(0);
 			log("    Balance timing result before: %d\n", result);
@@ -2788,10 +2782,9 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			log("    Running post-elaboration for %s.\n", nl.first.c_str());
 			nl.second->PostElaborationProcess();
 
-			log("    Optimizing priority selectors for %s.\n", nl.first.c_str());
-			nl.second->OptimizePrioSelectors();
-			log("    Merging selectors for %s.\n", nl.first.c_str());
-			nl.second->MergeSelectors();
+			log("    Running operator optimization for %s.\n", nl.first.c_str());
+			nl.second->OperatorOptimization(1, 1);
+			
 			log("    Performing resource sharing for %s.\n", nl.first.c_str());
 			nl.second->ResourceSharing();
 			log("    Performing final resource merging for %s.\n", nl.first.c_str());
@@ -2803,6 +2796,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 			nl.second->MergeRams();
 
 			log("    Balancing timing for %s.\n", nl.first.c_str());
+			result = nl.second->BalanceTiming(0);
 			log("    Balance timing result before: %d\n", result);
 			result = nl.second->BalanceTiming(1);
 			log("    Balance timing result after: %d\n", result);
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 20102b4b7..bf9569d99 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -195,8 +195,8 @@ void merge_operators(RTLIL::Module *module, RTLIL::Cell *mux, const std::vector<
 
 	for (auto &operand : muxed_operands) {
 		operand.sig.extend_u0(max_width, operand.is_signed);
-		// if (operand.sign != muxed_operands[0].sign)
-		// 	operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
+		if (operand.sign != muxed_operands[0].sign)
+			operand = ExtSigSpec(module->Neg(NEW_ID, operand.sig, operand.is_signed));
 	}
 
 	for (const auto& p : ports) {
diff --git a/verific b/verific
index 44a6fdd9f..5494ec600 160000
--- a/verific
+++ b/verific
@@ -1 +1 @@
-Subproject commit 44a6fdd9f1017959ffd53dafdca75904e5230224
+Subproject commit 5494ec6005899a889b603216e5f7a9ea58dee712