From 4029034ce3abe101ab59563d6b43bace3f7a370b Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Fri, 22 Aug 2025 08:35:10 -0700
Subject: [PATCH] Fix issue with $mux in abc

---
 passes/techmap/abc.cc | 1 +
 1 file changed, 1 insertion(+)

diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index b23ad6350..715c59a92 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -1370,6 +1370,7 @@ void AbcModuleState::extract(AbcSigMap &assign_map, RTLIL::Design *design, RTLIL
 					RTLIL::IdString remapped_name = remap_name(c->getPort(name).as_wire()->name);
 					cell->setPort(name, module->wire(remapped_name));
 				}
+				cell->fixup_parameters();
 				design->select(module, cell);
 				continue;
 			}