From 85d39653ac62fa4f1f809fb71b0df82a8bd01dfc Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:20:29 -0700
Subject: [PATCH 1/3] Remove unused model

---
 techlibs/ecp5/abc_model.v | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/techlibs/ecp5/abc_model.v b/techlibs/ecp5/abc_model.v
index 4eb923cb1..56a733b75 100644
--- a/techlibs/ecp5/abc_model.v
+++ b/techlibs/ecp5/abc_model.v
@@ -3,16 +3,3 @@
 (* abc_box_id=2 *)
 module \$__ABC_DPR16X4_COMB (input [3:0] A, S, output [3:0] Y);
 endmodule
-
-module \$__ABC_DPR16X4_SEQ (
-	input  [3:0] DI,
-	input  [3:0] WAD,
-	input        WRE,
-	input        WCK,
-	input  [3:0] RAD,
-	output [3:0] DO
-);
-	parameter WCKMUX = "WCK";
-	parameter WREMUX = "WRE";
-	parameter [63:0] INITVAL = 64'h0000000000000000;
-endmodule

From 455da572723e4f19ddc1d636b700a5fe1e975fbb Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:21:21 -0700
Subject: [PATCH 2/3] Fix spacing

---
 techlibs/ecp5/cells_sim.v | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/ecp5/cells_sim.v b/techlibs/ecp5/cells_sim.v
index e2bf3c854..01b10f392 100644
--- a/techlibs/ecp5/cells_sim.v
+++ b/techlibs/ecp5/cells_sim.v
@@ -116,7 +116,7 @@ module TRELLIS_DPR16X4 (
 	input        WCK,
 	input  [3:0] RAD,
 	/* (* abc_arrival=<TODO> *) */
-    output [3:0] DO
+	output [3:0] DO
 );
 	parameter WCKMUX = "WCK";
 	parameter WREMUX = "WRE";

From 3c1c376fb126017b8c3fdc3811830da11a15b635 Mon Sep 17 00:00:00 2001
From: Eddie Hung <eddie@fpgeh.com>
Date: Fri, 23 Aug 2019 13:22:37 -0700
Subject: [PATCH 3/3] Revert to upstream

---
 passes/techmap/abc9.cc | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 919c4ce53..0a5b07e6f 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1194,7 +1194,8 @@ struct Abc9Pass : public Pass {
 			std::map<RTLIL::Cell*, std::set<RTLIL::SigBit>> cell_to_bit, cell_to_bit_up, cell_to_bit_down;
 			std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
 
-			for (auto cell : all_cells) {
+			for (auto cell : all_cells)
+			{
 				clkdomain_t key;
 
 				for (auto &conn : cell->connections())
@@ -1228,7 +1229,6 @@ struct Abc9Pass : public Pass {
 				else
 					continue;
 
-
 				unassigned_cells.erase(cell);
 				expand_queue.insert(cell);
 				expand_queue_up.insert(cell);