From 3ed5da8c9e7830b659898c1bc53a41999acecc0d Mon Sep 17 00:00:00 2001 From: Akash Levy Date: Thu, 21 Aug 2025 12:59:03 -0700 Subject: [PATCH] Fix clock gate naming --- passes/techmap/clockgate.cc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/passes/techmap/clockgate.cc b/passes/techmap/clockgate.cc index 508e66d23..ba0cffb2a 100644 --- a/passes/techmap/clockgate.cc +++ b/passes/techmap/clockgate.cc @@ -371,17 +371,18 @@ struct ClockgatePass : public Pass { if (!matching_icg_desc) continue; - Cell* icg = module->addCell(NEW_ID, matching_icg_desc->name); + Cell* cell = *ce_ffs.begin(); + Cell* icg = module->addCell(NEW_ID2_SUFFIX("icg"), matching_icg_desc->name); icg->setPort(matching_icg_desc->ce_pin, clk.ce_bit); icg->setPort(matching_icg_desc->clk_in_pin, clk.clk_bit); - gclk.new_net = module->addWire(NEW_ID); + gclk.new_net = module->addWire(NEW_ID2_SUFFIX("gclk")); icg->setPort(matching_icg_desc->clk_out_pin, gclk.new_net); // Tie low DFT ports like scan chain enable for (auto port : matching_icg_desc->tie_lo_pins) icg->setPort(port, Const(0, 1)); // Fix CE polarity if needed if (!clk.pol_ce) { - SigBit ce_fixed_pol = module->NotGate(NEW_ID, clk.ce_bit); + SigBit ce_fixed_pol = module->NotGate(NEW_ID2_SUFFIX("ce_not"), clk.ce_bit); icg->setPort(matching_icg_desc->ce_pin, ce_fixed_pol); } }