diff --git a/techlibs/gowin/synth_gowin.cc b/techlibs/gowin/synth_gowin.cc
index f76f49deb..876a727c5 100644
--- a/techlibs/gowin/synth_gowin.cc
+++ b/techlibs/gowin/synth_gowin.cc
@@ -46,7 +46,7 @@ struct SynthGowinPass : public ScriptPass
 
 	const std::vector<DSPRule> gw5a_dsp_rules = {
 		{27, 36,  2, 19, "$__MUL27X36"},
-		{27, 18, 13, 13, "$__MUL27X18"},
+		{27, 18, 13,  2, "$__MUL27X18"},
 		{12, 12,  2,  2, "$__MUL12X12"},
 	};
 
diff --git a/tests/arch/gowin/mul_gw5a.ys b/tests/arch/gowin/mul_gw5a.ys
index a8b0c2e7d..7dd3ad4f6 100644
--- a/tests/arch/gowin/mul_gw5a.ys
+++ b/tests/arch/gowin/mul_gw5a.ys
@@ -37,6 +37,19 @@ cd top
 select -assert-count 1 t:MULTALU27X18
 
 
+# 4x13 -> 1 MULTALU27X18 (asymmetric: narrower operand below the 12x12 cell's
+# width, yet the product fits one 27x18 tile; relies on operand-order
+# normalization in mul2dsp plus B_MIN=2 on the 27x18 rule)
+design -reset
+read_verilog mul_gw5a.v
+chparam -set X_WIDTH 4 -set Y_WIDTH 13 -set A_WIDTH 17
+hierarchy -top top
+proc
+synth_gowin -family gw5a
+cd top
+select -assert-count 1 t:MULTALU27X18
+
+
 # 28x18 -> A overflows 27: 1 MULTALU27X18 + MULT12X12 partials
 design -reset
 read_verilog mul_gw5a.v