diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 3892c7581..e631c4655 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -21,6 +21,7 @@
 #include "kernel/sigtools.h"
 #include "kernel/log.h"
 #include "kernel/celltypes.h"
+#include "kernel/newcelltypes.h"
 #include "kernel/ffinit.h"
 #include <stdlib.h>
 #include <stdio.h>
@@ -101,7 +102,10 @@ struct keep_cache_t
 };
 
 keep_cache_t keep_cache;
-CellTypes ct_reg, ct_all;
+static constexpr auto ct_reg = TurboCellTypes::Categories::join(
+	TurboCellTypes::Compat::internals_mem_ff,
+	TurboCellTypes::categories.is_anyinit);
+CellTypes ct_all;
 int count_rm_cells, count_rm_wires;
 
 void rmunused_module_cells(Module *module, bool verbose)
@@ -307,10 +311,10 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 	if (!purge_mode)
 		for (auto &it : module->cells_) {
 			RTLIL::Cell *cell = it.second;
-			if (ct_reg.cell_known(cell->type)) {
+			if (ct_reg(cell->type)) {
 				bool clk2fflogic = cell->get_bool_attribute(ID(clk2fflogic));
 				for (auto &it2 : cell->connections())
-					if (clk2fflogic ? it2.first == ID::D : ct_reg.cell_output(cell->type, it2.first))
+					if (clk2fflogic ? it2.first == ID::D : ct_all.cell_output(cell->type, it2.first))
 						register_signals.add(it2.second);
 			}
 			for (auto &it2 : cell->connections())
@@ -516,14 +520,12 @@ bool rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool verbos
 bool rmunused_module_init(RTLIL::Module *module, bool verbose)
 {
 	bool did_something = false;
-	CellTypes fftypes;
-	fftypes.setup_internals_mem();
 
 	SigMap sigmap(module);
 	dict<SigBit, State> qbits;
 
 	for (auto cell : module->cells())
-		if (fftypes.cell_known(cell->type) && cell->hasPort(ID::Q))
+		if (TurboCellTypes::Compat::internals_mem_ff(cell->type) && cell->hasPort(ID::Q))
 		{
 			SigSpec sig = cell->getPort(ID::Q);
 
@@ -696,10 +698,6 @@ struct OptCleanPass : public Pass {
 
 		keep_cache.reset(design, purge_mode);
 
-		ct_reg.setup_internals_mem();
-		ct_reg.setup_internals_anyinit();
-		ct_reg.setup_stdcells_mem();
-
 		ct_all.setup(design);
 
 		count_rm_cells = 0;
@@ -719,7 +717,6 @@ struct OptCleanPass : public Pass {
 		design->check();
 
 		keep_cache.reset();
-		ct_reg.clear();
 		ct_all.clear();
 		log_pop();
 
@@ -760,10 +757,6 @@ struct CleanPass : public Pass {
 
 		keep_cache.reset(design);
 
-		ct_reg.setup_internals_mem();
-		ct_reg.setup_internals_anyinit();
-		ct_reg.setup_stdcells_mem();
-
 		ct_all.setup(design);
 
 		count_rm_cells = 0;
@@ -784,7 +777,6 @@ struct CleanPass : public Pass {
 		design->check();
 
 		keep_cache.reset();
-		ct_reg.clear();
 		ct_all.clear();
 
 		request_garbage_collection();