From 2d60ff8e444817708fd40cc01a56d5ae4d01a2cc Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Wed, 12 Nov 2025 10:46:48 -0800
Subject: [PATCH] One more fix for splitnetlist

---
 passes/silimate/splitnetlist.cc | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/passes/silimate/splitnetlist.cc b/passes/silimate/splitnetlist.cc
index 42d45797c..c300754fb 100644
--- a/passes/silimate/splitnetlist.cc
+++ b/passes/silimate/splitnetlist.cc
@@ -31,7 +31,8 @@ void recordTransFanin(RTLIL::SigSpec &sig, dict<RTLIL::SigSpec, std::set<Cell *>
 
 				if (cell->input(portName)) {
 					if (!actual.is_chunk()) {
-						for (auto it = actual.chunks().rbegin(); it != actual.chunks().rend(); ++it) {
+						auto chunks = actual.chunks();
+						for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
 							RTLIL::SigSpec sub_actual = *it;
 							recordTransFanin(sub_actual, sig2CellsInFanin, lhsSig2RhsSig, visitedCells, visitedSigSpec);
 						}
@@ -62,7 +63,8 @@ void sigCellDrivers(RTLIL::Design *design, dict<RTLIL::SigSpec, std::set<Cell *>
 			std::set<Cell *> *newSet;
 			if (cell->output(portName)) {
 				if (!actual.is_chunk()) {
-					for (auto it = actual.chunks().rbegin(); it != actual.chunks().rend(); ++it) {
+					auto chunks = actual.chunks();
+					for (auto it = chunks.rbegin(); it != chunks.rend(); ++it) {
 						RTLIL::SigSpec sub_actual = *it;
 						if (sig2CellsInFanin.count(sub_actual)) {
 							newSet = sig2CellsInFanin[sub_actual];