From 7f5b7aacb9f401d057c47f1f4a6d6e369dfe0163 Mon Sep 17 00:00:00 2001 From: nella Date: Wed, 12 Aug 2026 10:00:30 +0200 Subject: [PATCH] Count module output ports as consumers. --- techlibs/gatemate/gatemate_foldinv.cc | 4 ++++ tests/arch/gatemate/logic.ys | 4 ++-- tests/arch/gatemate/luttrees.ys | 4 ++-- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/techlibs/gatemate/gatemate_foldinv.cc b/techlibs/gatemate/gatemate_foldinv.cc index aa1764639..2843d62eb 100644 --- a/techlibs/gatemate/gatemate_foldinv.cc +++ b/techlibs/gatemate/gatemate_foldinv.cc @@ -125,6 +125,10 @@ struct FoldInvWorker { void fold_output_inverters() { pool used_bits; + for (auto wire : module->wires()) + if (wire->port_output) + for (auto bit : sigmap(SigSpec(wire))) + used_bits.insert(bit); // Find bits that are actually used for (auto cell : module->selected_cells()) { for (auto conn : cell->connections()) { diff --git a/tests/arch/gatemate/logic.ys b/tests/arch/gatemate/logic.ys index 646c24202..e6204cdca 100644 --- a/tests/arch/gatemate/logic.ys +++ b/tests/arch/gatemate/logic.ys @@ -27,7 +27,7 @@ design -load orig equiv_opt -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopad -luttree -abc_new # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-count 4 t:CC_LUT1 -select -assert-count 3 t:CC_LUT2 +select -assert-count 1 t:CC_LUT1 +select -assert-count 6 t:CC_LUT2 select -assert-count 2 t:CC_L2T4 select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 %% t:* %D diff --git a/tests/arch/gatemate/luttrees.ys b/tests/arch/gatemate/luttrees.ys index d87b66154..f3a61ee60 100644 --- a/tests/arch/gatemate/luttrees.ys +++ b/tests/arch/gatemate/luttrees.ys @@ -30,5 +30,5 @@ equiv_opt -async2sync -assert -map +/gatemate/cells_sim.v synth_gatemate -noiopa design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd luttrees # Constrain all select calls below inside the top module -select -assert-count 917 t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% -select -assert-none t:CC_LUT1 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D +select -assert-count 750 t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% +select -assert-none t:CC_LUT2 t:CC_L2T4 t:CC_L2T5 %% t:* %D