From 6de07db10082fa7c7ec7029611ac26273177e2ba Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Aug 2024 19:45:00 -0700 Subject: [PATCH 01/15] [core] switch to rf-abc --- .gitmodules | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.gitmodules b/.gitmodules index d88d4b1e5..d186a4b95 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,3 @@ [submodule "abc"] path = abc - url = https://github.com/YosysHQ/abc + url = https://github.com/RapidFlex/abc.git From 4ad9001cbfd7a0af18371123a8181c2e2bc5eea1 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 29 Aug 2024 19:48:04 -0700 Subject: [PATCH 02/15] [core] specify branch --- .gitmodules | 1 + 1 file changed, 1 insertion(+) diff --git a/.gitmodules b/.gitmodules index d186a4b95..1c7f18bc1 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,3 +1,4 @@ [submodule "abc"] path = abc url = https://github.com/RapidFlex/abc.git + branch = yosys-experimental From d7cf53d86afea418371edac2804cda007cd5e1a3 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 May 2026 17:33:24 -0700 Subject: [PATCH 03/15] [core] add rf techlibs --- techlibs/rapidflex/Makefile.inc | 55 + techlibs/rapidflex/alkaidC/arith_map.v | 154 + techlibs/rapidflex/alkaidC/ccb_inst_code.v | 29 + techlibs/rapidflex/alkaidC/cell_sim.v | 8 + techlibs/rapidflex/alkaidC/cell_sim_arith.v | 15 + techlibs/rapidflex/alkaidC/cell_sim_ccb.v | 101 + techlibs/rapidflex/alkaidC/cell_sim_ff.v | 586 + techlibs/rapidflex/alkaidC/cell_sim_pcnt.v | 9691 ++++++++++++ techlibs/rapidflex/alkaidC/dff_map.v | 177 + techlibs/rapidflex/alkaidC/synth.ys | 128 + techlibs/rapidflex/alkaidC/synth_no_adder.ys | 128 + techlibs/rapidflex/alkaidC/verilog_rewrite.ys | 41 + techlibs/rapidflex/alkaidL/arith_map.v | 154 + techlibs/rapidflex/alkaidL/bram.txt | 18 + techlibs/rapidflex/alkaidL/bram_map.v | 38 + techlibs/rapidflex/alkaidL/cell_sim.v | 7 + techlibs/rapidflex/alkaidL/cell_sim_arith.v | 15 + techlibs/rapidflex/alkaidL/cell_sim_bram.v | 876 ++ techlibs/rapidflex/alkaidL/cell_sim_dsp.v | 545 + techlibs/rapidflex/alkaidL/cell_sim_ff.v | 586 + techlibs/rapidflex/alkaidL/dff_map.v | 177 + techlibs/rapidflex/alkaidL/dsp_map.v | 17 + techlibs/rapidflex/alkaidL/synth.ys | 128 + techlibs/rapidflex/alkaidL/synth_no_adder.ys | 128 + techlibs/rapidflex/alkaidL/verilog_rewrite.ys | 41 + techlibs/rapidflex/alkaidT/arith_map.v | 154 + techlibs/rapidflex/alkaidT/bram.txt | 314 + techlibs/rapidflex/alkaidT/bram_map.v | 575 + techlibs/rapidflex/alkaidT/cell_sim.v | 8 + techlibs/rapidflex/alkaidT/cell_sim_arith.v | 15 + techlibs/rapidflex/alkaidT/cell_sim_bram.v | 876 ++ techlibs/rapidflex/alkaidT/cell_sim_dsp.v | 561 + techlibs/rapidflex/alkaidT/cell_sim_ff.v | 586 + techlibs/rapidflex/alkaidT/cell_sim_new_dsp.v | 385 + techlibs/rapidflex/alkaidT/dff_map.v | 177 + techlibs/rapidflex/alkaidT/dsp_map.v | 35 + techlibs/rapidflex/alkaidT/synth.ys | 123 + techlibs/rapidflex/alkaidT/verilog_rewrite.ys | 41 + techlibs/rapidflex/common/cells_sim.v | 53 + techlibs/rapidflex/src/clock_buffer_cmd.cc | 553 + techlibs/rapidflex/src/pugixml.cpp | 12313 ++++++++++++++++ techlibs/rapidflex/src/pugixml.hpp | 1544 ++ techlibs/rapidflex/src/rf_dsp_mad.cc | 192 + techlibs/rapidflex/src/rf_dsp_mad.pmg | 26 + techlibs/rapidflex/src/rf_new_dsp.cc | 441 + techlibs/rapidflex/src/rf_new_dsp.pmg | 478 + techlibs/rapidflex/src/synth_rf_alkaid.cc | 526 + techlibs/rapidflex/util/pcnt_cell_sim_gen.py | 142 + .../util/pcounter_ip_template_generator.py | 482 + 49 files changed, 34443 insertions(+) create mode 100644 techlibs/rapidflex/Makefile.inc create mode 100644 techlibs/rapidflex/alkaidC/arith_map.v create mode 100644 techlibs/rapidflex/alkaidC/ccb_inst_code.v create mode 100644 techlibs/rapidflex/alkaidC/cell_sim.v create mode 100644 techlibs/rapidflex/alkaidC/cell_sim_arith.v create mode 100644 techlibs/rapidflex/alkaidC/cell_sim_ccb.v create mode 100644 techlibs/rapidflex/alkaidC/cell_sim_ff.v create mode 100644 techlibs/rapidflex/alkaidC/cell_sim_pcnt.v create mode 100644 techlibs/rapidflex/alkaidC/dff_map.v create mode 100644 techlibs/rapidflex/alkaidC/synth.ys create mode 100644 techlibs/rapidflex/alkaidC/synth_no_adder.ys create mode 100644 techlibs/rapidflex/alkaidC/verilog_rewrite.ys create mode 100644 techlibs/rapidflex/alkaidL/arith_map.v create mode 100644 techlibs/rapidflex/alkaidL/bram.txt create mode 100644 techlibs/rapidflex/alkaidL/bram_map.v create mode 100644 techlibs/rapidflex/alkaidL/cell_sim.v create mode 100644 techlibs/rapidflex/alkaidL/cell_sim_arith.v create mode 100644 techlibs/rapidflex/alkaidL/cell_sim_bram.v create mode 100644 techlibs/rapidflex/alkaidL/cell_sim_dsp.v create mode 100644 techlibs/rapidflex/alkaidL/cell_sim_ff.v create mode 100644 techlibs/rapidflex/alkaidL/dff_map.v create mode 100644 techlibs/rapidflex/alkaidL/dsp_map.v create mode 100644 techlibs/rapidflex/alkaidL/synth.ys create mode 100644 techlibs/rapidflex/alkaidL/synth_no_adder.ys create mode 100644 techlibs/rapidflex/alkaidL/verilog_rewrite.ys create mode 100644 techlibs/rapidflex/alkaidT/arith_map.v create mode 100644 techlibs/rapidflex/alkaidT/bram.txt create mode 100644 techlibs/rapidflex/alkaidT/bram_map.v create mode 100644 techlibs/rapidflex/alkaidT/cell_sim.v create mode 100644 techlibs/rapidflex/alkaidT/cell_sim_arith.v create mode 100644 techlibs/rapidflex/alkaidT/cell_sim_bram.v create mode 100644 techlibs/rapidflex/alkaidT/cell_sim_dsp.v create mode 100644 techlibs/rapidflex/alkaidT/cell_sim_ff.v create mode 100644 techlibs/rapidflex/alkaidT/cell_sim_new_dsp.v create mode 100644 techlibs/rapidflex/alkaidT/dff_map.v create mode 100644 techlibs/rapidflex/alkaidT/dsp_map.v create mode 100644 techlibs/rapidflex/alkaidT/synth.ys create mode 100644 techlibs/rapidflex/alkaidT/verilog_rewrite.ys create mode 100644 techlibs/rapidflex/common/cells_sim.v create mode 100644 techlibs/rapidflex/src/clock_buffer_cmd.cc create mode 100644 techlibs/rapidflex/src/pugixml.cpp create mode 100644 techlibs/rapidflex/src/pugixml.hpp create mode 100644 techlibs/rapidflex/src/rf_dsp_mad.cc create mode 100644 techlibs/rapidflex/src/rf_dsp_mad.pmg create mode 100644 techlibs/rapidflex/src/rf_new_dsp.cc create mode 100644 techlibs/rapidflex/src/rf_new_dsp.pmg create mode 100644 techlibs/rapidflex/src/synth_rf_alkaid.cc create mode 100644 techlibs/rapidflex/util/pcnt_cell_sim_gen.py create mode 100644 techlibs/rapidflex/util/pcounter_ip_template_generator.py diff --git a/techlibs/rapidflex/Makefile.inc b/techlibs/rapidflex/Makefile.inc new file mode 100644 index 000000000..895a72bb0 --- /dev/null +++ b/techlibs/rapidflex/Makefile.inc @@ -0,0 +1,55 @@ +# cell lib generation +techlibs/rapidflex/alkaidC/cell_sim_pcnt.v: techlibs/rapidflex/util/pcnt_cell_sim_gen.py + $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ --file $@ + +CXXFLAGS += -Itechlibs/rapidflex/src/pugixml.hpp +OBJS += techlibs/rapidflex/src/pugixml.o +OBJS += techlibs/rapidflex/src/synth_rapidflex.o +OBJS += techlibs/rapidflex/src/clock_buffer_cmd.o + +# -------------------------------------- + +OBJS += techlibs/rapidflex/src/rf_new_dsp.o +OBJS += techlibs/rapidflex/src/rf_dsp_mad.o +GENFILES += techlibs/rapidflex/src/rf_new_dsp_pm.h techlibs/rapidflex/src/rf_dsp_mad_pm.h techlibs/rapidflex/alkaidC/cell_sim_pcnt.v +techlibs/rapidflex/src/rf_new_dsp.o: techlibs/rapidflex/src/rf_new_dsp_pm.h +techlibs/rapidflex/src/rf_dsp_mad.o: techlibs/rapidflex/src/rf_dsp_mad_pm.h +$(eval $(call add_extra_objs,techlibs/rapidflex/src/rf_new_dsp_pm.h,techlibs/rapidflex/src/rf_dsp_mad_pm.h)) + +# -------------------------------------- + +$(eval $(call add_share_file,share/rapidflex/common,techlibs/rapidflex/common/cells_sim.v)) + +# --------------AlkaidC cell lib ------------------------ +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/arith_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/ccb_inst_code.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_arith.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_ccb.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_ff.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_pcnt.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/dff_map.v)) +$(eval $(call add_gen_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_pcnt.v)) + +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/arith_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/bram_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/bram.txt)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/cell_sim_arith.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/cell_sim_bram.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/cell_sim_dsp.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/cell_sim_ff.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/cell_sim.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/dff_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidL,techlibs/rapidflex/alkaidL/dsp_map.v)) + +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/arith_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/bram_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/bram.txt)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/cell_sim_arith.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/cell_sim_bram.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/cell_sim_dsp.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/cell_sim_new_dsp.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/cell_sim_ff.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/cell_sim.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/dff_map.v)) +$(eval $(call add_share_file,share/rapidflex/alkaidT,techlibs/rapidflex/alkaidT/dsp_map.v)) diff --git a/techlibs/rapidflex/alkaidC/arith_map.v b/techlibs/rapidflex/alkaidC/arith_map.v new file mode 100644 index 000000000..d54433654 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/arith_map.v @@ -0,0 +1,154 @@ +// Arithmetic units: adder +// Adapt from: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/0ad1af26a29243a9e76379943d735e119dcd0cc6/ql-qlf-plugin/qlf_k6n10/cells_sim.v +// Many thanks to F4PGA for their contribution + +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + // The max. number of adders we can support in AlkaidS is (12x2-1)x4x16 = 1472 + // Fail when resource limit exceeds + // Also fail when a low utilization rate is detected + // Originally prefer to defer carry mapping when < 2-bit adder is detected + // Due to a bug found in scalable seq detector, the bound is increased to 4-bit adder + wire _TECHMAP_FAIL_ = Y_WIDTH > 1472 || Y_WIDTH < 4; + generate + if ((A_WIDTH == 0 || B_WIDTH == 0) && Y_WIDTH > 0) begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate + wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean"; + localparam Y_COL_WIDTH = 96 - 3; + localparam Y_MAX_WIDTH = 12 - 3; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH: 0] CARRY; + + assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1]; + genvar i; + generate if (Y_WIDTH < Y_COL_WIDTH) begin + wire CARRY_end_buf; + wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[Y_WIDTH] CARRY_end_buf"; + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + + _fpga_adder pretaill_adder ( + .cin (CARRY[Y_WIDTH-1] ), + .cout (CARRY_end_buf), + .a (AA[Y_WIDTH-1] ), + .b (BB[Y_WIDTH-1] ), + .sumout (Y[Y_WIDTH-1] ) + ); + + + _fpga_adder tail_adder ( + .cin (CARRY_end_buf), + .cout (), + .a (1'b0), + .b (1'b0), + .sumout (CARRY[Y_WIDTH]) + ); + + generate for (i = 1; i < Y_WIDTH-1 ; i = i+1) begin:gen3 + _fpga_adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end endgenerate + end else begin + generate for (i = 0; i < Y_WIDTH ; i = i+1) begin:gen4 + // Due to VPR limitations regarding IO connexion to carry chain, + // we generate the carry chain input signal using an intermediate adder + // since we can connect a & b from io pads, but not cin & cout + if (i == 0) begin + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + end else if (i % (Y_MAX_WIDTH + 1) == 0) begin + wire CARRY_end_buf; + wire CARRY_start_buf; + wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[i+1] CARRY_end_buf; insbuf CARRY_end_buf CARRY_start_buf"; + _fpga_adder tail_adder ( + .cin (CARRY[i]), + .cout (), + .a (1'b0), + .b (1'b0), + .sumout (CARRY_end_buf) + ); + + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY_start_buf), + .a (CARRY_end_buf), + .b (1'b1), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY_start_buf), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end else begin + _fpga_adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end + end endgenerate + end endgenerate + assign X = AA ^ BB; +endmodule diff --git a/techlibs/rapidflex/alkaidC/ccb_inst_code.v b/techlibs/rapidflex/alkaidC/ccb_inst_code.v new file mode 100644 index 000000000..99c34f8d8 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/ccb_inst_code.v @@ -0,0 +1,29 @@ +/////////////////////////////////////////////////////////////////////////////////////////////////////////////////// +// File name: define.v +// Descriptions: This file is the opcode for ccb tile instructions +// Author: Yihong +// Date: 2025/8/14 +// Revision: 0.0.1 +// Revision History: +// V0.0.1 - 2025/8/14 initial release +//////////////////////////////////////////////////////////////////////////////////////////////////////////////////// + +//Operations +`define ADD 4'b1000 +`define SUB 4'b1001 +`define PUSH 4'b1010 +`define PULL 4'b1011 +`define MOV 4'b1100 +`define MOV_T1 4'b1101 +`define MOV_T2 4'b1110 +`define INTR 4'b1111 +`define NA 10'h000 + +// SRC/DES +`define R0 3'b000 +`define R1 3'b001 +`define R2 3'b010 +`define R3 3'b011 +`define C0 3'b100 +`define C1 3'b101 +`define C2 3'b110 \ No newline at end of file diff --git a/techlibs/rapidflex/alkaidC/cell_sim.v b/techlibs/rapidflex/alkaidC/cell_sim.v new file mode 100644 index 000000000..8680b4c47 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/cell_sim.v @@ -0,0 +1,8 @@ +//------------------------------------------------- +// Include all the primitives +//------------------------------------------------- +`include "cell_sim_arith.v" +`include "cell_sim_ff.v" +`include "cell_sim_pcnt.v" +`include "ccb_inst_code.v" +`include "cell_sim_ccb.v" diff --git a/techlibs/rapidflex/alkaidC/cell_sim_arith.v b/techlibs/rapidflex/alkaidC/cell_sim_arith.v new file mode 100644 index 000000000..5a325e5b6 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/cell_sim_arith.v @@ -0,0 +1,15 @@ +//--------------------------------------- +// 1-bit adder +//--------------------------------------- +(* abc9_box, lib_whitebox *) +module _fpga_adder( + output sumout, + output cout, + input a, + input b, + input cin +); + assign sumout = a ^ b ^ cin; + assign cout = (a & b) | ((a | b) & cin); + +endmodule diff --git a/techlibs/rapidflex/alkaidC/cell_sim_ccb.v b/techlibs/rapidflex/alkaidC/cell_sim_ccb.v new file mode 100644 index 000000000..c8b454fdf --- /dev/null +++ b/techlibs/rapidflex/alkaidC/cell_sim_ccb.v @@ -0,0 +1,101 @@ +//------------------------------------------------- +// Counter Configuration Block (CCB) Primitives +//------------------------------------------------- +`default_nettype none + +module ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + // Event0 triggered instructions + parameter [0:9] EVENT0_INST0 = `NA, + parameter [0:9] EVENT0_INST1 = `NA, + parameter [0:9] EVENT0_INST2 = `NA, + parameter [0:9] EVENT0_INST3 = `NA, + parameter [0:9] EVENT0_INST4 = `NA, + parameter [0:9] EVENT0_INST5 = `NA, + parameter [0:9] EVENT0_INST6 = `NA, + parameter [0:9] EVENT0_INST7 = `NA, + // Event1 triggered instructions + parameter [0:9] EVENT1_INST0 = `NA, + parameter [0:9] EVENT1_INST1 = `NA, + parameter [0:9] EVENT1_INST2 = `NA, + parameter [0:9] EVENT1_INST3 = `NA, + parameter [0:9] EVENT1_INST4 = `NA, + parameter [0:9] EVENT1_INST5 = `NA, + parameter [0:9] EVENT1_INST6 = `NA, + parameter [0:9] EVENT1_INST7 = `NA, + // Event2 triggered instructions + parameter [0:9] EVENT2_INST0 = `NA, + parameter [0:9] EVENT2_INST1 = `NA, + parameter [0:9] EVENT2_INST2 = `NA, + parameter [0:9] EVENT2_INST3 = `NA, + parameter [0:9] EVENT2_INST4 = `NA, + parameter [0:9] EVENT2_INST5 = `NA, + parameter [0:9] EVENT2_INST6 = `NA, + parameter [0:9] EVENT2_INST7 = `NA, + // Event3 triggered instructions + parameter [0:9] EVENT3_INST0 = `NA, + parameter [0:9] EVENT3_INST1 = `NA, + parameter [0:9] EVENT3_INST2 = `NA, + parameter [0:9] EVENT3_INST3 = `NA, + parameter [0:9] EVENT3_INST4 = `NA, + parameter [0:9] EVENT3_INST5 = `NA, + parameter [0:9] EVENT3_INST6 = `NA, + parameter [0:9] EVENT3_INST7 = `NA, + // Initial register values, R0-R3 + parameter [0:31] R0 = {32{1'b0}}, + parameter [0:31] R1 = {32{1'b0}}, + parameter [0:31] R2 = {32{1'b0}}, + parameter [0:31] R3 = {32{1'b0}}, + // FIFO initial values + parameter [0:31] FIFO_INIT0 = {32{1'b0}}, + parameter [0:31] FIFO_INIT1 = {32{1'b0}}, + parameter [0:31] FIFO_INIT2 = {32{1'b0}}, + parameter [0:31] FIFO_INIT3 = {32{1'b0}}, + // PCNT initial values + parameter [0:31] LOAD_VAL_PCNT0 = {32{1'b0}}, + parameter [0:31] LOAD_VAL_PCNT1 = {32{1'b0}}, + parameter [0:31] LOAD_VAL_PCNT2 = {32{1'b0}}, + parameter [0:31] MATCH0_REF_PCNT0 = {32{1'b0}}, + parameter [0:31] MATCH0_REF_PCNT1 = {32{1'b0}}, + parameter [0:31] MATCH0_REF_PCNT2 = {32{1'b0}}, + parameter [0:31] MATCH1_REF_PCNT0 = {32{1'b0}}, + parameter [0:31] MATCH1_REF_PCNT1 = {32{1'b0}}, + parameter [0:31] MATCH1_REF_PCNT2 = {32{1'b0}} +)( + input ccb_clk_i, + input ccb_rst_ni, + input [0:3] ccb_event_i, + input [0:5] pcnt_event_i, + output [0:31] match0_ref0_o, + output [0:31] match1_ref0_o, + output [0:31] load_val0_o, + output [0:31] match0_ref1_o, + output [0:31] match1_ref1_o, + output [0:31] load_val1_o, + output [0:31] match0_ref2_o, + output [0:31] match1_ref2_o, + output [0:31] load_val2_o + +); + + +// Dummy +assign match0_ref0_o = 0; +assign match1_ref0_o = 0; +assign load_val0_o = 0; + +assign match0_ref1_o = 0; +assign match1_ref1_o = 0; +assign load_val1_o = 0; + +assign match0_ref2_o = 0; +assign match1_ref2_o = 0; +assign load_val2_o = 0; + + +endmodule + +`default_nettype wire diff --git a/techlibs/rapidflex/alkaidC/cell_sim_ff.v b/techlibs/rapidflex/alkaidC/cell_sim_ff.v new file mode 100644 index 000000000..726987e16 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/cell_sim_ff.v @@ -0,0 +1,586 @@ +//----------------------------- +// Rising-edge D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffn( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffns( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffns( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Two-bit D-type flip-flop with active-high asynchronous reset +// 1st stage is positive-edge triggered +// 2nd stage is negative-edge triggered +//----------------------------- +// Do not allow ABC or other optimization to touch the ff! +//(* abc9_flop, lib_whitebox *) +module dffnr_dffr( + output Q, + input D, + input R, + input C +); + +wire Q0; + + dffnr FF_0 (.D(D), .C(C), .R(R), .Q(Q0)); + dffr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q)); + +endmodule + +//----------------------------- +// Two-bit D-type flip-flop with active-high asynchronous reset +// 1st stage is positive-edge triggered +// 2nd stage is negative-edge triggered +//----------------------------- +// Do not allow ABC or other optimization to touch the ff! +//(* abc9_flop, lib_whitebox *) +module dffr_dffnr( + output Q, + input D, + input R, + input C +); + +wire Q0; + + dffr FF_0 (.D(D), .C(C), .R(R), .Q(Q0)); + dffnr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q)); + +endmodule + diff --git a/techlibs/rapidflex/alkaidC/cell_sim_pcnt.v b/techlibs/rapidflex/alkaidC/cell_sim_pcnt.v new file mode 100644 index 000000000..1525c24c7 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/cell_sim_pcnt.v @@ -0,0 +1,9691 @@ +//------------------------------------------------- +// IMPORTANT: This file is auto generated!!! DO NOT MODIFY BY HAND!!! +//------------------------------------------------- +// Pcounter Primitives +// Naming convention: +// pcounter_clk_rst_ +// size: [N | ] ranges from 0 to 31, representing the number of bits. N is a parameterized design, which is supposed not be exposed to users +// trigger_type: [p|n] denotes [rising edge (posedge) | falling edge (negedge) ] +// reset_type: [a|s] denotes [ asynchronous | synchronous ] +// reset_polarity: [p|n] denotes [ active-high | active-low ] +// event_function : [ load | add | sub | sr | sl ] denotes [ load | add | substract | shift right | shift left ] on the data_i values +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstn_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstn_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstn_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstn_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstn_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstn_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstn_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstn_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstn_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_srstn_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstn_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstn_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstp_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstp_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstp_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstp_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstp_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstp_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstp_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstp_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_srstp_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with synchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_srstp_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_srstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_srstp_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_srstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_srstp_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstn_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstn_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstn_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstn_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstn_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstn_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstn_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstn_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstn_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_arstn_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstn_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstn_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstp_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstp_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstp_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstp_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstp_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstp_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstp_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstp_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkp_arstp_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by rising edge clock + +// with asynchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkp_arstp_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(posedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkp_arstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkp_arstp_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkp_arstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkp_arstp_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstn_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstn_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstn_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstn_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstn_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstn_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstn_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstn_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstn_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_srstn_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstn_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstn_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstp_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstp_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstp_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstp_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstp_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstp_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstp_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstp_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_srstp_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with synchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_srstp_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_srstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_srstp_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_srstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_srstp_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstn_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstn_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstn_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstn_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstn_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstn_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstn_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstn_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstn_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-low reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_arstn_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or negedge rst_i) + begin + if (~rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstn_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstn_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstn_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_load #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_load #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_load #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_load #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of load values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_load_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstp_load_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_load_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstp_load_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_add #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_add #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_add #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_add #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of add values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_add_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o + ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstp_add_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_add_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstp_add_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_sub #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_sub #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_sub #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_sub #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of subtract values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_sub_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o - ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstp_sub_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_sub_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstp_sub_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_sr #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_sr #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_sr #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_sr #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of shift-right values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_sr_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o >> ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstp_sr_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_sr_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstp_sr_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_sl #( + parameter integer DATA_WIDTH = 32, + parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, + parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << LOAD_VAL; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; + assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 31] LOAD_VAL = {32{1'b0}}, + parameter [0 : 31] MATCH0_REF = {32{1'b0}}, + parameter [0 : 31] MATCH1_REF = {32{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_sl #( + .DATA_WIDTH(32), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_sl #( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0, + parameter [0 : 15] LOAD_VAL = {16{1'b0}}, + parameter [0 : 15] MATCH0_REF = {16{1'b0}}, + parameter [0 : 15] MATCH1_REF = {16{1'b0}} +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + output match0_o, + output match1_o, + output zero_o +); + pcounterN_clkn_arstp_sl #( + .DATA_WIDTH(16), + .LOAD_VAL(LOAD_VAL), + .MATCH0_REF(MATCH0_REF), + .MATCH1_REF(MATCH1_REF) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o) + ); +endmodule +`default_nettype wire +//------------------------------------------------- + +// Template of Programmable counter to be counting up or down as well as paused + +// triggered by falling edge clock + +// with asynchronous active-high reset + +// Capable of shift-left values from inputs + +`default_nettype none + +module pcounterN_clkn_arstp_sl_ccb #( + parameter integer DATA_WIDTH = 32 +)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, + input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, + input [0 : DATA_WIDTH - 1] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : DATA_WIDTH - 1] q_o +); + reg [0 : DATA_WIDTH - 1] q_o; + always@(negedge clk_i or posedge rst_i) + begin + if (rst_i) //Set Counter to Zero + q_o <= 0; + else if(event_i) + q_o <= q_o << ccb_load_val_i; + else if (~enable_i) + q_o <= q_o; // pause + else if(up_down_i) //count down + q_o <= q_o - 1; + else //count up + q_o <= q_o + 1; + end + assign zero_o = (q_o == 0) ? 1 : 0; + assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; + assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; +endmodule +`default_nettype wire +`default_nettype none + +module pcounter32_clkn_arstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 31] ccb_match0_ref_i, + input [0 : 31] ccb_match1_ref_i, + input [0 : 31] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 31] q_o +); + pcounterN_clkn_arstp_sl_ccb #( + .DATA_WIDTH(32) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire +`default_nettype none + +module pcounter16_clkn_arstp_sl_ccb # ( + // Location constraints + parameter FPGA_LOC_X = 0, + parameter FPGA_LOC_Y = 0, + parameter FPGA_LOC_Z = 0)( + input clk_i, + input rst_i, + input up_down_i, + input event_i, + input enable_i, + input [0 : 15] ccb_match0_ref_i, + input [0 : 15] ccb_match1_ref_i, + input [0 : 15] ccb_load_val_i, + output match0_o, + output match1_o, + output zero_o, + output [0 : 15] q_o +); + pcounterN_clkn_arstp_sl_ccb #( + .DATA_WIDTH(16) + ) core ( + .clk_i(clk_i), + .rst_i(rst_i), + .up_down_i(up_down_i), + .event_i(event_i), + .enable_i(enable_i), + .ccb_load_val_i(ccb_load_val_i), + .ccb_match0_ref_i(ccb_match0_ref_i), + .ccb_match1_ref_i(ccb_match1_ref_i), + .match0_o(match0_o), + .match1_o(match1_o), + .zero_o(zero_o), + .q_o(q_o) + ); +endmodule +`default_nettype wire diff --git a/techlibs/rapidflex/alkaidC/dff_map.v b/techlibs/rapidflex/alkaidC/dff_map.v new file mode 100644 index 000000000..f6d01a4ed --- /dev/null +++ b/techlibs/rapidflex/alkaidC/dff_map.v @@ -0,0 +1,177 @@ +// Rising edge DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Rising edge DFF with async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Rising edge DFF with async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Rising edge DFF with async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Rising edge DFF with async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Rising edge DFF with sync active-high reset +module \$_SDFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Rising edge DFF with sync active-high set +module \$_SDFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Rising edge DFF with sync active-low reset +module \$_SDFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Rising edge DFF with sync active-low set +module \$_SDFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Falling edge DFF +module \$_DFF_N_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Falling edge DFF with async active-high reset +module \$_DFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Falling edge DFF with async active-high set +module \$_DFF_NP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Falling edge DFF with async active-low reset +module \$_DFF_NN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Falling edge DFF with async active-low set +module \$_DFF_NN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Falling edge DFF with sync active-high reset +module \$_SDFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Falling edge DFF with sync active-high set +module \$_SDFF_NP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Falling edge DFF with sync active-low reset +module \$_SDFF_NN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Falling edge DFF with sync active-low set +module \$_SDFF_NN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/techlibs/rapidflex/alkaidC/synth.ys b/techlibs/rapidflex/alkaidC/synth.ys new file mode 100644 index 000000000..4844ccf0b --- /dev/null +++ b/techlibs/rapidflex/alkaidC/synth.ys @@ -0,0 +1,128 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt -nodffe + +opt_expr +opt_clean +check +opt -nodffe +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +#memory_dff +#wreduce t:$mul +#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +#select a:mul2dsp +#setattr -unset mul2dsp +#opt_expr -fine +#wreduce +#select -clear +#chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +alumacc +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#opt -fast -nodffe +#opt_expr +#opt_merge +#opt_clean +#opt -nodffe +#share +#opt -nodffe +#fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +#opt -fast -nodffe +opt +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +#techmap -map ${YOSYS_BRAM_MAP_VERILOG} +#opt -fast -mux_undef -undriven -fine -nodffe +#memory_map +#opt -undriven -fine -nodffe + +######################## +# Map Adders +techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +opt -fast -nodffe +opt_expr +opt_merge +opt_clean +opt -nodffe + +######################### +# Map flip-flops +######################### +memory +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_dff -nodffe +opt_clean +opt -nodffe + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} +# Map dff again since ABC may generate some new FFs +techmap -map ${YOSYS_DFF_MAP_VERILOG} +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} +write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidC/synth_no_adder.ys b/techlibs/rapidflex/alkaidC/synth_no_adder.ys new file mode 100644 index 000000000..bef3c7dc5 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/synth_no_adder.ys @@ -0,0 +1,128 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt -nodffe + +opt_expr +opt_clean +check +opt -nodffe +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +#memory_dff +#wreduce t:$mul +#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +#select a:mul2dsp +#setattr -unset mul2dsp +#opt_expr -fine +#wreduce +#select -clear +#chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +alumacc +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#opt -fast -nodffe +#opt_expr +#opt_merge +#opt_clean +#opt -nodffe +#share +#opt -nodffe +#fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +#opt -fast -nodffe +opt +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +#techmap -map ${YOSYS_BRAM_MAP_VERILOG} +#opt -fast -mux_undef -undriven -fine -nodffe +#memory_map +#opt -undriven -fine -nodffe + +######################## +# Map Adders +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#opt -fast -nodffe +#opt_expr +#opt_merge +#opt_clean +#opt -nodffe + +######################### +# Map flip-flops +######################### +memory +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_dff -nodffe +opt_clean +opt -nodffe + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} +# Map dff again since ABC may generate some new FFs +techmap -map ${YOSYS_DFF_MAP_VERILOG} +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} +write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidC/verilog_rewrite.ys b/techlibs/rapidflex/alkaidC/verilog_rewrite.ys new file mode 100644 index 000000000..217e8d558 --- /dev/null +++ b/techlibs/rapidflex/alkaidC/verilog_rewrite.ys @@ -0,0 +1,41 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff +clean + +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_verilog ${OUTPUT_VERILOG} diff --git a/techlibs/rapidflex/alkaidL/arith_map.v b/techlibs/rapidflex/alkaidL/arith_map.v new file mode 100644 index 000000000..d54433654 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/arith_map.v @@ -0,0 +1,154 @@ +// Arithmetic units: adder +// Adapt from: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/0ad1af26a29243a9e76379943d735e119dcd0cc6/ql-qlf-plugin/qlf_k6n10/cells_sim.v +// Many thanks to F4PGA for their contribution + +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + // The max. number of adders we can support in AlkaidS is (12x2-1)x4x16 = 1472 + // Fail when resource limit exceeds + // Also fail when a low utilization rate is detected + // Originally prefer to defer carry mapping when < 2-bit adder is detected + // Due to a bug found in scalable seq detector, the bound is increased to 4-bit adder + wire _TECHMAP_FAIL_ = Y_WIDTH > 1472 || Y_WIDTH < 4; + generate + if ((A_WIDTH == 0 || B_WIDTH == 0) && Y_WIDTH > 0) begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate + wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean"; + localparam Y_COL_WIDTH = 96 - 3; + localparam Y_MAX_WIDTH = 12 - 3; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH: 0] CARRY; + + assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1]; + genvar i; + generate if (Y_WIDTH < Y_COL_WIDTH) begin + wire CARRY_end_buf; + wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[Y_WIDTH] CARRY_end_buf"; + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + + _fpga_adder pretaill_adder ( + .cin (CARRY[Y_WIDTH-1] ), + .cout (CARRY_end_buf), + .a (AA[Y_WIDTH-1] ), + .b (BB[Y_WIDTH-1] ), + .sumout (Y[Y_WIDTH-1] ) + ); + + + _fpga_adder tail_adder ( + .cin (CARRY_end_buf), + .cout (), + .a (1'b0), + .b (1'b0), + .sumout (CARRY[Y_WIDTH]) + ); + + generate for (i = 1; i < Y_WIDTH-1 ; i = i+1) begin:gen3 + _fpga_adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end endgenerate + end else begin + generate for (i = 0; i < Y_WIDTH ; i = i+1) begin:gen4 + // Due to VPR limitations regarding IO connexion to carry chain, + // we generate the carry chain input signal using an intermediate adder + // since we can connect a & b from io pads, but not cin & cout + if (i == 0) begin + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + end else if (i % (Y_MAX_WIDTH + 1) == 0) begin + wire CARRY_end_buf; + wire CARRY_start_buf; + wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[i+1] CARRY_end_buf; insbuf CARRY_end_buf CARRY_start_buf"; + _fpga_adder tail_adder ( + .cin (CARRY[i]), + .cout (), + .a (1'b0), + .b (1'b0), + .sumout (CARRY_end_buf) + ); + + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY_start_buf), + .a (CARRY_end_buf), + .b (1'b1), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY_start_buf), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end else begin + _fpga_adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end + end endgenerate + end endgenerate + assign X = AA ^ BB; +endmodule diff --git a/techlibs/rapidflex/alkaidL/bram.txt b/techlibs/rapidflex/alkaidL/bram.txt new file mode 100644 index 000000000..7d0da595a --- /dev/null +++ b/techlibs/rapidflex/alkaidL/bram.txt @@ -0,0 +1,18 @@ +bram $__FLEX_TDPRAM_256x36 # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 8 # Number of address bits + dbits 36 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_256x36 + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary +endmatch + diff --git a/techlibs/rapidflex/alkaidL/bram_map.v b/techlibs/rapidflex/alkaidL/bram_map.v new file mode 100644 index 000000000..f559f57b3 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/bram_map.v @@ -0,0 +1,38 @@ +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_256x36 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:7] A1ADDR; + input A1EN; + output [0:35] A1DATA; + input [0:7] B1ADDR; + input B1EN; + input [0:35] B1DATA; + + generate + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + ) _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule diff --git a/techlibs/rapidflex/alkaidL/cell_sim.v b/techlibs/rapidflex/alkaidL/cell_sim.v new file mode 100644 index 000000000..b97638d7a --- /dev/null +++ b/techlibs/rapidflex/alkaidL/cell_sim.v @@ -0,0 +1,7 @@ +//------------------------------------------------- +// Include all the primitives +//------------------------------------------------- +`include "cell_sim_arith.v" +`include "cell_sim_dsp.v" +`include "cell_sim_bram.v" +`include "cell_sim_ff.v" diff --git a/techlibs/rapidflex/alkaidL/cell_sim_arith.v b/techlibs/rapidflex/alkaidL/cell_sim_arith.v new file mode 100644 index 000000000..5a325e5b6 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/cell_sim_arith.v @@ -0,0 +1,15 @@ +//--------------------------------------- +// 1-bit adder +//--------------------------------------- +(* abc9_box, lib_whitebox *) +module _fpga_adder( + output sumout, + output cout, + input a, + input b, + input cin +); + assign sumout = a ^ b ^ cin; + assign cout = (a & b) | ((a | b) & cin); + +endmodule diff --git a/techlibs/rapidflex/alkaidL/cell_sim_bram.v b/techlibs/rapidflex/alkaidL/cell_sim_bram.v new file mode 100644 index 000000000..57a320821 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/cell_sim_bram.v @@ -0,0 +1,876 @@ +//------------------------------------------------- +// Block RAM Primitives +//------------------------------------------------- + +//------------------------------------------------- +// True Dual-port RAM Core logic +// This module is written in a scalable way +// By default it is configured as 256x36 = 9k-bits +// +// IMPORTANT: Please do not use this module as a hard ip!!! +module tdpram_core (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); +// Parameters +parameter ADDR_WIDTH = 8; +parameter DEPTH = 2**ADDR_WIDTH; +parameter BYTE_WIDTH = 9; +parameter NUM_BYTES = 4; +parameter [0:0] IS_WCLK_N = 1'b0; // Indicate if the write clock is triggered at negative edge: 1 = Yes; 0 = No +parameter [0:0] IS_RCLK_N = 1'b0; // Indicate if the read clock is triggered at negative edge: 1 = Yes; 0 = No + +input ren_ni; +input wen_ni; +input [0:ADDR_WIDTH-1] raddr_i; +input [0:ADDR_WIDTH-1] waddr_i; +input [0:BYTE_WIDTH*NUM_BYTES-1] bwen_ni; +input [0:BYTE_WIDTH*NUM_BYTES-1] data_i; +input wclk_i; +input rclk_i; +output [0:BYTE_WIDTH*NUM_BYTES-1] q_o; + +reg [0:NUM_BYTES*BYTE_WIDTH-1] ram[0:DEPTH-1]; +reg [0:NUM_BYTES*BYTE_WIDTH-1] q_reg; + +integer i; + +assign q_o = q_reg; + +// Initial values are all random, to mimic the actual behavoir of a RAM +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + ram[i] = $random; + end + q_reg <= $random; +end + +case(|IS_WCLK_N) + 1'b0: + always @(posedge wclk_i) begin + if (~wen_ni) begin + for (i = 0; i < NUM_BYTES * BYTE_WIDTH; i = i + 1) begin + if (~bwen_ni[i]) begin + ram[waddr_i][i] <= data_i[i]; + end + end + end + end + 1'b1: + always @(negedge wclk_i) begin + if (~wen_ni) begin + for (i = 0; i < NUM_BYTES * BYTE_WIDTH; i = i + 1) begin + if (~bwen_ni[i]) begin + ram[waddr_i][i] <= data_i[i]; + end + end + end + end +endcase + +case(|IS_RCLK_N) + 1'b0: + always @(posedge rclk_i) begin + if (~ren_ni) begin + q_reg <= ram[raddr_i]; + end + end + 1'b1: + always @(negedge rclk_i) begin + if (~ren_ni) begin + q_reg <= ram[raddr_i]; + end + end +endcase + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram256x36 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram256x36_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram256x36_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram256x36_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram512x18 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram512x18_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram512x18_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram512x18_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram1024x9 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram1024x9_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram1024x9_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram1024x9_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram2048x4 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram2048x4_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram2048x4_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram2048x4_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule diff --git a/techlibs/rapidflex/alkaidL/cell_sim_dsp.v b/techlibs/rapidflex/alkaidL/cell_sim_dsp.v new file mode 100644 index 000000000..8bbac6d14 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/cell_sim_dsp.v @@ -0,0 +1,545 @@ +//------------------------------------------------- +// DSP Primitives +//------------------------------------------------- + +//------------------------------------------------- +// Multiply accumulators +module quad_mac12x10 (A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + + assign Y = A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3; + +endmodule + +//------------------------------------------------- +// Multiply accumulators with input registering +module quad_mac12x10_regi (CLK, RSTB, A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; +reg [0:A_WIDTH-1] A2_reg; +reg [0:B_WIDTH-1] B2_reg; +reg [0:A_WIDTH-1] A3_reg; +reg [0:B_WIDTH-1] B3_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + A2_reg <= 0; + B2_reg <= 0; + A3_reg <= 0; + B3_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + A2_reg <= A2; + B2_reg <= B2; + A3_reg <= A3; + B3_reg <= B3; + end +end + +assign Y = A0_reg * B0_reg + A1_reg * B1_reg + A2_reg * B2_reg + A3_reg * B3_reg; + +endmodule + +//------------------------------------------------- +// Multiply accumulators with output registering +module quad_mac12x10_rego (CLK, RSTB, A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3; + end +end + +assign Y = Y_reg; + +endmodule + +//------------------------------------------------- +// Multiply accumulators with input and output registering +module quad_mac12x10_regio (CLK, RSTB, A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; +reg [0:A_WIDTH-1] A2_reg; +reg [0:B_WIDTH-1] B2_reg; +reg [0:A_WIDTH-1] A3_reg; +reg [0:B_WIDTH-1] B3_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + A2_reg <= 0; + B2_reg <= 0; + A3_reg <= 0; + B3_reg <= 0; + Y_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + A2_reg <= A2; + B2_reg <= B2; + A3_reg <= A3; + B3_reg <= B3; + Y_reg <= A0_reg * B0_reg + A1_reg * B1_reg + A2_reg * B2_reg + A3_reg * B3_reg; + end +end + +assign Y = Y_reg; + +endmodule + + +module quad_mac12x10_dual_output (A0, B0, A1, B1, A2, B2, A3, B3, Y0, Y1); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y0; +output [0:Y_WIDTH-1] Y1; + + assign Y0 = A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3; + assign Y1 = A2 * B2 + A3 * B3; + +endmodule + +module mac12x10 (A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + + assign Y = A0 * B0 + A1 * B1; + +endmodule + +module mac12x10_regi (CLK, RSTB, A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + end +end + + assign Y = A0_reg * B0_reg + A1_reg * B1_reg; + +endmodule + +module mac12x10_rego (CLK, RSTB, A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A0 * B0 + A1 * B1; + end +end + + assign Y = Y_reg; + +endmodule + +module mac12x10_regio (CLK, RSTB, A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + Y_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + Y_reg = A0_reg * B0_reg + A1_reg * B1_reg; + end +end + + assign Y = Y_reg; + +endmodule + + +//------------------------------------------------- +// Multipliers +module mult12x10 (A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + + assign Y = A * B; + +endmodule + +module mult12x10_regi (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + end +end + + assign Y = A_reg * B_reg; + +endmodule + +module mult12x10_rego (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A * B; + end +end + + assign Y = Y_reg; + +endmodule + +module mult12x10_regio (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + Y_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + Y_reg <= A_reg * B_reg; + end +end + + assign Y = Y_reg; + +endmodule + + +module mult24x20 (A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + + assign Y = A * B; + +endmodule + +module mult24x20_regi (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + end +end + + assign Y = A_reg * B_reg; + +endmodule + +module mult24x20_rego (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A * B; + end +end + + assign Y = Y_reg; + +endmodule + +module mult24x20_regio (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + Y_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + Y_reg <= A_reg * B_reg; + end +end + + assign Y = Y_reg; + +endmodule + + +// A half multiplier which only output the most significant 11 bit +module half_mult12x10 (A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH/2-1] Y; + +wire [0:Y_WIDTH-1] mult_out; + + mult12x10 FULL_MULT (.A(A), + .B(B), + .Y(mult_out) + ); + assign Y = mult_out[0:Y_WIDTH/2-1]; + +endmodule diff --git a/techlibs/rapidflex/alkaidL/cell_sim_ff.v b/techlibs/rapidflex/alkaidL/cell_sim_ff.v new file mode 100644 index 000000000..726987e16 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/cell_sim_ff.v @@ -0,0 +1,586 @@ +//----------------------------- +// Rising-edge D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffn( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffns( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffns( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Two-bit D-type flip-flop with active-high asynchronous reset +// 1st stage is positive-edge triggered +// 2nd stage is negative-edge triggered +//----------------------------- +// Do not allow ABC or other optimization to touch the ff! +//(* abc9_flop, lib_whitebox *) +module dffnr_dffr( + output Q, + input D, + input R, + input C +); + +wire Q0; + + dffnr FF_0 (.D(D), .C(C), .R(R), .Q(Q0)); + dffr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q)); + +endmodule + +//----------------------------- +// Two-bit D-type flip-flop with active-high asynchronous reset +// 1st stage is positive-edge triggered +// 2nd stage is negative-edge triggered +//----------------------------- +// Do not allow ABC or other optimization to touch the ff! +//(* abc9_flop, lib_whitebox *) +module dffr_dffnr( + output Q, + input D, + input R, + input C +); + +wire Q0; + + dffr FF_0 (.D(D), .C(C), .R(R), .Q(Q0)); + dffnr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q)); + +endmodule + diff --git a/techlibs/rapidflex/alkaidL/dff_map.v b/techlibs/rapidflex/alkaidL/dff_map.v new file mode 100644 index 000000000..f6d01a4ed --- /dev/null +++ b/techlibs/rapidflex/alkaidL/dff_map.v @@ -0,0 +1,177 @@ +// Rising edge DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Rising edge DFF with async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Rising edge DFF with async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Rising edge DFF with async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Rising edge DFF with async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Rising edge DFF with sync active-high reset +module \$_SDFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Rising edge DFF with sync active-high set +module \$_SDFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Rising edge DFF with sync active-low reset +module \$_SDFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Rising edge DFF with sync active-low set +module \$_SDFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Falling edge DFF +module \$_DFF_N_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Falling edge DFF with async active-high reset +module \$_DFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Falling edge DFF with async active-high set +module \$_DFF_NP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Falling edge DFF with async active-low reset +module \$_DFF_NN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Falling edge DFF with async active-low set +module \$_DFF_NN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Falling edge DFF with sync active-high reset +module \$_SDFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Falling edge DFF with sync active-high set +module \$_SDFF_NP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Falling edge DFF with sync active-low reset +module \$_SDFF_NN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Falling edge DFF with sync active-low set +module \$_SDFF_NN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/techlibs/rapidflex/alkaidL/dsp_map.v b/techlibs/rapidflex/alkaidL/dsp_map.v new file mode 100644 index 000000000..adc8aff29 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/dsp_map.v @@ -0,0 +1,17 @@ +module mult_14x10_map ( + input [0:13] A, + input [0:9] B, + output [0:23] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult_14x10 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/techlibs/rapidflex/alkaidL/synth.ys b/techlibs/rapidflex/alkaidL/synth.ys new file mode 100644 index 000000000..4844ccf0b --- /dev/null +++ b/techlibs/rapidflex/alkaidL/synth.ys @@ -0,0 +1,128 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt -nodffe + +opt_expr +opt_clean +check +opt -nodffe +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +#memory_dff +#wreduce t:$mul +#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +#select a:mul2dsp +#setattr -unset mul2dsp +#opt_expr -fine +#wreduce +#select -clear +#chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +alumacc +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#opt -fast -nodffe +#opt_expr +#opt_merge +#opt_clean +#opt -nodffe +#share +#opt -nodffe +#fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +#opt -fast -nodffe +opt +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +#techmap -map ${YOSYS_BRAM_MAP_VERILOG} +#opt -fast -mux_undef -undriven -fine -nodffe +#memory_map +#opt -undriven -fine -nodffe + +######################## +# Map Adders +techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +opt -fast -nodffe +opt_expr +opt_merge +opt_clean +opt -nodffe + +######################### +# Map flip-flops +######################### +memory +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_dff -nodffe +opt_clean +opt -nodffe + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} +# Map dff again since ABC may generate some new FFs +techmap -map ${YOSYS_DFF_MAP_VERILOG} +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} +write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidL/synth_no_adder.ys b/techlibs/rapidflex/alkaidL/synth_no_adder.ys new file mode 100644 index 000000000..bef3c7dc5 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/synth_no_adder.ys @@ -0,0 +1,128 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt -nodffe + +opt_expr +opt_clean +check +opt -nodffe +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +#memory_dff +#wreduce t:$mul +#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +#select a:mul2dsp +#setattr -unset mul2dsp +#opt_expr -fine +#wreduce +#select -clear +#chtype -set $mul t:$__soft_mul# Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +alumacc +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#opt -fast -nodffe +#opt_expr +#opt_merge +#opt_clean +#opt -nodffe +#share +#opt -nodffe +#fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +#opt -fast -nodffe +opt +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +#techmap -map ${YOSYS_BRAM_MAP_VERILOG} +#opt -fast -mux_undef -undriven -fine -nodffe +#memory_map +#opt -undriven -fine -nodffe + +######################## +# Map Adders +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#opt -fast -nodffe +#opt_expr +#opt_merge +#opt_clean +#opt -nodffe + +######################### +# Map flip-flops +######################### +memory +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_dff -nodffe +opt_clean +opt -nodffe + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} +# Map dff again since ABC may generate some new FFs +techmap -map ${YOSYS_DFF_MAP_VERILOG} +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} +write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidL/verilog_rewrite.ys b/techlibs/rapidflex/alkaidL/verilog_rewrite.ys new file mode 100644 index 000000000..217e8d558 --- /dev/null +++ b/techlibs/rapidflex/alkaidL/verilog_rewrite.ys @@ -0,0 +1,41 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff +clean + +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_verilog ${OUTPUT_VERILOG} diff --git a/techlibs/rapidflex/alkaidT/arith_map.v b/techlibs/rapidflex/alkaidT/arith_map.v new file mode 100644 index 000000000..d54433654 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/arith_map.v @@ -0,0 +1,154 @@ +// Arithmetic units: adder +// Adapt from: https://github.com/chipsalliance/yosys-f4pga-plugins/blob/0ad1af26a29243a9e76379943d735e119dcd0cc6/ql-qlf-plugin/qlf_k6n10/cells_sim.v +// Many thanks to F4PGA for their contribution + +(* techmap_celltype = "$alu" *) +module _80_quicklogic_alu (A, B, CI, BI, X, Y, CO); + + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] X, Y; + + input CI, BI; + output [Y_WIDTH-1:0] CO; + + // The max. number of adders we can support in AlkaidS is (12x2-1)x4x16 = 1472 + // Fail when resource limit exceeds + // Also fail when a low utilization rate is detected + // Originally prefer to defer carry mapping when < 2-bit adder is detected + // Due to a bug found in scalable seq detector, the bound is increased to 4-bit adder + wire _TECHMAP_FAIL_ = Y_WIDTH > 1472 || Y_WIDTH < 4; + generate + if ((A_WIDTH == 0 || B_WIDTH == 0) && Y_WIDTH > 0) begin + wire _TECHMAP_FAIL_ = 1; + end + endgenerate + wire [1024:0] _TECHMAP_DO_ = "splitnets CARRY; clean"; + localparam Y_COL_WIDTH = 96 - 3; + localparam Y_MAX_WIDTH = 12 - 3; + + (* force_downto *) + wire [Y_WIDTH-1:0] A_buf, B_buf; + \$pos #(.A_SIGNED(A_SIGNED), .A_WIDTH(A_WIDTH), .Y_WIDTH(Y_WIDTH)) A_conv (.A(A), .Y(A_buf)); + \$pos #(.A_SIGNED(B_SIGNED), .A_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) B_conv (.A(B), .Y(B_buf)); + + (* force_downto *) + wire [Y_WIDTH-1:0] AA = A_buf; + (* force_downto *) + wire [Y_WIDTH-1:0] BB = BI ? ~B_buf : B_buf; + wire [Y_WIDTH: 0] CARRY; + + assign CO[Y_WIDTH-1:0] = CARRY[Y_WIDTH:1]; + genvar i; + generate if (Y_WIDTH < Y_COL_WIDTH) begin + wire CARRY_end_buf; + wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[Y_WIDTH] CARRY_end_buf"; + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + + _fpga_adder pretaill_adder ( + .cin (CARRY[Y_WIDTH-1] ), + .cout (CARRY_end_buf), + .a (AA[Y_WIDTH-1] ), + .b (BB[Y_WIDTH-1] ), + .sumout (Y[Y_WIDTH-1] ) + ); + + + _fpga_adder tail_adder ( + .cin (CARRY_end_buf), + .cout (), + .a (1'b0), + .b (1'b0), + .sumout (CARRY[Y_WIDTH]) + ); + + generate for (i = 1; i < Y_WIDTH-1 ; i = i+1) begin:gen3 + _fpga_adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end endgenerate + end else begin + generate for (i = 0; i < Y_WIDTH ; i = i+1) begin:gen4 + // Due to VPR limitations regarding IO connexion to carry chain, + // we generate the carry chain input signal using an intermediate adder + // since we can connect a & b from io pads, but not cin & cout + if (i == 0) begin + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY[0]), + .a (CI ), + .b (CI ), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY[0]), + .cout (CARRY[1]), + .a (AA[0] ), + .b (BB[0] ), + .sumout (Y[0] ) + ); + end else if (i % (Y_MAX_WIDTH + 1) == 0) begin + wire CARRY_end_buf; + wire CARRY_start_buf; + wire [1024:0] _TECHMAP_DO_ = "insbuf CARRY[i+1] CARRY_end_buf; insbuf CARRY_end_buf CARRY_start_buf"; + _fpga_adder tail_adder ( + .cin (CARRY[i]), + .cout (), + .a (1'b0), + .b (1'b0), + .sumout (CARRY_end_buf) + ); + + _fpga_adder intermediate_adder ( + .cin ( ), + .cout (CARRY_start_buf), + .a (CARRY_end_buf), + .b (1'b1), + .sumout ( ) + ); + + _fpga_adder first_adder ( + .cin (CARRY_start_buf), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end else begin + _fpga_adder my_adder ( + .cin (CARRY[i] ), + .cout (CARRY[i+1]), + .a (AA[i] ), + .b (BB[i] ), + .sumout (Y[i] ) + ); + end + end endgenerate + end endgenerate + assign X = AA ^ BB; +endmodule diff --git a/techlibs/rapidflex/alkaidT/bram.txt b/techlibs/rapidflex/alkaidT/bram.txt new file mode 100644 index 000000000..4ccf4ba0a --- /dev/null +++ b/techlibs/rapidflex/alkaidT/bram.txt @@ -0,0 +1,314 @@ +bram $__FLEX_TDPRAM_256x36 # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 8 # Number of address bits + dbits 36 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_256x36 + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_256x36_wclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 8 # Number of address bits + dbits 36 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_256x36_wclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 19 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_256x36_rclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 8 # Number of address bits + dbits 36 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_256x36_rclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 19 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_256x36_rwclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 8 # Number of address bits + dbits 36 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_256x36_rwclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 19 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_512x18 # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 9 # Number of address bits + dbits 18 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_512x18 + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 10 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_512x18_wclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 9 # Number of address bits + dbits 18 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_512x18_wclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 10 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_512x18_rclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 9 # Number of address bits + dbits 18 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_512x18_rclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 10 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_512x18_rwclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 9 # Number of address bits + dbits 18 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_512x18_rwclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 10 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_1024x9 # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 10 # Number of address bits + dbits 9 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_1024x9 + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 5 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_1024x9_wclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 10 # Number of address bits + dbits 9 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_1024x9_wclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 5 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_1024x9_rclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 10 # Number of address bits + dbits 9 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_1024x9_rclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 5 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_1024x9_rwclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 10 # Number of address bits + dbits 9 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_1024x9_rwclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + min dbits 5 + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_2048x4 # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 11 # Number of address bits + dbits 4 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_2048x4 + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_2048x4_wclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 11 # Number of address bits + dbits 4 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 1 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_2048x4_wclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_2048x4_rclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 11 # Number of address bits + dbits 4 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 1 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_2048x4_rclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary + or_next_if_better +endmatch + +bram $__FLEX_TDPRAM_2048x4_rwclkn # Name of the BRAM cell + init 0 # Set to '1' if BRAM can be initialized + abits 11 # Number of address bits + dbits 4 # Number of data bits + groups 2 # Number of port groups + ports 1 1 # Number of ports in each group + wrmode 0 1 # Set to '1' if this group is write ports + enable 1 1 # Number of enable bits + transp 0 0 # transparent (read ports) + clocks 2 3 # clock configuration + clkpol 0 0 # clock polarity configuration +endbram + +match $__FLEX_TDPRAM_2048x4_rwclkn + min efficiency 0 # Only use this bram is <=0 ram bits are used + make_transp # Add external circuitry to simulate 'transparent read' if necessary +endmatch + diff --git a/techlibs/rapidflex/alkaidT/bram_map.v b/techlibs/rapidflex/alkaidT/bram_map.v new file mode 100644 index 000000000..fa9892fc7 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/bram_map.v @@ -0,0 +1,575 @@ +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_256x36 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:7] A1ADDR; + input A1EN; + output [0:35] A1DATA; + input [0:7] B1ADDR; + input B1EN; + input [0:35] B1DATA; + + generate + dpram256x36 + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_256x36_WCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:7] A1ADDR; + input A1EN; + output [0:35] A1DATA; + input [0:7] B1ADDR; + input B1EN; + input [0:35] B1DATA; + + generate + dpram256x36_wclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_256x36_RCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:7] A1ADDR; + input A1EN; + output [0:35] A1DATA; + input [0:7] B1ADDR; + input B1EN; + input [0:35] B1DATA; + + generate + dpram256x36_rclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_256x36_RWCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:7] A1ADDR; + input A1EN; + output [0:35] A1DATA; + input [0:7] B1ADDR; + input B1EN; + input [0:35] B1DATA; + + generate + dpram256x36_rwclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_512x18 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:8] A1ADDR; + input A1EN; + output [0:17] A1DATA; + input [0:8] B1ADDR; + input B1EN; + input [0:17] B1DATA; + + generate + dpram512x18 + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_512x18_WCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:8] A1ADDR; + input A1EN; + output [0:17] A1DATA; + input [0:8] B1ADDR; + input B1EN; + input [0:17] B1DATA; + + generate + dpram512x18_wclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_512x18_RCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:8] A1ADDR; + input A1EN; + output [0:17] A1DATA; + input [0:8] B1ADDR; + input B1EN; + input [0:17] B1DATA; + + generate + dpram512x18_rclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_512x18_RWCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:8] A1ADDR; + input A1EN; + output [0:17] A1DATA; + input [0:8] B1ADDR; + input B1EN; + input [0:17] B1DATA; + + generate + dpram512x18_rwclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_1024x9 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:9] A1ADDR; + input A1EN; + output [0:8] A1DATA; + input [0:9] B1ADDR; + input B1EN; + input [0:8] B1DATA; + + generate + dpram1024x9 + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_1024x9_WCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:9] A1ADDR; + input A1EN; + output [0:8] A1DATA; + input [0:9] B1ADDR; + input B1EN; + input [0:8] B1DATA; + + generate + dpram1024x9_wclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_1024x9_RCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:9] A1ADDR; + input A1EN; + output [0:8] A1DATA; + input [0:9] B1ADDR; + input B1EN; + input [0:8] B1DATA; + + generate + dpram1024x9_rclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_1024x9_RWCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:9] A1ADDR; + input A1EN; + output [0:8] A1DATA; + input [0:9] B1ADDR; + input B1EN; + input [0:8] B1DATA; + + generate + dpram1024x9_rwclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_2048x4 (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:10] A1ADDR; + input A1EN; + output [0:3] A1DATA; + input [0:10] B1ADDR; + input B1EN; + input [0:3] B1DATA; + + generate + dpram2048x4 + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_2048x4_WCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 1; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:10] A1ADDR; + input A1EN; + output [0:3] A1DATA; + input [0:10] B1ADDR; + input B1EN; + input [0:3] B1DATA; + + generate + dpram2048x4_wclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_2048x4_RCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 1; + + input CLK2; + input CLK3; + input [0:10] A1ADDR; + input A1EN; + output [0:3] A1DATA; + input [0:10] B1ADDR; + input B1EN; + input [0:3] B1DATA; + + generate + dpram2048x4_rclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule + +//----------------------------- +// This is a true dual-port RAM +// BUT without support on Byte-Write-Enable +// Due to limited support from Yosys +//----------------------------- +module \$__FLEX_TDPRAM_2048x4_RWCLKN (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); + + parameter [0:0] CLKPOL2 = 0; + parameter [0:0] CLKPOL3 = 0; + + input CLK2; + input CLK3; + input [0:10] A1ADDR; + input A1EN; + output [0:3] A1DATA; + input [0:10] B1ADDR; + input B1EN; + input [0:3] B1DATA; + + generate + dpram2048x4_rwclkn + _TECHMAP_REPLACE_ ( + .rclk_i (CLK2), + .wclk_i (CLK3), + .bwen_ni (|1), + .wen_ni (B1EN), + .waddr_i (B1ADDR), + .data_i (B1DATA), + .ren_ni (A1EN), + .raddr_i (A1ADDR), + .q_o (A1DATA) + ); + endgenerate + +endmodule diff --git a/techlibs/rapidflex/alkaidT/cell_sim.v b/techlibs/rapidflex/alkaidT/cell_sim.v new file mode 100644 index 000000000..fe5126e06 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/cell_sim.v @@ -0,0 +1,8 @@ +//------------------------------------------------- +// Include all the primitives +//------------------------------------------------- +`include "cell_sim_arith.v" +`include "cell_sim_dsp.v" +`include "cell_sim_new_dsp.v" +`include "cell_sim_bram.v" +`include "cell_sim_ff.v" diff --git a/techlibs/rapidflex/alkaidT/cell_sim_arith.v b/techlibs/rapidflex/alkaidT/cell_sim_arith.v new file mode 100644 index 000000000..5a325e5b6 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/cell_sim_arith.v @@ -0,0 +1,15 @@ +//--------------------------------------- +// 1-bit adder +//--------------------------------------- +(* abc9_box, lib_whitebox *) +module _fpga_adder( + output sumout, + output cout, + input a, + input b, + input cin +); + assign sumout = a ^ b ^ cin; + assign cout = (a & b) | ((a | b) & cin); + +endmodule diff --git a/techlibs/rapidflex/alkaidT/cell_sim_bram.v b/techlibs/rapidflex/alkaidT/cell_sim_bram.v new file mode 100644 index 000000000..57a320821 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/cell_sim_bram.v @@ -0,0 +1,876 @@ +//------------------------------------------------- +// Block RAM Primitives +//------------------------------------------------- + +//------------------------------------------------- +// True Dual-port RAM Core logic +// This module is written in a scalable way +// By default it is configured as 256x36 = 9k-bits +// +// IMPORTANT: Please do not use this module as a hard ip!!! +module tdpram_core (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); +// Parameters +parameter ADDR_WIDTH = 8; +parameter DEPTH = 2**ADDR_WIDTH; +parameter BYTE_WIDTH = 9; +parameter NUM_BYTES = 4; +parameter [0:0] IS_WCLK_N = 1'b0; // Indicate if the write clock is triggered at negative edge: 1 = Yes; 0 = No +parameter [0:0] IS_RCLK_N = 1'b0; // Indicate if the read clock is triggered at negative edge: 1 = Yes; 0 = No + +input ren_ni; +input wen_ni; +input [0:ADDR_WIDTH-1] raddr_i; +input [0:ADDR_WIDTH-1] waddr_i; +input [0:BYTE_WIDTH*NUM_BYTES-1] bwen_ni; +input [0:BYTE_WIDTH*NUM_BYTES-1] data_i; +input wclk_i; +input rclk_i; +output [0:BYTE_WIDTH*NUM_BYTES-1] q_o; + +reg [0:NUM_BYTES*BYTE_WIDTH-1] ram[0:DEPTH-1]; +reg [0:NUM_BYTES*BYTE_WIDTH-1] q_reg; + +integer i; + +assign q_o = q_reg; + +// Initial values are all random, to mimic the actual behavoir of a RAM +initial begin + for (i = 0; i < DEPTH; i = i + 1) begin + ram[i] = $random; + end + q_reg <= $random; +end + +case(|IS_WCLK_N) + 1'b0: + always @(posedge wclk_i) begin + if (~wen_ni) begin + for (i = 0; i < NUM_BYTES * BYTE_WIDTH; i = i + 1) begin + if (~bwen_ni[i]) begin + ram[waddr_i][i] <= data_i[i]; + end + end + end + end + 1'b1: + always @(negedge wclk_i) begin + if (~wen_ni) begin + for (i = 0; i < NUM_BYTES * BYTE_WIDTH; i = i + 1) begin + if (~bwen_ni[i]) begin + ram[waddr_i][i] <= data_i[i]; + end + end + end + end +endcase + +case(|IS_RCLK_N) + 1'b0: + always @(posedge rclk_i) begin + if (~ren_ni) begin + q_reg <= ram[raddr_i]; + end + end + 1'b1: + always @(negedge rclk_i) begin + if (~ren_ni) begin + q_reg <= ram[raddr_i]; + end + end +endcase + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram256x36 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram256x36_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram256x36_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 256x36 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram256x36_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:7] raddr_i; +input [0:7] waddr_i; +input [0:35] bwen_ni; +input [0:35] data_i; +input wclk_i; +input rclk_i; +output [0:35] q_o; + + tdpram_core #( + .ADDR_WIDTH(8), + .BYTE_WIDTH(9), + .NUM_BYTES(4), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram512x18 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram512x18_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram512x18_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 512x18 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram512x18_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:8] raddr_i; +input [0:8] waddr_i; +input [0:17] bwen_ni; +input [0:17] data_i; +input wclk_i; +input rclk_i; +output [0:17] q_o; + + tdpram_core #( + .ADDR_WIDTH(9), + .BYTE_WIDTH(9), + .NUM_BYTES(2), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram1024x9 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram1024x9_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram1024x9_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 1024x9 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram1024x9_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:9] raddr_i; +input [0:9] waddr_i; +input [0:8] bwen_ni; +input [0:8] data_i; +input wclk_i; +input rclk_i; +output [0:8] q_o; + + tdpram_core #( + .ADDR_WIDTH(10), + .BYTE_WIDTH(9), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram2048x4 (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [x] positive edge +// - [ ] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram2048x4_wclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(0) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [x] positive edge +// - [ ] negative edge +module dpram2048x4_rclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(0), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule + +//------------------------------------------------- +// True Dual-port RAM Core logic 2048x4 +// - read clock is triggered at +// - [ ] positive edge +// - [x] negative edge +// - write clock is triggered at +// - [ ] positive edge +// - [x] negative edge +module dpram2048x4_rwclkn (wclk_i, + bwen_ni, + wen_ni, + waddr_i, + data_i, + rclk_i, + ren_ni, + raddr_i, + q_o + ); + +input ren_ni; +input wen_ni; +input [0:10] raddr_i; +input [0:10] waddr_i; +input [0:3] bwen_ni; +input [0:3] data_i; +input wclk_i; +input rclk_i; +output [0:3] q_o; + + tdpram_core #( + .ADDR_WIDTH(11), + .BYTE_WIDTH(4), + .NUM_BYTES(1), + .IS_WCLK_N(1), + .IS_RCLK_N(1) + ) tdpram_core ( + .rclk_i (rclk_i), + .wclk_i (wclk_i), + .bwen_ni (bwen_ni), + .wen_ni (wen_ni), + .waddr_i (waddr_i), + .data_i (data_i), + .ren_ni (ren_ni), + .raddr_i (raddr_i), + .q_o (q_o) + ); + +endmodule diff --git a/techlibs/rapidflex/alkaidT/cell_sim_dsp.v b/techlibs/rapidflex/alkaidT/cell_sim_dsp.v new file mode 100644 index 000000000..244086e10 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/cell_sim_dsp.v @@ -0,0 +1,561 @@ +//------------------------------------------------- +// DSP Primitives +//------------------------------------------------- + +//------------------------------------------------- +// Multiply accumulators +module quad_mac12x10 (A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + + assign Y = A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3; + +endmodule + +//------------------------------------------------- +// Multiply accumulators with input registering +module quad_mac12x10_regi (CLK, RSTB, A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; +reg [0:A_WIDTH-1] A2_reg; +reg [0:B_WIDTH-1] B2_reg; +reg [0:A_WIDTH-1] A3_reg; +reg [0:B_WIDTH-1] B3_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + A2_reg <= 0; + B2_reg <= 0; + A3_reg <= 0; + B3_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + A2_reg <= A2; + B2_reg <= B2; + A3_reg <= A3; + B3_reg <= B3; + end +end + +assign Y = A0_reg * B0_reg + A1_reg * B1_reg + A2_reg * B2_reg + A3_reg * B3_reg; + +endmodule + +//------------------------------------------------- +// Multiply accumulators with output registering +module quad_mac12x10_rego (CLK, RSTB, A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3; + end +end + +assign Y = Y_reg; + +endmodule + +//------------------------------------------------- +// Multiply accumulators with input and output registering +module quad_mac12x10_regio (CLK, RSTB, A0, B0, A1, B1, A2, B2, A3, B3, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; +reg [0:A_WIDTH-1] A2_reg; +reg [0:B_WIDTH-1] B2_reg; +reg [0:A_WIDTH-1] A3_reg; +reg [0:B_WIDTH-1] B3_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + A2_reg <= 0; + B2_reg <= 0; + A3_reg <= 0; + B3_reg <= 0; + Y_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + A2_reg <= A2; + B2_reg <= B2; + A3_reg <= A3; + B3_reg <= B3; + Y_reg <= A0_reg * B0_reg + A1_reg * B1_reg + A2_reg * B2_reg + A3_reg * B3_reg; + end +end + +assign Y = Y_reg; + +endmodule + + +module quad_mac12x10_dual_output (A0, B0, A1, B1, A2, B2, A3, B3, Y0, Y1); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +input [0:A_WIDTH-1] A2; +input [0:B_WIDTH-1] B2; +input [0:A_WIDTH-1] A3; +input [0:B_WIDTH-1] B3; +output [0:Y_WIDTH-1] Y0; +output [0:Y_WIDTH-1] Y1; + + assign Y0 = A0 * B0 + A1 * B1 + A2 * B2 + A3 * B3; + assign Y1 = A2 * B2 + A3 * B3; + +endmodule + +module mac12x10 (A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + + assign Y = A0 * B0 + A1 * B1; + +endmodule + +module mac12x10_regi (CLK, RSTB, A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + end +end + + assign Y = A0_reg * B0_reg + A1_reg * B1_reg; + +endmodule + +module mac12x10_rego (CLK, RSTB, A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A0 * B0 + A1 * B1; + end +end + + assign Y = Y_reg; + +endmodule + +module mac12x10_regio (CLK, RSTB, A0, B0, A1, B1, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:A_WIDTH-1] A1; +input [0:B_WIDTH-1] B1; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A0_reg; +reg [0:B_WIDTH-1] B0_reg; +reg [0:A_WIDTH-1] A1_reg; +reg [0:B_WIDTH-1] B1_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A0_reg <= 0; + B0_reg <= 0; + A1_reg <= 0; + B1_reg <= 0; + Y_reg <= 0; + end else begin + A0_reg <= A0; + B0_reg <= B0; + A1_reg <= A1; + B1_reg <= B1; + Y_reg = A0_reg * B0_reg + A1_reg * B1_reg; + end +end + + assign Y = Y_reg; + +endmodule + + +//------------------------------------------------- +// Multipliers +module mult12x10 (A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + + assign Y = A * B; + +endmodule + +module mult12x10_regi (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + end +end + + assign Y = A_reg * B_reg; + +endmodule + +module mult12x10_rego (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A * B; + end +end + + assign Y = Y_reg; + +endmodule + +module mult12x10_regio (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + Y_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + Y_reg <= A_reg * B_reg; + end +end + + assign Y = Y_reg; + +endmodule + + +module mult24x20 (A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + + assign Y = A * B; + +endmodule + +module mult24x20_regi (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + end +end + + assign Y = A_reg * B_reg; + +endmodule + +module mult24x20_rego (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + Y_reg <= 0; + end else begin + Y_reg <= A * B; + end +end + + assign Y = Y_reg; + +endmodule + +module mult24x20_regio (CLK, RSTB, A, B, Y); +// Parameters +parameter A_WIDTH = 24; +parameter B_WIDTH = 20; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input CLK; +input RSTB; +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH-1] Y; + +reg [0:A_WIDTH-1] A_reg; +reg [0:B_WIDTH-1] B_reg; +reg [0:Y_WIDTH-1] Y_reg; + +always @(posedge CLK) begin + if (RSTB == 1'b0) begin + A_reg <= 0; + B_reg <= 0; + Y_reg <= 0; + end else begin + A_reg <= A; + B_reg <= B; + Y_reg <= A_reg * B_reg; + end +end + + assign Y = Y_reg; + +endmodule + + +// A half multiplier which only output the most significant 11 bit +module half_mult12x10 (A, B, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A; +input [0:B_WIDTH-1] B; +output [0:Y_WIDTH/2-1] Y; + +wire [0:Y_WIDTH-1] mult_out; + + mult12x10 FULL_MULT (.A(A), + .B(B), + .Y(mult_out) + ); + assign Y = mult_out[0:Y_WIDTH/2-1]; + +endmodule + +module mad12x10x22 (A0, B0, C0, Y); +// Parameters +parameter A_WIDTH = 12; +parameter B_WIDTH = 10; +parameter Y_WIDTH = A_WIDTH + B_WIDTH; + +input [0:A_WIDTH-1] A0; +input [0:B_WIDTH-1] B0; +input [0:Y_WIDTH-1] C0; +output [0:Y_WIDTH-1] Y; + + assign Y = A0 * B0 + C0; + +endmodule + diff --git a/techlibs/rapidflex/alkaidT/cell_sim_ff.v b/techlibs/rapidflex/alkaidT/cell_sim_ff.v new file mode 100644 index 000000000..726987e16 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/cell_sim_ff.v @@ -0,0 +1,586 @@ +//----------------------------- +// Rising-edge D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dff( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-high synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffs( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Rising-edge D-type flip-flop with active-low synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b0; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffn( + output reg Q, + input D, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + Q <= D; + 1'b1: + always @(negedge C) + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or posedge R) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffns( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or posedge S) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low asynchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C or negedge RN) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low asynchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module dffnsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C or negedge SN) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnr( + output reg Q, + input D, + input R, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (R == 1'b1) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-high synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffns( + output reg Q, + input D, + input S, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (S == 1'b1) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low synchronous reset +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnrn( + output reg Q, + input D, + input RN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + 1'b1: + always @(negedge C) + if (RN == 1'b0) + Q <= 1'b0; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Falling-edge D-type flip-flop with active-low synchronous set +//----------------------------- +(* abc9_flop, lib_whitebox *) +module sdffnsn( + output reg Q, + input D, + input SN, + (* clkbuf_sink *) + (* invertible_pin = "IS_C_INVERTED" *) + input C +); + parameter [0:0] INIT = 1'b0; + parameter [0:0] IS_C_INVERTED = 1'b1; + initial Q = INIT; + case(|IS_C_INVERTED) + 1'b0: + always @(posedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + 1'b1: + always @(negedge C) + if (SN == 1'b0) + Q <= 1'b1; + else + Q <= D; + endcase +endmodule + +//----------------------------- +// Two-bit D-type flip-flop with active-high asynchronous reset +// 1st stage is positive-edge triggered +// 2nd stage is negative-edge triggered +//----------------------------- +// Do not allow ABC or other optimization to touch the ff! +//(* abc9_flop, lib_whitebox *) +module dffnr_dffr( + output Q, + input D, + input R, + input C +); + +wire Q0; + + dffnr FF_0 (.D(D), .C(C), .R(R), .Q(Q0)); + dffr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q)); + +endmodule + +//----------------------------- +// Two-bit D-type flip-flop with active-high asynchronous reset +// 1st stage is positive-edge triggered +// 2nd stage is negative-edge triggered +//----------------------------- +// Do not allow ABC or other optimization to touch the ff! +//(* abc9_flop, lib_whitebox *) +module dffr_dffnr( + output Q, + input D, + input R, + input C +); + +wire Q0; + + dffr FF_0 (.D(D), .C(C), .R(R), .Q(Q0)); + dffnr FF_1 (.D(Q0), .C(C), .R(R), .Q(Q)); + +endmodule + diff --git a/techlibs/rapidflex/alkaidT/cell_sim_new_dsp.v b/techlibs/rapidflex/alkaidT/cell_sim_new_dsp.v new file mode 100644 index 000000000..18faf9cf3 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/cell_sim_new_dsp.v @@ -0,0 +1,385 @@ +module mad12x10x22 (clk_i, rst_ni, a_i, b_i, d_i, out_o, mode_i, rst_acc, accsel, cas_g, overflow); + +input [0:47] a_i; +input [0:39] b_i; +input [0:59] d_i; +input [0:12] mode_i; +output [0:59] out_o; + +input clk_i; +input rst_ni; +input rst_acc; +input accsel; +input cas_g; +output overflow; + + dsp #( + .N_SIZE (12), + .M_SIZE (10) + ) u_dsp( + .a_i (a_i), + .b_i (b_i), + .out_o (out_o), + + .clk_i (clk_i), + .rst_ni (rst_ni), + .d_i (d_i), + .mode_i (mode_i), + .rst_acc (rst_acc), + .accsel (accsel), + .cas_g (cas_g), + .overflow (overflow) + ); + +endmodule + +module mad24x20x44 (clk_i, rst_ni, a_i, b_i, d_i, out_o, mode_i, rst_acc, accsel, cas_g, overflow); + +input [0:95] a_i; +input [0:79] b_i; +input [0:103] d_i; +input [0:12] mode_i; +output [0:103] out_o; + +input clk_i; +input rst_ni; +input rst_acc; +input accsel; +input cas_g; +output overflow; + + dsp #( + .N_SIZE (24), + .M_SIZE (20) + ) u_dsp( + .a_i (a_i), + .b_i (b_i), + .out_o (out_o), + + .clk_i (clk_i), + .rst_ni (rst_ni), + .d_i (d_i), + .mode_i (mode_i), + .rst_acc (rst_acc), + .accsel (accsel), + .cas_g (cas_g), + .overflow (overflow) + ); + +endmodule + +//----------------------------------------------------- +// Design Name : Parameterized DSP block +// File Name : dsp.v +// Function : A N*M-bit DSP block which can operate in fracturable modes: +// 1. four [N/4]*[M/4]-bit multiplication with accumulation +// 1.1 (combinational) +// 1.2 (with input registers triggered by rising edge) +// 1.3 (with output registers triggered by rising edge) +// 1.4 (with input and output registers triggered by rising edge) +// 1.5 (with input registers triggered by falling edge) +// 1.6 (with output registers triggered by falling edge) +// 1.7 (with input and output registers triggered by falling edge) +// 2. two [N/2]*[M/2]-bit multipliers +// 2.1 (combinational) +// 2.2 (with input registers triggered by rising edge) +// 2.3 (with output registers triggered by rising edge) +// 2.4 (with input and output registers triggered by rising edge) +// 2.5 (with input registers triggered by falling edge) +// 2.6 (with output registers triggered by falling edge) +// 2.7 (with input and output registers triggered by falling edge) +// 3. Single N*M-bit multipliers +// 3.1 (combinational) +// 3.2 (with input registers triggered by rising edge) +// 3.3 (with output registers triggered by rising edge) +// 3.4 (with input and output registers triggered by rising edge) +// 3.5 (with input registers triggered by falling edge) +// 3.6 (with output registers triggered by falling edge) +// 3.7 (with input and output registers triggered by falling edge) +// 4. Two [N/4]*[M/4]-bit multiply-accumulators +// 4.1 (combinational) +// 4.2 (with input registers triggered by rising edge) +// 4.3 (with output registers triggered by rising edge) +// 4.4 (with input and output registers triggered by rising edge) +// 4.5 (with input registers triggered by falling edge) +// 4.6 (with output registers triggered by falling edge) +// 4.7 (with input and output registers triggered by falling edge) +// 5. One [N/4]*[M/4]-bit multiplier + One [N/4]*[M/4]-bit MAC +// 5.1 (combinational) +// 5.2 (with input registers triggered by rising edge) +// 5.3 (with output registers triggered by rising edge) +// 5.4 (with input and output registers triggered by rising edge) +// 5.5 (with input registers triggered by falling edge) +// 5.6 (with output registers triggered by falling edge) +// 5.7 (with input and output registers triggered by falling edge) +// 6. One [N/4]*[M/4]-bit MAC + One [N/4]*[M/4]-bit multiply +// 6.1 (combinational) +// 6.2 (with input registers triggered by rising edge) +// 6.3 (with output registers triggered by rising edge) +// 6.4 (with input and output registers triggered by rising edge) +// 6.5 (with input registers triggered by falling edge) +// 6.6 (with output registers triggered by falling edge) +// 6.7 (with input and output registers triggered by falling edge) +// 7. MSB parts [N/2+M/2] of four multipliers +// 7.1 (combinational) +// 7.2 (with input registers triggered by rising edge) +// 7.3 (with output registers triggered by rising edge) +// 7.4 (with input and output registers triggered by rising edge) +// 7.5 (with input registers triggered by falling edge) +// 7.6 (with output registers triggered by falling edge) +// 7.7 (with input and output registers triggered by falling edge) +// 8. One [N/4]*[M/4]-bit multiply + MSB parts [N/2+M/2] of four multipliers +// 8.1 (combinational) +// 8.2 (with input registers triggered by rising edge) +// 8.3 (with output registers triggered by rising edge) +// 8.4 (with input and output registers triggered by rising edge) +// 8.5 (with input registers triggered by falling edge) +// 8.6 (with output registers triggered by falling edge) +// 8.7 (with input and output registers triggered by falling edge) +// 9. One [N/4]*[M/4]-bit MAC + MSB parts [N/2+M/2] of four multipliers +// 9.1 (combinational) +// 9.2 (with input registers triggered by rising edge) +// 9.3 (with output registers triggered by rising edge) +// 9.4 (with input and output registers triggered by rising edge) +// 9.5 (with input registers triggered by falling edge) +// 9.6 (with output registers triggered by falling edge) +// 9.7 (with input and output registers triggered by falling edge) +// - In all the above modes, clock edges can be either positive or negative triggered +// Coder : Xifan Tang +//----------------------------------------------------- +`default_nettype wire + +module dsp (clk_i, rst_ni, a_i, b_i, d_i, out_o, mode_i, rst_acc, accsel, cas_g, overflow); + // Parameters that can pass through + parameter N_SIZE = 12; // Default parameter for N + parameter M_SIZE = 10; // Default parameter for M + // Local parameters + localparam A_WIDTH = 4 * N_SIZE; // Default parameter for a + localparam B_WIDTH = 4 * M_SIZE; // Default parameter for b + localparam C_WIDTH = N_SIZE + M_SIZE; // Default parameter for cin + localparam OUT_WIDTH = A_WIDTH / 2 + B_WIDTH / 2; // Default parameter for data output + + parameter P_SIZE = OUT_WIDTH; // Default parameter for previous d + + // Ensure that all the mode bit constants unique!!! + localparam MODE_BIT_CLK = 0; // Mode bit that controls polarity of the clock signals + localparam MODE_BIT_REGI_UPPER = 1; // Mode bit that controls the registering of upper part of the inputs + localparam MODE_BIT_REGI_LOWER = 2; // Mode bit that controls the registering of lower part of the inputs + localparam MODE_BIT_REGO_UPPER = 3; // Mode bit that controls the registering of upper part of the outputs + localparam MODE_BIT_REGO_LOWER = 4; // Mode bit that controls the registering of lower part of the outputs + localparam MODE_BIT_MAC_LSB = 5; // LSB of the mode bits that control the core computing units + localparam MODE_BIT_MAC_MSB = 8; // MSB of the mode bits that contorl the core computing units + localparam MODE_BIT_RST = 9; // MSB of the mode bits that contorl the polarity of reset signals + localparam MODE_BIT_SIGN = 10; //Mode bit that controls valid of the sign bit + // localparam MODE_BIT_CARRY = 11; //Mode bit that controls valid of the carry bit + localparam MODE_MUL_INPUT_REG = 11; // Mode bit that controls the registering of the inputs of the multipliers + localparam MODE_MUL_OUTPUT_REG = 12; // Mode bit that controls the registering of the outputs of the multipliers + + localparam ADDER_REDUNDENT = 8; // Default parameter for adder redundancy + localparam ADD_ACC_WIDTH = OUT_WIDTH/2 + ADDER_REDUNDENT; // Default accumulating parameter for adder width + localparam ACC_OUT_WIDTH = OUT_WIDTH + 2*ADDER_REDUNDENT; + + // Ports + input clk_i; + input rst_ni; + input [0:A_WIDTH-1] a_i; + input [0:B_WIDTH-1] b_i; + input [0:ACC_OUT_WIDTH-1] d_i; + output [0:ACC_OUT_WIDTH-1] out_o; + input [0:12] mode_i; + output overflow; + // input cin; + // output cout; + input rst_acc; //For accumulate resettable + input accsel; // Accumulate or add new data + input cas_g; // Global cascade mode for top level dsp + + + wire clk_core; + wire clr; + assign clk_core = mode_i[MODE_BIT_CLK] ? clk_i : ~clk_i; + assign clr = mode_i[MODE_BIT_RST] ? ~rst_ni : rst_ni; + + // Control logic for registering inputs and outputs + + wire [0:A_WIDTH-1] in_a; + wire [0:B_WIDTH-1] in_b; + wire [0:ACC_OUT_WIDTH-1] in_d; + wire [0:ACC_OUT_WIDTH-1] cas_out; + + reg [0:A_WIDTH-1] a_i_reg; + reg [0:B_WIDTH-1] b_i_reg; + reg [0:ACC_OUT_WIDTH-1] d_i_reg; + reg [0:ACC_OUT_WIDTH-1] out_o_reg; + + always @(posedge clk_core or negedge clr) begin + if (clr == 1'b0) begin + a_i_reg <= 0; + b_i_reg <= 0; + d_i_reg <= 0; + out_o_reg <= 0; + end else begin + a_i_reg <= a_i; + b_i_reg <= b_i; + d_i_reg <= d_i; + out_o_reg <= cas_out; + end + end + + assign in_a[0:A_WIDTH/2-1] = mode_i[MODE_BIT_REGI_LOWER] ? a_i_reg[0:A_WIDTH/2-1] : a_i[0:A_WIDTH/2-1]; + assign in_a[A_WIDTH/2:A_WIDTH-1] = mode_i[MODE_BIT_REGI_UPPER] ? a_i_reg[A_WIDTH/2:A_WIDTH-1] : a_i[A_WIDTH/2:A_WIDTH-1]; + assign in_b[0:B_WIDTH/2-1] = mode_i[MODE_BIT_REGI_LOWER] ? b_i_reg[0:B_WIDTH/2-1] : b_i[0:B_WIDTH/2-1]; + assign in_b[B_WIDTH/2:B_WIDTH-1] = mode_i[MODE_BIT_REGI_UPPER] ? b_i_reg[B_WIDTH/2:B_WIDTH-1] : b_i[B_WIDTH/2:B_WIDTH-1]; + assign in_d[0:ACC_OUT_WIDTH/2-1] = mode_i[MODE_BIT_REGI_LOWER] ? d_i_reg[0:ACC_OUT_WIDTH/2-1] : d_i[0:ACC_OUT_WIDTH/2-1]; + assign in_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] = mode_i[MODE_BIT_REGI_UPPER] ? d_i_reg[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] : d_i[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1]; + assign out_o[0:ACC_OUT_WIDTH/2-1] = mode_i[MODE_BIT_REGO_LOWER] ? out_o_reg[0:ACC_OUT_WIDTH/2-1] : cas_out[0:ACC_OUT_WIDTH/2-1]; + assign out_o[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] = mode_i[MODE_BIT_REGO_UPPER] ? out_o_reg[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] : cas_out[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1]; + + // Control logic for registering inputs and outputs of the multipliers + + wire [0:A_WIDTH-1] mac_a; + wire [0:B_WIDTH-1] mac_b; + wire [0:ACC_OUT_WIDTH-1] mac_d; + wire [0:ACC_OUT_WIDTH-1] mac_out; + + reg [0:A_WIDTH-1] in_a_reg; + reg [0:B_WIDTH-1] in_b_reg; + reg [0:ACC_OUT_WIDTH-1] in_d_reg; + + wire [0:ACC_OUT_WIDTH/2-1] mul_out_0; + wire [0:ACC_OUT_WIDTH/2-1] mul_out_1; + wire [0:ACC_OUT_WIDTH/2-1] mul_out_2; + wire [0:ACC_OUT_WIDTH/2-1] mul_out_3; + + reg [0:ACC_OUT_WIDTH/2-1] mul_out_0_reg; + reg [0:ACC_OUT_WIDTH/2-1] mul_out_1_reg; + reg [0:ACC_OUT_WIDTH/2-1] mul_out_2_reg; + reg [0:ACC_OUT_WIDTH/2-1] mul_out_3_reg; + + wire [0:ACC_OUT_WIDTH/2-1] q_o_0; + wire [0:ACC_OUT_WIDTH/2-1] q_o_1; + wire [0:ACC_OUT_WIDTH/2-1] q_o_2; + wire [0:ACC_OUT_WIDTH/2-1] q_o_3; + + always @(posedge clk_core or negedge clr) begin + if (clr == 1'b0) begin + in_a_reg <= 0; + in_b_reg <= 0; + in_d_reg <= 0; + mul_out_0_reg <= 0; + mul_out_1_reg <= 0; + mul_out_2_reg <= 0; + mul_out_3_reg <= 0; + end else begin + in_a_reg <= in_a; + in_b_reg <= in_b; + in_d_reg <= in_d; + mul_out_0_reg <= mul_out_0; + mul_out_1_reg <= mul_out_1; + mul_out_2_reg <= mul_out_2; + mul_out_3_reg <= mul_out_3; + end + end + + assign mac_a = mode_i[MODE_MUL_INPUT_REG] ? in_a_reg : in_a; + assign mac_b = mode_i[MODE_MUL_INPUT_REG] ? in_b_reg : in_b; + assign mac_d = mode_i[MODE_MUL_INPUT_REG] ? in_d_reg : in_d; + + assign q_o_0 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_0_reg : mul_out_0; + assign q_o_1 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_1_reg : mul_out_1; + assign q_o_2 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_2_reg : mul_out_2; + assign q_o_3 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_3_reg : mul_out_3; + + // Control logic around the core computing units + always @(*) begin + case (mode_i[MODE_BIT_MAC_LSB:MODE_BIT_MAC_MSB]) + 4'b0000: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + q_o_1; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2; + mac_out = q_o_3; + end + 4'b0001: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + mac_d[0:ACC_OUT_WIDTH/2-1]; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + mac_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1]; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2; + mac_out = {q_o_0, q_o_3}; + end + 4'b0010: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0; + mul_out_3 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1]; + mac_out = {q_o_1, q_o_2}; + end + 4'b0011: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + out_o_reg[0:ACC_OUT_WIDTH/2-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + out_o_reg[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1]; + mac_out = {q_o_0, q_o_1}; + end + 4'b0100: begin + mac_out = mac_a[0:A_WIDTH/2-1] * mac_b[0:B_WIDTH/2-1]; + end + 4'b0101: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + mac_d[0:ACC_OUT_WIDTH/2-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + mac_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1]; + mac_out = {q_o_0, q_o_1}; + end + 4'b0110: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1]; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1]; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1]; + mac_out = {q_o_0[0:ACC_OUT_WIDTH/4-1], q_o_1[0:ACC_OUT_WIDTH/4-1], q_o_2[0:ACC_OUT_WIDTH/4-1], q_o_3[0:ACC_OUT_WIDTH/4-1]}; + end + 4'b1000: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1]; + mac_out = {q_o_0, q_o_1}; + end + 4'b1001: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + mac_d[0:ACC_OUT_WIDTH/2-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + q_o_1; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2; + mac_out = {q_o_2, q_o_3}; + end + 4'b1010: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + q_o_1; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2; + mac_out = {q_o_1, q_o_3}; + end + 4'b1011: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1]; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2; + mac_out = {q_o_1, q_o_3}; + end + 4'b1101: begin + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + mac_d[0:ACC_OUT_WIDTH/2-1]; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + mac_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1]; + mac_out = {q_o_2, q_o_3}; + end + 4'b1110: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1]; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1]; + mac_out = {q_o_0, q_o_2[0:ACC_OUT_WIDTH/4-1], q_o_3[0:ACC_OUT_WIDTH/4-1]}; + end + default: begin + mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1]; + mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1]; + mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1]; + mac_out = {q_o_0, q_o_2[0:ACC_OUT_WIDTH/4-1], q_o_3[0:ACC_OUT_WIDTH/4-1]}; + end + endcase + end + + always @(*) begin + cas_out = cas_g ? mac_out + mac_d : mac_out; + end + +endmodule \ No newline at end of file diff --git a/techlibs/rapidflex/alkaidT/dff_map.v b/techlibs/rapidflex/alkaidT/dff_map.v new file mode 100644 index 000000000..f6d01a4ed --- /dev/null +++ b/techlibs/rapidflex/alkaidT/dff_map.v @@ -0,0 +1,177 @@ +// Rising edge DFF +module \$_DFF_P_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dff _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Rising edge DFF with async active-high reset +module \$_DFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Rising edge DFF with async active-high set +module \$_DFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Rising edge DFF with async active-low reset +module \$_DFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Rising edge DFF with async active-low set +module \$_DFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Rising edge DFF with sync active-high reset +module \$_SDFF_PP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Rising edge DFF with sync active-high set +module \$_SDFF_PP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffs _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Rising edge DFF with sync active-low reset +module \$_SDFF_PN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Rising edge DFF with sync active-low set +module \$_SDFF_PN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Falling edge DFF +module \$_DFF_N_ (D, C, Q); + input D; + input C; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C)); +endmodule + +// Falling edge DFF with async active-high reset +module \$_DFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Falling edge DFF with async active-high set +module \$_DFF_NP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Falling edge DFF with async active-low reset +module \$_DFF_NN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Falling edge DFF with async active-low set +module \$_DFF_NN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + dffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule + +// Falling edge DFF with sync active-high reset +module \$_SDFF_NP0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnr _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .R(R)); +endmodule + +// Falling edge DFF with sync active-high set +module \$_SDFF_NP1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffns _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .S(R)); +endmodule + +// Falling edge DFF with sync active-low reset +module \$_SDFF_NN0_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnrn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .RN(R)); +endmodule + +// Falling edge DFF with sync active-low set +module \$_SDFF_NN1_ (D, C, R, Q); + input D; + input C; + input R; + output Q; + parameter _TECHMAP_WIREINIT_Q_ = 1'bx; + sdffnsn _TECHMAP_REPLACE_ (.Q(Q), .D(D), .C(C), .SN(R)); +endmodule diff --git a/techlibs/rapidflex/alkaidT/dsp_map.v b/techlibs/rapidflex/alkaidT/dsp_map.v new file mode 100644 index 000000000..115649efc --- /dev/null +++ b/techlibs/rapidflex/alkaidT/dsp_map.v @@ -0,0 +1,35 @@ +module mult_24x20_map ( + input [0:23] A, + input [0:19] B, + output [0:43] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult24x20 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule + +module mult_12x10_map ( + input [0:11] A, + input [0:9] B, + output [0:21] Y +); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 0; + parameter B_WIDTH = 0; + parameter Y_WIDTH = 0; + + mult12x10 #() _TECHMAP_REPLACE_ ( + .A (A), + .B (B), + .Y (Y) ); + +endmodule diff --git a/techlibs/rapidflex/alkaidT/synth.ys b/techlibs/rapidflex/alkaidT/synth.ys new file mode 100644 index 000000000..d600a87f5 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/synth.ys @@ -0,0 +1,123 @@ +# Yosys synthesis script for ${TOP_MODULE} + +######################### +# Parse input files +######################### +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} +# Read technology library +read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} + +######################### +# Prepare for synthesis +######################### +# Identify top module from hierarchy +hierarchy -check -top ${TOP_MODULE} +# - Convert process blocks to AST +proc +# Flatten all the gates/primitives +flatten +# Identify tri-state buffers from 'z' signal in AST +# with follow-up optimizations to clean up AST +tribuf -logic +opt_expr +opt_clean +# demote inout ports to input or output port +# with follow-up optimizations to clean up AST +deminout +opt -nodffe + +opt_expr +opt_clean +check +opt -nodffe +wreduce -keepdc +peepopt +pmuxtree +opt_clean + +######################## +# Map multipliers +# Inspired from synth_xilinx.cc +######################### +# Avoid merging any registers into DSP, reserve memory port registers first +memory_dff +wreduce t:$mul +techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} +select a:mul2dsp +setattr -unset mul2dsp +opt_expr -fine +wreduce +select -clear +chtype -set $mul t:$__soft_mul # Extract arithmetic functions + +######################### +# Run coarse synthesis +######################### +# Run a tech map with default library +alumacc +opt +#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} +#share +#opt -nodffe +#fsm +# Run a quick follow-up optimization to sweep out unused nets/signals +#opt -fast -nodffe +# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells +memory -nomap +opt_clean + +######################### +# Map logics to BRAMs +######################### +memory_bram -rules ${YOSYS_BRAM_MAP_RULES} +techmap -map ${YOSYS_BRAM_MAP_VERILOG} +opt -fast -mux_undef -undriven -fine -nodffe +memory_map +opt -undriven -fine -nodffe + +######################## +# Map Adders +#techmap -map +/techmap.v -map ${YOSYS_ADDER_AVG_MAP_VERILOG} +opt -fast -nodffe +opt_expr +opt_merge +opt_clean +opt -nodffe + +######################### +# Map flip-flops +######################### +memory +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 +techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} +opt_expr -mux_undef +simplemap +opt_expr +opt_merge +opt_dff -nodffe +opt_clean +opt -nodffe + +######################### +# Map LUTs +######################### +abc -lut ${LUT_SIZE} +# Map dff again since ABC may generate some new FFs +techmap -map ${YOSYS_DFF_MAP_VERILOG} +techmap -map ${YOSYS_ADDER_MAP_VERILOG} + +######################### +# Check and show statisitics +######################### +hierarchy -check +stat + +######################### +# Output netlists +######################### +opt_clean -purge +write_blif ${OUTPUT_BLIF} +write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidT/verilog_rewrite.ys b/techlibs/rapidflex/alkaidT/verilog_rewrite.ys new file mode 100644 index 000000000..217e8d558 --- /dev/null +++ b/techlibs/rapidflex/alkaidT/verilog_rewrite.ys @@ -0,0 +1,41 @@ +# Yosys synthesis script for ${TOP_MODULE} +# Read verilog files +read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} + +# Technology mapping +hierarchy -top ${TOP_MODULE} +proc +techmap -D NO_LUT -map +/adff2dff.v + +# Synthesis +flatten +opt_expr +opt_clean +check +opt -nodffe -nosdff +fsm +opt -nodffe -nosdff +wreduce +peepopt +opt_clean +opt -nodffe -nosdff +memory -nomap +opt_clean +opt -fast -full -nodffe -nosdff +memory_map +opt -full -nodffe -nosdff +techmap +opt -fast -nodffe -nosdff +clean + +clean + +# LUT mapping +abc -lut ${LUT_SIZE} + +# Check +synth -run check + +# Clean and output blif +opt_clean -purge +write_verilog ${OUTPUT_VERILOG} diff --git a/techlibs/rapidflex/common/cells_sim.v b/techlibs/rapidflex/common/cells_sim.v new file mode 100644 index 000000000..95bc86be4 --- /dev/null +++ b/techlibs/rapidflex/common/cells_sim.v @@ -0,0 +1,53 @@ +// Copyright 2020-2022 F4PGA Authors +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +// SPDX-License-Identifier: Apache-2.0 + + +module inv ( + output Q, + input A +); + assign Q = A ? 0 : 1; +endmodule + +module buff ( + output Q, + input A +); + assign Q = A; +endmodule + +module logic_0 ( + output a +); + assign a = 0; +endmodule + +module logic_1 ( + output a +); + assign a = 1; +endmodule + +(* blackbox *) +module gclkbuff ( + input A, + output Z +); + + assign Z = A; + +endmodule + diff --git a/techlibs/rapidflex/src/clock_buffer_cmd.cc b/techlibs/rapidflex/src/clock_buffer_cmd.cc new file mode 100644 index 000000000..2deb9ee04 --- /dev/null +++ b/techlibs/rapidflex/src/clock_buffer_cmd.cc @@ -0,0 +1,553 @@ +#include +#include +#include +#include + +#include "backends/rtlil/rtlil_backend.h" +#include "kernel/celltypes.h" +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +#include "kernel/sigtools.h" +#include "kernel/yosys.h" +#include "pugixml.hpp" +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +struct InsertClockBuffer : public Pass { + InsertClockBuffer() + : Pass("insert_clock_buffer", + "This command is to insert clock buffer into the design") {} + + /*utility function used by insert_ckbuff; copied from blif.cc*/ + const std::string str(RTLIL::IdString id) { + std::string str = RTLIL::unescape_id(id); + for (size_t i = 0; i < str.size(); i++) + if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') + str[i] = '?'; + return str; + } + + /*utility function used by insert_ckbuff; copied from blif.cc*/ + const std::string str(RTLIL::SigBit sig) { + if (sig.wire == NULL) { + return "null"; + } + + std::string str = RTLIL::unescape_id(sig.wire->name); + for (size_t i = 0; i < str.size(); i++) + if (str[i] == '#' || str[i] == '=' || str[i] == '<' || str[i] == '>') + str[i] = '?'; + + if (sig.wire->width != 1) + str += + stringf("[%d]", sig.wire->upto ? sig.wire->start_offset + + sig.wire->width - sig.offset - 1 + : sig.wire->start_offset + sig.offset); + + return str; + } + + // eval_lut: Evaluate the output of a single LUT based on given input values + // Parameters: + // lut - Pointer to an RTLIL $lut cell + // inputs - map specifying the values of input signals + // (can provide only a subset of inputs) + // sigmap - SigMap, used to get the actual driving signal for each input + // Returns: + // Boolean output of the LUT (true/false) + bool eval_lut(const RTLIL::Cell *lut, std::map inputs, + const SigMap &sigmap) { + // Get the input vector of the LUT and map each signal to its actual driver + SigSpec lut_inputs = sigmap(lut->getPort(ID::A)); + + // Number of LUT inputs + int width = lut->getParam(ID::WIDTH).as_int(); + + // LUT truth table storing output for each input combination + Const lut_table = lut->getParam(ID::LUT); + + // Index into the LUT truth table + int lut_index = 0; + + // Iterate through each input bit + for (int i = 0; i < width; i++) { + // Get the i-th input signal and map it to its final driver + SigBit bit = sigmap(lut_inputs[i]); + + // Boolean value of the current input + bool value; + + // If the input value is provided by the user, use it + if (inputs.count(bit)) + value = inputs[bit]; + // Otherwise, use the signal's default or constant value + else + value = SigSpec(bit).as_bool(); + + // Accumulate this bit into the LUT index + // '<< i' places the value at the correct bit position + lut_index |= (value << i); + } + + // Lookup the LUT output for the computed index and return as bool + return lut_table.extract(lut_index).as_bool(); + } + + /* This function rewires subckt such as flip-flops (FFs) and pcounter that use + internally generated signals as their clock inputs. We can perform this + rewiring before connecting the new clock buffer (ckbuf), because the new wires + are added to the top module—not to the ckbuf itself. Therefore, once an + internally generated clock is detected, a new wire is created in the top + module and directly connected to the affected subckt. This rewiring process is + independent of the addition of the ckbuf. */ + void rewire_subckt(RTLIL::Module *module, RTLIL::Cell *cell, + RTLIL::IdString id_name, std::string C_input) { + std::string C_output = C_input + "_ckbuf"; + if (!module->wire("\\" + C_output)) { + auto output_wire = module->addWire("\\" + C_output, 1); + } + /* connect new ckbuf to the subckt */ + cell->unsetPort(id_name); // unsetPort("C") + cell->setPort(id_name, module->wire("\\" + C_output)); + cell->fixup_parameters(); + } + + /* This is a general-purpose function that works for all subcircuits (subckt). + It detects clock and reset signals and determines whether they are global. + If any global signal is detected, the function will rewire the subcircuit + accordingly. + */ + void process_cell(RTLIL::Module *module, RTLIL::Cell *cell, + std::map inputs, + std::vector clk_indicator_group, + std::vector reset_indicator_group, + std::set &ckbuf_info, + std::map &ckbuf_type) { + RTLIL::IdString clk_indicator; + for (auto clk : clk_indicator_group) { + if (cell->hasPort(clk)) { + clk_indicator = clk; + break; + } + } + + // dff could have reset signal with keywords R or RN. We shall determine + // which is the port name for current cell + RTLIL::IdString reset_indicator; + for (auto rst : reset_indicator_group) { + if (cell->hasPort(rst)) { + reset_indicator = rst; + break; + } + } + + if (reset_indicator.empty() && clk_indicator.empty()) { + return; + } + + bool global_clock = false; + bool global_reset = false; + for (auto &it : inputs) { + RTLIL::Wire *wire = it.second; + for (int i = 0; i < wire->width; i++) { + if (cell->hasPort(clk_indicator)) { + if (cell->getPort(clk_indicator) == RTLIL::SigSpec(wire, i)) { + global_clock = true; + continue; /*if the signal is global clock, then there is no need + to check whether it is global reset or not*/ + } + } + + if (cell->hasPort(reset_indicator)) { + if (cell->getPort(reset_indicator) == RTLIL::SigSpec(wire, i)) { + global_reset = true; + } + } + } + } + /*grab the information of the internally generated clocks*/ + if (!global_clock && cell->hasPort(clk_indicator)) { + std::string C_input = str(cell->getPort(clk_indicator)).c_str(); + ckbuf_info.insert(C_input); + ckbuf_type[C_input] = "clock"; + rewire_subckt(module, cell, clk_indicator, C_input); + } + /*grab the information of the internally generated resets*/ + if (!global_reset && cell->hasPort(reset_indicator)) { + std::string C_input = str(cell->getPort(reset_indicator)).c_str(); + ckbuf_info.insert(C_input); + ckbuf_type[C_input] = "reset"; + rewire_subckt(module, cell, reset_indicator, C_input); + } + } + + /* This function examines sequential logic and returns a set of strings + representing internally generated signals. When such a signal is found, it + invokes rewire_subckt.*/ + std::set + find_internal_clk_r_signal(RTLIL::Module *module, RTLIL::Design *design, + std::map &ckbuf_type) { + std::set ckbuf_info; + /*get input ports of the top module*/ + std::map inputs, outputs; + for (auto wire : module->wires()) { + if (wire->port_input) + inputs[wire->port_id] = wire; + } + for (auto cell : module->cells()) { + /*Bypass yosys internal cells $lut which doesn't have clock signal */ + if ((cell->type) == ID($lut)) { + continue; + } else { + /*check whether the C port is internally generated clock signal or not*/ + std::vector clk_indicator_group = {ID(C), ID(clk_i)}; + std::vector reset_indicator_group = {ID(RN), ID(R), + ID(rst_i)}; + process_cell(module, cell, inputs, clk_indicator_group, + reset_indicator_group, ckbuf_info, ckbuf_type); + } + } + return ckbuf_info; + } + + /* insert .subckt ckbuf for each internally generated clock or reset signal */ + void insert_ckbuf(RTLIL::Module *module, + const std::set &ckbuf_info) { + for (const std::string &ckbuf : ckbuf_info) { + RTLIL::Cell *ckbuf_cell = + module->addCell(stringf("$ckbuf$%s", ckbuf.c_str()), "\\ckbuf"); + ckbuf_cell->setPort("\\in", module->wire("\\" + ckbuf)); + ckbuf_cell->setPort("\\out", module->wire("\\" + ckbuf + "_ckbuf")); + ckbuf_cell->set_src_attribute(""); + } + } + + /*This function is for generating cell map file*/ + void generate_cell_map(const char *fname, + const std::set &ckbuf_info, + const std::map &ckbuf_type) { + pugi::xml_document out_xml; + pugi::xml_node root_node = out_xml.append_child("ckbuf_cell_map"); + for (const std::string &ckbuf : ckbuf_info) { + std::string in = ckbuf; + std::string out = ckbuf + "_ckbuf"; + std::string type; + + auto it = ckbuf_type.find(ckbuf); + if (it != ckbuf_type.end()) { + type = it->second; + } else { + log_error("No port type defined for ckbuf %s \n", out.c_str()); + } + + pugi::xml_node ckbuf_node = root_node.append_child("ckbuf"); + ckbuf_node.append_attribute("input_net") = in.c_str(); + ckbuf_node.append_attribute("cell") = out.c_str(); + ckbuf_node.append_attribute("type") = type.c_str(); + } + out_xml.save_file(fname); + log("cell map is stored in file %s \n", fname); + } + void rewire_lut_primitive(RTLIL::Cell *cell, + const std::vector &sig, + const RTLIL::Const &new_lut, int new_width) { + cell->unsetPort(ID::A); + cell->setPort(ID::A, sig); + + // Update LUT parameters + cell->parameters[ID::LUT] = new_lut; // Set new truth table + cell->parameters[ID::WIDTH] = new_width; + cell->fixup_parameters(); + } + + void process_cell_rewire_lut( + RTLIL::Module *module, RTLIL::Cell *cell, + const std::map> + &internal_signal_io_map, + const std::map &internal_signal_lut, + const Yosys::SigMap &sigmap) { + std::set sig; + /* sig and ordered_sig contain the same signals. + * sig is used to store the rewired signals and avoid duplicates, + * while ordered_sig preserves the signal order so it stays aligned + * with the truth table information. + */ + std::vector ordered_sig; + std::map> sig_replace_port_map; + std::map sig_replace_cell_map; + std::set temp_sig; + std::set lut_inputs = cell->getPort(ID::A).to_sigbit_set(); + std::vector lut_inputs_vector = + cell->getPort(ID::A).to_sigbit_vector(); + std::set common_port_all; + std::vector replaced_boolean_value; + std::vector remained_boolean_value; + bool rewire_required = false; + std::vector old_lut = + cell->parameters.at(ID::LUT).bits(); // Original LUT truth table + for (const auto &[internal_signal_output, internal_signal_input] : + internal_signal_io_map) { + std::set common_port; + std::string mapped_ckbuf_name; + if (std::includes(lut_inputs.begin(), lut_inputs.end(), + internal_signal_input.begin(), + internal_signal_input.end())) { + std::set_intersection(lut_inputs.begin(), lut_inputs.end(), + internal_signal_input.begin(), + internal_signal_input.end(), + std::inserter(common_port, common_port.end())); + std::string C_output = internal_signal_output + "_ckbuf"; + mapped_ckbuf_name = internal_signal_output; + if (!module->wire("\\" + C_output)) { + log("wire %s is not defined", C_output.c_str()); + } + auto replaced_sig = module->wire("\\" + C_output); + if (sig.find(replaced_sig) != sig.end()) { + /* element has already been recorded*/ + log("signal %s has been replaced!\n", C_output.c_str()); + continue; + } + sig.insert(replaced_sig); + if (std::find(ordered_sig.begin(), ordered_sig.end(), replaced_sig) == + ordered_sig.end()) { + ordered_sig.push_back(replaced_sig); + } + sig_replace_port_map[replaced_sig] = common_port; + auto src_cell = internal_signal_lut.at(mapped_ckbuf_name); + sig_replace_cell_map[replaced_sig] = src_cell; + rewire_required = true; + common_port_all.insert(common_port.begin(), common_port.end()); + } + } + + if (rewire_required) { + // For example, the following lut will be rewired + // .names a b internal_clock1 + // .names a b c out + // as + // .names internal_clock1_ckbuf c out + // where internal_clock1 is the original internal signals and + // internal_clock1_ckbuf is the outputs of ckbuf. (.subckt ckbuf + // internal_clock1 internal_clock1_ckbuf) + // we need to update the truth table of .names internal_clock1_ckbuf + // c out concurrently + /* The first step is to get the original truth table, i.e. the truth + * table of .names a b c d out */ + int bit_width = lut_inputs_vector.size(); + std::vector> original_truth_table; + std::map sig_index_map; + + for (size_t index = 0; index < lut_inputs_vector.size(); index++) { + sig_index_map[lut_inputs_vector[index]] = index; + } + + for (int index = 0; index < old_lut.size(); index++) { + if (old_lut[index] == RTLIL::State::S1) { + std::vector bits(bit_width, false); + for (int b = 0; b < bit_width; b++) { + bits[b] = (index >> b) & 1; + } + original_truth_table.push_back(bits); + } + } + + /* get remained sigs */ + std::set_difference(lut_inputs.begin(), lut_inputs.end(), + common_port_all.begin(), common_port_all.end(), + std::inserter(temp_sig, temp_sig.end())); + + std::vector> modified_bit; + + for (const auto &line : original_truth_table) { + std::vector remained_bit; + /* get sigs that can be replaced by ckbuf and evaluate its truth + * table values and updates the final truth table*/ + for (auto replaced_sig : sig) { + const RTLIL::Cell *cell_temp = + module->cell(sig_replace_cell_map[replaced_sig]); + auto ports = sig_replace_port_map[replaced_sig]; + + std::map common_port_map; + for (auto port : ports) { + common_port_map[port] = line[sig_index_map[port]]; + } + + bool changed_bit = eval_lut(cell_temp, common_port_map, sigmap); + remained_bit.push_back(changed_bit); + } + /* get remained sigs and use previous truth table values*/ + for (auto port : temp_sig) { + remained_bit.push_back(line[sig_index_map[port]]); + } + + modified_bit.push_back(remained_bit); + } + /* get the final truth table of the rewired lut such as .names + * internal_clock1_ckbuf c out */ + std::vector modified_bit_int; + for (const auto &line : modified_bit) { + int value = 0; + for (size_t i = 0; i < line.size(); i++) { + if (line[i]) { + value |= (1 << i); + } + } + modified_bit_int.push_back(value); + } + + sig.insert(temp_sig.begin(), temp_sig.end()); + ordered_sig.insert(ordered_sig.end(), temp_sig.begin(), temp_sig.end()); + + int new_width = sig.size(); + int num_entries = 1 << new_width; + RTLIL::Const new_lut(num_entries); + /*initialize lut value to 0*/ + for (int i = 0; i < num_entries; i++) { + new_lut.bits()[i] = RTLIL::State::S0; + } + /* assign final truth table's info to current cell */ + for (int i : modified_bit_int) { + new_lut.bits()[i] = RTLIL::State::S1; + } + + rewire_lut_primitive(cell, ordered_sig, new_lut, new_width); + module->fixup_ports(); + std::set lut_outputs = + cell->getPort(ID::Y).to_sigbit_set(); + } + } + /* This function rewires luts which have internally generated signals as its + * input*/ + void rewire_luts(RTLIL::Module *module, + const std::set &ckbuf_info) { + /* find the lut that has internally generated clock as an output and get its + * io map */ + Yosys::SigMap sigmap(module); + std::map> internal_signal_io_map; + std::map internal_signal_lut; + std::set flattened_io_map; + /*the first for loop constructs the map between internall signal name and + its corresponding fan-ins For example, consider the following netlist: + .names a b internal_clock1 + .names c d internal_clock2 + The internal_signal_io_map stores key-value pairs from all luts like this: + [internal_clock1, {a, b}], [internal_clock2, {c, d}]. + */ + for (const auto cell : module->cells()) { + if ((cell->type) == ID($lut)) { + auto &inputs = cell->getPort(ID::A); + std::string output = str(cell->getPort(ID::Y)); + auto width = cell->parameters.at(ID::WIDTH).as_int(); + log_assert(inputs.size() == width); + if (ckbuf_info.find(output) != ckbuf_info.end()) { + /* We assume that all LUT cells are explicitly named before the + current pass. Anonymous cells indicate an unexpected state after + techmapping and are treated as a fatal error. */ + if (cell->name.empty()) { + log_error("cell->name is empty for output=%s\n", output.c_str()); + } + auto io_set = inputs.to_sigbit_set(); + internal_signal_io_map[output] = io_set; + internal_signal_lut[output] = cell->name.c_str(); + flattened_io_map.insert(internal_signal_io_map[output].begin(), + internal_signal_io_map[output].end()); + continue; + } + } + } + + /* This for loop does two things: + 1. detect logic that can be replaced by internal signals + For example, consider the following netlist: + .names a b internal_clock1 + .names c d internal_clock2 + The internal_signal_io_map stores key-value pairs from all luts like + this: [internal_clock1, {a, b}], [internal_clock2, {c, d}]. When we + encounter a netlist like: .names a b c d out we can replace it with .names + internal_clock1 internal_clock2 out + + 2. rewire luts + For example, the following lut will be rewired + .names internal_clock1 internal_clock2 out + as + .names internal_clock1_ckbuf internal_clock2_ckbuf out_ckbuf + where internal_clock1/2 are the original internal signals and + internal_clock1_ckbuf/2_ckbuf are the outputs of ckbuf. (.subckt ckbuf + internal_clock1 internal_clock1_ckbuf) + */ + for (auto cell : module->cells()) { + if ((cell->type) == ID($lut)) { + std::string output = str(cell->getPort(ID::Y)); + if (ckbuf_info.find(output) != ckbuf_info.end()) { + continue; /*by pass the luts that generate internal clk/reset */ + } else { + process_cell_rewire_lut(module, cell, internal_signal_io_map, + internal_signal_lut, sigmap); + /*replace internal clk/reset with clk/reset_buf signal */ + } + } + } + } + + void execute(std::vector args, RTLIL::Design *design) override { + log("Arguments to the command insert_clock_buffer:\n"); + std::string top_module_name; + std::string cell_map_file; + for (size_t i = 0; i < args.size(); i++) { + log(" %s\n", args[i].c_str()); + + if (args[i] == "-top" && i + 1 < args.size()) { + top_module_name = args[i + 1]; + } else if (args[i] == "-cell_map_file" && i + 1 < args.size()) { + cell_map_file = args[i + 1]; + } + } + + if (cell_map_file.empty()) { + cell_map_file = "cell_map.xml"; + } + log("cell map location is %s \n", cell_map_file.c_str()); + + /*if top_module_name is empty, get it from design*/ + if (top_module_name.empty()) + for (auto module : design->modules()) + if (module->get_bool_attribute(ID::top)) + top_module_name = module->name.str(); + + if (top_module_name.empty()) { + log_error("No top module detected. Insert clock buffer failed."); + } else { + log("Top module in current design: %s \n", top_module_name.c_str()); + } + + /*Insert clock buffer into the top module*/ + design->sort(); + for (auto module : design->modules()) { + /*only insert buffer to top module*/ + if (module->name == RTLIL::escape_id(top_module_name)) { + std::map ckbuf_type; + std::set ckbuf_info = + find_internal_clk_r_signal(module, design, ckbuf_type); + /*insert ckbuf and rewire dff */ + insert_ckbuf(module, ckbuf_info); + + module->fixup_ports(); + /*rewire luts */ + rewire_luts(module, ckbuf_info); + + module->fixup_ports(); + /* print out cells */ + if (!ckbuf_info.empty()) { + generate_cell_map(cell_map_file.c_str(), ckbuf_info, ckbuf_type); + } else { + log("Ckbuf info is empty. No cell map file will be generated! \n"); + } + break; + } + } + design->check(); + } +} Insert_clock_buffer; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/rapidflex/src/pugixml.cpp b/techlibs/rapidflex/src/pugixml.cpp new file mode 100644 index 000000000..15cad0fd1 --- /dev/null +++ b/techlibs/rapidflex/src/pugixml.cpp @@ -0,0 +1,12313 @@ +/** + * pugixml parser - version 1.7 + * -------------------------------------------------------- + * Copyright (C) 2006-2015, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com) + * Report bugs and download new versions at http://pugixml.org/ + * + * This library is distributed under the MIT License. See notice at the end + * of this file. + * + * This work is based on the pugxml parser, which is: + * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net) + */ + +#ifndef SOURCE_PUGIXML_CPP +#define SOURCE_PUGIXML_CPP + +#include "pugixml.hpp" + +#include +#include +#include +#include +#include + +#ifdef PUGIXML_WCHAR_MODE +#include +#endif + +#ifndef PUGIXML_NO_XPATH +#include +#include +#ifdef PUGIXML_NO_EXCEPTIONS +#include +#endif +#endif + +#ifndef PUGIXML_NO_STL +#include +#include +#include +#endif + +// For placement new +#include + +#ifdef _MSC_VER +#pragma warning(push) +#pragma warning(disable : 4127) // conditional expression is constant +#pragma warning( \ + disable : 4324) // structure was padded due to __declspec(align()) +#pragma warning(disable : 4611) // interaction between '_setjmp' and C++ object + // destruction is non-portable +#pragma warning(disable : 4702) // unreachable code +#pragma warning(disable : 4996) // this function or variable may be unsafe +#pragma warning(disable : 4793) // function compiled as native: presence of + // '_setjmp' makes a function unmanaged +#endif + +#ifdef __INTEL_COMPILER +#pragma warning(disable : 177) // function was declared but never referenced +#pragma warning(disable : 279) // controlling expression is constant +#pragma warning(disable : 1478 1786) // function was declared "deprecated" +#pragma warning( \ + disable : 1684) // conversion from pointer to same-sized integral type +#endif + +#if defined(__BORLANDC__) && defined(PUGIXML_HEADER_ONLY) +#pragma warn - 8080 // symbol is declared but never used; disabling this inside + // push/pop bracket does not make the warning go away +#endif + +#ifdef __BORLANDC__ +#pragma option push +#pragma warn - 8008 // condition is always false +#pragma warn - 8066 // unreachable code +#endif + +#ifdef __SNC__ +// Using diag_push/diag_pop does not disable the warnings inside templates due +// to a compiler bug +#pragma diag_suppress = 178 // function was declared but never referenced +#pragma diag_suppress = 237 // controlling expression is constant +#endif + +// Inlining controls +#if defined(_MSC_VER) && _MSC_VER >= 1300 +#define PUGI__NO_INLINE __declspec(noinline) +#elif defined(__GNUC__) +#define PUGI__NO_INLINE __attribute__((noinline)) +#else +#define PUGI__NO_INLINE +#endif + +// Branch weight controls +#if defined(__GNUC__) +#define PUGI__UNLIKELY(cond) __builtin_expect(cond, 0) +#else +#define PUGI__UNLIKELY(cond) (cond) +#endif + +// Simple static assertion +#define PUGI__STATIC_ASSERT(cond) \ + { \ + static const char condition_failed[(cond) ? 1 : -1] = {0}; \ + (void)condition_failed[0]; \ + } + +// Digital Mars C++ bug workaround for passing char loaded from memory via stack +#ifdef __DMC__ +#define PUGI__DMC_VOLATILE volatile +#else +#define PUGI__DMC_VOLATILE +#endif + +// Borland C++ bug workaround for not defining ::memcpy depending on header +// include order (can't always use std::memcpy because some compilers don't have +// it at all) +#if defined(__BORLANDC__) && !defined(__MEM_H_USING_LIST) +using std::memcpy; +using std::memmove; +using std::memset; +#endif + +// In some environments MSVC is a compiler but the CRT lacks certain +// MSVC-specific features +#if defined(_MSC_VER) && !defined(__S3E__) +#define PUGI__MSVC_CRT_VERSION _MSC_VER +#endif + +#ifdef PUGIXML_HEADER_ONLY +#define PUGI__NS_BEGIN \ + namespace pugi { \ + namespace impl { +#define PUGI__NS_END \ + } \ + } +#define PUGI__FN inline +#define PUGI__FN_NO_INLINE inline +#else +#if defined(_MSC_VER) && \ + _MSC_VER < 1300 // MSVC6 seems to have an amusing bug with anonymous + // namespaces inside namespaces +#define PUGI__NS_BEGIN \ + namespace pugi { \ + namespace impl { +#define PUGI__NS_END \ + } \ + } +#else +#define PUGI__NS_BEGIN \ + namespace pugi { \ + namespace impl { \ + namespace { +#define PUGI__NS_END \ + } \ + } \ + } +#endif +#define PUGI__FN +#define PUGI__FN_NO_INLINE PUGI__NO_INLINE +#endif + +// uintptr_t +#if !defined(_MSC_VER) || _MSC_VER >= 1600 +#include +#else +namespace pugi { +#ifndef _UINTPTR_T_DEFINED +typedef size_t uintptr_t; +#endif + +typedef unsigned __int8 uint8_t; +typedef unsigned __int16 uint16_t; +typedef unsigned __int32 uint32_t; +} // namespace pugi +#endif + +// Memory allocation +PUGI__NS_BEGIN +PUGI__FN void *default_allocate(size_t size) { return malloc(size); } + +PUGI__FN void default_deallocate(void *ptr) { free(ptr); } + +template struct xml_memory_management_function_storage { + static allocation_function allocate; + static deallocation_function deallocate; +}; + +// Global allocation functions are stored in class statics so that in header +// mode linker deduplicates them Without a template<> we'll get multiple +// definitions of the same static +template +allocation_function xml_memory_management_function_storage::allocate = + default_allocate; +template +deallocation_function xml_memory_management_function_storage::deallocate = + default_deallocate; + +typedef xml_memory_management_function_storage xml_memory; +PUGI__NS_END + +// String utilities +PUGI__NS_BEGIN +// Get string length +PUGI__FN size_t strlength(const char_t *s) { + assert(s); + +#ifdef PUGIXML_WCHAR_MODE + return wcslen(s); +#else + return strlen(s); +#endif +} + +// Compare two strings +PUGI__FN bool strequal(const char_t *src, const char_t *dst) { + assert(src && dst); + +#ifdef PUGIXML_WCHAR_MODE + return wcscmp(src, dst) == 0; +#else + return strcmp(src, dst) == 0; +#endif +} + +// Compare lhs with [rhs_begin, rhs_end) +PUGI__FN bool strequalrange(const char_t *lhs, const char_t *rhs, + size_t count) { + for (size_t i = 0; i < count; ++i) + if (lhs[i] != rhs[i]) + return false; + + return lhs[count] == 0; +} + +// Get length of wide string, even if CRT lacks wide character support +PUGI__FN size_t strlength_wide(const wchar_t *s) { + assert(s); + +#ifdef PUGIXML_WCHAR_MODE + return wcslen(s); +#else + const wchar_t *end = s; + while (*end) + end++; + return static_cast(end - s); +#endif +} +PUGI__NS_END + +// auto_ptr-like object for exception recovery +PUGI__NS_BEGIN +template struct auto_deleter { + T *data; + D deleter; + + auto_deleter(T *data_, D deleter_) : data(data_), deleter(deleter_) {} + + ~auto_deleter() { + if (data) + deleter(data); + } + + T *release() { + T *result = data; + data = 0; + return result; + } +}; +PUGI__NS_END + +#ifdef PUGIXML_COMPACT +PUGI__NS_BEGIN +class compact_hash_table { +public: + compact_hash_table() : _items(0), _capacity(0), _count(0) {} + + void clear() { + if (_items) { + xml_memory::deallocate(_items); + _items = 0; + _capacity = 0; + _count = 0; + } + } + + void **find(const void *key) { + assert(key); + + if (_capacity == 0) + return 0; + + size_t hashmod = _capacity - 1; + size_t bucket = hash(key) & hashmod; + + for (size_t probe = 0; probe <= hashmod; ++probe) { + item_t &probe_item = _items[bucket]; + + if (probe_item.key == key) + return &probe_item.value; + + if (probe_item.key == 0) + return 0; + + // hash collision, quadratic probing + bucket = (bucket + probe + 1) & hashmod; + } + + assert(!"Hash table is full"); + return 0; + } + + void **insert(const void *key) { + assert(key); + assert(_capacity != 0 && _count < _capacity - _capacity / 4); + + size_t hashmod = _capacity - 1; + size_t bucket = hash(key) & hashmod; + + for (size_t probe = 0; probe <= hashmod; ++probe) { + item_t &probe_item = _items[bucket]; + + if (probe_item.key == 0) { + probe_item.key = key; + _count++; + return &probe_item.value; + } + + if (probe_item.key == key) + return &probe_item.value; + + // hash collision, quadratic probing + bucket = (bucket + probe + 1) & hashmod; + } + + assert(!"Hash table is full"); + return 0; + } + + bool reserve() { + if (_count + 16 >= _capacity - _capacity / 4) + return rehash(); + + return true; + } + +private: + struct item_t { + const void *key; + void *value; + }; + + item_t *_items; + size_t _capacity; + + size_t _count; + + bool rehash(); + + static unsigned int hash(const void *key) { + unsigned int h = + static_cast(reinterpret_cast(key)); + + // MurmurHash3 32-bit finalizer + h ^= h >> 16; + h *= 0x85ebca6bu; + h ^= h >> 13; + h *= 0xc2b2ae35u; + h ^= h >> 16; + + return h; + } +}; + +PUGI__FN_NO_INLINE bool compact_hash_table::rehash() { + compact_hash_table rt; + rt._capacity = (_capacity == 0) ? 32 : _capacity * 2; + rt._items = static_cast( + xml_memory::allocate(sizeof(item_t) * rt._capacity)); + + if (!rt._items) + return false; + + memset(rt._items, 0, sizeof(item_t) * rt._capacity); + + for (size_t i = 0; i < _capacity; ++i) + if (_items[i].key) + *rt.insert(_items[i].key) = _items[i].value; + + if (_items) + xml_memory::deallocate(_items); + + _capacity = rt._capacity; + _items = rt._items; + + assert(_count == rt._count); + + return true; +} + +PUGI__NS_END +#endif + +PUGI__NS_BEGIN +static const size_t xml_memory_page_size = +#ifdef PUGIXML_MEMORY_PAGE_SIZE + PUGIXML_MEMORY_PAGE_SIZE +#else + 32768 +#endif + ; + +#ifdef PUGIXML_COMPACT +static const uintptr_t xml_memory_block_alignment = 4; + +static const uintptr_t xml_memory_page_alignment = sizeof(void *); +#else +static const uintptr_t xml_memory_block_alignment = sizeof(void *); + +static const uintptr_t xml_memory_page_alignment = 64; +static const uintptr_t xml_memory_page_pointer_mask = + ~(xml_memory_page_alignment - 1); +#endif + +// extra metadata bits +static const uintptr_t xml_memory_page_contents_shared_mask = 32; +static const uintptr_t xml_memory_page_name_allocated_mask = 16; +static const uintptr_t xml_memory_page_value_allocated_mask = 8; +static const uintptr_t xml_memory_page_type_mask = 7; + +// combined masks for string uniqueness +static const uintptr_t xml_memory_page_name_allocated_or_shared_mask = + xml_memory_page_name_allocated_mask | xml_memory_page_contents_shared_mask; +static const uintptr_t xml_memory_page_value_allocated_or_shared_mask = + xml_memory_page_value_allocated_mask | xml_memory_page_contents_shared_mask; + +#ifdef PUGIXML_COMPACT +#define PUGI__GETPAGE_IMPL(header) (header).get_page() +#else +#define PUGI__GETPAGE_IMPL(header) \ + reinterpret_cast( \ + (header)&impl::xml_memory_page_pointer_mask) +#endif + +#define PUGI__GETPAGE(n) PUGI__GETPAGE_IMPL((n)->header) +#define PUGI__NODETYPE(n) \ + static_cast(((n)->header & impl::xml_memory_page_type_mask) + \ + 1) + +struct xml_allocator; + +struct xml_memory_page { + static xml_memory_page *construct(void *memory) { + xml_memory_page *result = static_cast(memory); + + result->allocator = 0; + result->prev = 0; + result->next = 0; + result->busy_size = 0; + result->freed_size = 0; + +#ifdef PUGIXML_COMPACT + result->compact_string_base = 0; + result->compact_shared_parent = 0; + result->compact_page_marker = 0; +#endif + + return result; + } + + xml_allocator *allocator; + + xml_memory_page *prev; + xml_memory_page *next; + + size_t busy_size; + size_t freed_size; + +#ifdef PUGIXML_COMPACT + char_t *compact_string_base; + void *compact_shared_parent; + uint32_t *compact_page_marker; +#endif +}; + +struct xml_memory_string_header { + uint16_t page_offset; // offset from page->data + uint16_t full_size; // 0 if string occupies whole page +}; + +struct xml_allocator { + xml_allocator(xml_memory_page *root) + : _root(root), _busy_size(root->busy_size) { +#ifdef PUGIXML_COMPACT + _hash = 0; +#endif + } + + xml_memory_page *allocate_page(size_t data_size) { + size_t size = sizeof(xml_memory_page) + data_size; + + // allocate block with some alignment, leaving memory for worst-case padding + void *memory = xml_memory::allocate(size + xml_memory_page_alignment); + if (!memory) + return 0; + + // align to next page boundary (note: this guarantees at least 1 usable byte + // before the page) + char *page_memory = reinterpret_cast( + (reinterpret_cast(memory) + xml_memory_page_alignment) & + ~(xml_memory_page_alignment - 1)); + + // prepare page structure + xml_memory_page *page = xml_memory_page::construct(page_memory); + assert(page); + + page->allocator = _root->allocator; + + // record the offset for freeing the memory block + assert(page_memory > memory && + page_memory - static_cast(memory) <= 127); + page_memory[-1] = + static_cast(page_memory - static_cast(memory)); + + return page; + } + + static void deallocate_page(xml_memory_page *page) { + char *page_memory = reinterpret_cast(page); + + xml_memory::deallocate(page_memory - page_memory[-1]); + } + + void *allocate_memory_oob(size_t size, xml_memory_page *&out_page); + + void *allocate_memory(size_t size, xml_memory_page *&out_page) { + if (PUGI__UNLIKELY(_busy_size + size > xml_memory_page_size)) + return allocate_memory_oob(size, out_page); + + void *buf = + reinterpret_cast(_root) + sizeof(xml_memory_page) + _busy_size; + + _busy_size += size; + + out_page = _root; + + return buf; + } + +#ifdef PUGIXML_COMPACT + void *allocate_object(size_t size, xml_memory_page *&out_page) { + void *result = allocate_memory(size + sizeof(uint32_t), out_page); + if (!result) + return 0; + + // adjust for marker + ptrdiff_t offset = static_cast(result) - + reinterpret_cast(out_page->compact_page_marker); + + if (PUGI__UNLIKELY(static_cast(offset) >= + 256 * xml_memory_block_alignment)) { + // insert new marker + uint32_t *marker = static_cast(result); + + *marker = static_cast(reinterpret_cast(marker) - + reinterpret_cast(out_page)); + out_page->compact_page_marker = marker; + + // since we don't reuse the page space until we reallocate it, we can just + // pretend that we freed the marker block this will make sure + // deallocate_memory correctly tracks the size + out_page->freed_size += sizeof(uint32_t); + + return marker + 1; + } else { + // roll back uint32_t part + _busy_size -= sizeof(uint32_t); + + return result; + } + } +#else + void *allocate_object(size_t size, xml_memory_page *&out_page) { + return allocate_memory(size, out_page); + } +#endif + + void deallocate_memory(void *ptr, size_t size, xml_memory_page *page) { + if (page == _root) + page->busy_size = _busy_size; + + assert(ptr >= reinterpret_cast(page) + sizeof(xml_memory_page) && + ptr < reinterpret_cast(page) + sizeof(xml_memory_page) + + page->busy_size); + (void)!ptr; + + page->freed_size += size; + assert(page->freed_size <= page->busy_size); + + if (page->freed_size == page->busy_size) { + if (page->next == 0) { + assert(_root == page); + + // top page freed, just reset sizes + page->busy_size = 0; + page->freed_size = 0; + +#ifdef PUGIXML_COMPACT + // reset compact state to maximize efficiency + page->compact_string_base = 0; + page->compact_shared_parent = 0; + page->compact_page_marker = 0; +#endif + + _busy_size = 0; + } else { + assert(_root != page); + assert(page->prev); + + // remove from the list + page->prev->next = page->next; + page->next->prev = page->prev; + + // deallocate + deallocate_page(page); + } + } + } + + char_t *allocate_string(size_t length) { + static const size_t max_encoded_offset = + (1 << 16) * xml_memory_block_alignment; + + PUGI__STATIC_ASSERT(xml_memory_page_size <= max_encoded_offset); + + // allocate memory for string and header block + size_t size = sizeof(xml_memory_string_header) + length * sizeof(char_t); + + // round size up to block alignment boundary + size_t full_size = (size + (xml_memory_block_alignment - 1)) & + ~(xml_memory_block_alignment - 1); + + xml_memory_page *page; + xml_memory_string_header *header = static_cast( + allocate_memory(full_size, page)); + + if (!header) + return 0; + + // setup header + ptrdiff_t page_offset = reinterpret_cast(header) - + reinterpret_cast(page) - + sizeof(xml_memory_page); + + assert(page_offset % xml_memory_block_alignment == 0); + assert(page_offset >= 0 && + static_cast(page_offset) < max_encoded_offset); + header->page_offset = static_cast( + static_cast(page_offset) / xml_memory_block_alignment); + + // full_size == 0 for large strings that occupy the whole page + assert(full_size % xml_memory_block_alignment == 0); + assert(full_size < max_encoded_offset || + (page->busy_size == full_size && page_offset == 0)); + header->full_size = static_cast( + full_size < max_encoded_offset ? full_size / xml_memory_block_alignment + : 0); + + // round-trip through void* to avoid 'cast increases required alignment of + // target type' warning header is guaranteed a pointer-sized alignment, + // which should be enough for char_t + return static_cast(static_cast(header + 1)); + } + + void deallocate_string(char_t *string) { + // this function casts pointers through void* to avoid 'cast increases + // required alignment of target type' warnings we're guaranteed the proper + // (pointer-sized) alignment on the input string if it was allocated via + // allocate_string + + // get header + xml_memory_string_header *header = + static_cast(static_cast(string)) - + 1; + assert(header); + + // deallocate + size_t page_offset = sizeof(xml_memory_page) + + header->page_offset * xml_memory_block_alignment; + xml_memory_page *page = reinterpret_cast( + static_cast(reinterpret_cast(header) - page_offset)); + + // if full_size == 0 then this string occupies the whole page + size_t full_size = header->full_size == 0 + ? page->busy_size + : header->full_size * xml_memory_block_alignment; + + deallocate_memory(header, full_size, page); + } + + bool reserve() { +#ifdef PUGIXML_COMPACT + return _hash->reserve(); +#else + return true; +#endif + } + + xml_memory_page *_root; + size_t _busy_size; + +#ifdef PUGIXML_COMPACT + compact_hash_table *_hash; +#endif +}; + +PUGI__FN_NO_INLINE void * +xml_allocator::allocate_memory_oob(size_t size, xml_memory_page *&out_page) { + const size_t large_allocation_threshold = xml_memory_page_size / 4; + + xml_memory_page *page = allocate_page( + size <= large_allocation_threshold ? xml_memory_page_size : size); + out_page = page; + + if (!page) + return 0; + + if (size <= large_allocation_threshold) { + _root->busy_size = _busy_size; + + // insert page at the end of linked list + page->prev = _root; + _root->next = page; + _root = page; + + _busy_size = size; + } else { + // insert page before the end of linked list, so that it is deleted as soon + // as possible the last page is not deleted even if it's empty (see + // deallocate_memory) + assert(_root->prev); + + page->prev = _root->prev; + page->next = _root; + + _root->prev->next = page; + _root->prev = page; + + page->busy_size = size; + } + + return reinterpret_cast(page) + sizeof(xml_memory_page); +} +PUGI__NS_END + +#ifdef PUGIXML_COMPACT +PUGI__NS_BEGIN +static const uintptr_t compact_alignment_log2 = 2; +static const uintptr_t compact_alignment = 1 << compact_alignment_log2; + +class compact_header { +public: + compact_header(xml_memory_page *page, unsigned int flags) { + PUGI__STATIC_ASSERT(xml_memory_block_alignment == compact_alignment); + + ptrdiff_t offset = (reinterpret_cast(this) - + reinterpret_cast(page->compact_page_marker)); + assert(offset % compact_alignment == 0 && + static_cast(offset) < 256 * compact_alignment); + + _page = static_cast(offset >> compact_alignment_log2); + _flags = static_cast(flags); + } + + void operator&=(uintptr_t mod) { _flags &= static_cast(mod); } + + void operator|=(uintptr_t mod) { _flags |= static_cast(mod); } + + uintptr_t operator&(uintptr_t mod) const { return _flags & mod; } + + xml_memory_page *get_page() const { + // round-trip through void* to silence 'cast increases required alignment of + // target type' warnings + const char *page_marker = reinterpret_cast(this) - + (_page << compact_alignment_log2); + const char *page = + page_marker - *reinterpret_cast( + static_cast(page_marker)); + + return const_cast( + reinterpret_cast( + static_cast(page))); + } + +private: + unsigned char _page; + unsigned char _flags; +}; + +PUGI__FN xml_memory_page *compact_get_page(const void *object, + int header_offset) { + const compact_header *header = reinterpret_cast( + static_cast(object) - header_offset); + + return header->get_page(); +} + +template +PUGI__FN_NO_INLINE T *compact_get_value(const void *object) { + return static_cast( + *compact_get_page(object, header_offset)->allocator->_hash->find(object)); +} + +template +PUGI__FN_NO_INLINE void compact_set_value(const void *object, T *value) { + *compact_get_page(object, header_offset)->allocator->_hash->insert(object) = + value; +} + +template +class compact_pointer { +public: + compact_pointer() : _data(0) {} + + void operator=(const compact_pointer &rhs) { *this = rhs + 0; } + + void operator=(T *value) { + if (value) { + // value is guaranteed to be compact-aligned; 'this' is not + // our decoding is based on 'this' aligned to compact alignment downwards + // (see operator T*) so for negative offsets (e.g. -3) we need to adjust + // the diff by compact_alignment - 1 to compensate for arithmetic shift + // rounding for negative values + ptrdiff_t diff = + reinterpret_cast(value) - reinterpret_cast(this); + ptrdiff_t offset = + ((diff + int(compact_alignment - 1)) >> compact_alignment_log2) - + start; + + if (static_cast(offset) <= 253) + _data = static_cast(offset + 1); + else { + compact_set_value(this, value); + + _data = 255; + } + } else + _data = 0; + } + + operator T *() const { + if (_data) { + if (_data < 255) { + uintptr_t base = + reinterpret_cast(this) & ~(compact_alignment - 1); + + return reinterpret_cast( + base + ((_data - 1 + start) << compact_alignment_log2)); + } else + return compact_get_value(this); + } else + return 0; + } + + T *operator->() const { return *this; } + +private: + unsigned char _data; +}; + +template class compact_pointer_parent { +public: + compact_pointer_parent() : _data(0) {} + + void operator=(const compact_pointer_parent &rhs) { *this = rhs + 0; } + + void operator=(T *value) { + if (value) { + // value is guaranteed to be compact-aligned; 'this' is not + // our decoding is based on 'this' aligned to compact alignment downwards + // (see operator T*) so for negative offsets (e.g. -3) we need to adjust + // the diff by compact_alignment - 1 to compensate for arithmetic shift + // behavior for negative values + ptrdiff_t diff = + reinterpret_cast(value) - reinterpret_cast(this); + ptrdiff_t offset = + ((diff + int(compact_alignment - 1)) >> compact_alignment_log2) + + 65533; + + if (static_cast(offset) <= 65533) { + _data = static_cast(offset + 1); + } else { + xml_memory_page *page = compact_get_page(this, header_offset); + + if (PUGI__UNLIKELY(page->compact_shared_parent == 0)) + page->compact_shared_parent = value; + + if (page->compact_shared_parent == value) { + _data = 65534; + } else { + compact_set_value(this, value); + + _data = 65535; + } + } + } else { + _data = 0; + } + } + + operator T *() const { + if (_data) { + if (_data < 65534) { + uintptr_t base = + reinterpret_cast(this) & ~(compact_alignment - 1); + + return reinterpret_cast( + base + ((_data - 1 - 65533) << compact_alignment_log2)); + } else if (_data == 65534) + return static_cast( + compact_get_page(this, header_offset)->compact_shared_parent); + else + return compact_get_value(this); + } else + return 0; + } + + T *operator->() const { return *this; } + +private: + uint16_t _data; +}; + +template class compact_string { +public: + compact_string() : _data(0) {} + + void operator=(const compact_string &rhs) { *this = rhs + 0; } + + void operator=(char_t *value) { + if (value) { + xml_memory_page *page = compact_get_page(this, header_offset); + + if (PUGI__UNLIKELY(page->compact_string_base == 0)) + page->compact_string_base = value; + + ptrdiff_t offset = value - page->compact_string_base; + + if (static_cast(offset) < (65535 << 7)) { + // round-trip through void* to silence 'cast increases required + // alignment of target type' warnings + uint16_t *base = reinterpret_cast( + static_cast(reinterpret_cast(this) - base_offset)); + + if (*base == 0) { + *base = static_cast((offset >> 7) + 1); + _data = static_cast((offset & 127) + 1); + } else { + ptrdiff_t remainder = offset - ((*base - 1) << 7); + + if (static_cast(remainder) <= 253) { + _data = static_cast(remainder + 1); + } else { + compact_set_value(this, value); + + _data = 255; + } + } + } else { + compact_set_value(this, value); + + _data = 255; + } + } else { + _data = 0; + } + } + + operator char_t *() const { + if (_data) { + if (_data < 255) { + xml_memory_page *page = compact_get_page(this, header_offset); + + // round-trip through void* to silence 'cast increases required + // alignment of target type' warnings + const uint16_t *base = + reinterpret_cast(static_cast( + reinterpret_cast(this) - base_offset)); + assert(*base); + + ptrdiff_t offset = ((*base - 1) << 7) + (_data - 1); + + return page->compact_string_base + offset; + } else { + return compact_get_value(this); + } + } else + return 0; + } + +private: + unsigned char _data; +}; +PUGI__NS_END +#endif + +#ifdef PUGIXML_COMPACT +namespace pugi { +struct xml_attribute_struct { + xml_attribute_struct(impl::xml_memory_page *page) + : header(page, 0), namevalue_base(0) { + PUGI__STATIC_ASSERT(sizeof(xml_attribute_struct) == 8); + } + + impl::compact_header header; + + uint16_t namevalue_base; + + impl::compact_string<4, 2> name; + impl::compact_string<5, 3> value; + + impl::compact_pointer prev_attribute_c; + impl::compact_pointer next_attribute; +}; + +struct xml_node_struct { + xml_node_struct(impl::xml_memory_page *page, xml_node_type type) + : header(page, type - 1), namevalue_base(0) { + PUGI__STATIC_ASSERT(sizeof(xml_node_struct) == 12); + } + + impl::compact_header header; + + uint16_t namevalue_base; + + impl::compact_string<4, 2> name; + impl::compact_string<5, 3> value; + + impl::compact_pointer_parent parent; + + impl::compact_pointer first_child; + + impl::compact_pointer prev_sibling_c; + impl::compact_pointer next_sibling; + + impl::compact_pointer first_attribute; +}; +} // namespace pugi +#else +namespace pugi { +struct xml_attribute_struct { + xml_attribute_struct(impl::xml_memory_page *page) + : header(reinterpret_cast(page)), name(0), value(0), + prev_attribute_c(0), next_attribute(0) {} + + uintptr_t header; + + char_t *name; + char_t *value; + + xml_attribute_struct *prev_attribute_c; + xml_attribute_struct *next_attribute; +}; + +struct xml_node_struct { + xml_node_struct(impl::xml_memory_page *page, xml_node_type type) + : header(reinterpret_cast(page) | (type - 1)), name(0), + value(0), parent(0), first_child(0), prev_sibling_c(0), next_sibling(0), + first_attribute(0) {} + + uintptr_t header; + + char_t *name; + char_t *value; + + xml_node_struct *parent; + + xml_node_struct *first_child; + + xml_node_struct *prev_sibling_c; + xml_node_struct *next_sibling; + + xml_attribute_struct *first_attribute; +}; +} // namespace pugi +#endif + +PUGI__NS_BEGIN +struct xml_extra_buffer { + char_t *buffer; + xml_extra_buffer *next; +}; + +struct xml_document_struct : public xml_node_struct, public xml_allocator { + xml_document_struct(xml_memory_page *page) + : xml_node_struct(page, node_document), xml_allocator(page), buffer(0), + extra_buffers(0) { +#ifdef PUGIXML_COMPACT + _hash = &hash; +#endif + } + + const char_t *buffer; + + xml_extra_buffer *extra_buffers; + +#ifdef PUGIXML_COMPACT + compact_hash_table hash; +#endif +}; + +template +inline xml_allocator &get_allocator(const Object *object) { + assert(object); + + return *PUGI__GETPAGE(object)->allocator; +} + +template +inline xml_document_struct &get_document(const Object *object) { + assert(object); + + return *static_cast(PUGI__GETPAGE(object)->allocator); +} +PUGI__NS_END + +// Low-level DOM operations +PUGI__NS_BEGIN +inline xml_attribute_struct *allocate_attribute(xml_allocator &alloc) { + xml_memory_page *page; + void *memory = alloc.allocate_object(sizeof(xml_attribute_struct), page); + if (!memory) + return 0; + + return new (memory) xml_attribute_struct(page); +} + +inline xml_node_struct *allocate_node(xml_allocator &alloc, + xml_node_type type) { + xml_memory_page *page; + void *memory = alloc.allocate_object(sizeof(xml_node_struct), page); + if (!memory) + return 0; + + return new (memory) xml_node_struct(page, type); +} + +inline void destroy_attribute(xml_attribute_struct *a, xml_allocator &alloc) { + if (a->header & impl::xml_memory_page_name_allocated_mask) + alloc.deallocate_string(a->name); + + if (a->header & impl::xml_memory_page_value_allocated_mask) + alloc.deallocate_string(a->value); + + alloc.deallocate_memory(a, sizeof(xml_attribute_struct), PUGI__GETPAGE(a)); +} + +inline void destroy_node(xml_node_struct *n, xml_allocator &alloc) { + if (n->header & impl::xml_memory_page_name_allocated_mask) + alloc.deallocate_string(n->name); + + if (n->header & impl::xml_memory_page_value_allocated_mask) + alloc.deallocate_string(n->value); + + for (xml_attribute_struct *attr = n->first_attribute; attr;) { + xml_attribute_struct *next = attr->next_attribute; + + destroy_attribute(attr, alloc); + + attr = next; + } + + for (xml_node_struct *child = n->first_child; child;) { + xml_node_struct *next = child->next_sibling; + + destroy_node(child, alloc); + + child = next; + } + + alloc.deallocate_memory(n, sizeof(xml_node_struct), PUGI__GETPAGE(n)); +} + +inline void append_node(xml_node_struct *child, xml_node_struct *node) { + child->parent = node; + + xml_node_struct *head = node->first_child; + + if (head) { + xml_node_struct *tail = head->prev_sibling_c; + + tail->next_sibling = child; + child->prev_sibling_c = tail; + head->prev_sibling_c = child; + } else { + node->first_child = child; + child->prev_sibling_c = child; + } +} + +inline void prepend_node(xml_node_struct *child, xml_node_struct *node) { + child->parent = node; + + xml_node_struct *head = node->first_child; + + if (head) { + child->prev_sibling_c = head->prev_sibling_c; + head->prev_sibling_c = child; + } else + child->prev_sibling_c = child; + + child->next_sibling = head; + node->first_child = child; +} + +inline void insert_node_after(xml_node_struct *child, xml_node_struct *node) { + xml_node_struct *parent = node->parent; + + child->parent = parent; + + if (node->next_sibling) + node->next_sibling->prev_sibling_c = child; + else + parent->first_child->prev_sibling_c = child; + + child->next_sibling = node->next_sibling; + child->prev_sibling_c = node; + + node->next_sibling = child; +} + +inline void insert_node_before(xml_node_struct *child, xml_node_struct *node) { + xml_node_struct *parent = node->parent; + + child->parent = parent; + + if (node->prev_sibling_c->next_sibling) + node->prev_sibling_c->next_sibling = child; + else + parent->first_child = child; + + child->prev_sibling_c = node->prev_sibling_c; + child->next_sibling = node; + + node->prev_sibling_c = child; +} + +inline void remove_node(xml_node_struct *node) { + xml_node_struct *parent = node->parent; + + if (node->next_sibling) + node->next_sibling->prev_sibling_c = node->prev_sibling_c; + else + parent->first_child->prev_sibling_c = node->prev_sibling_c; + + if (node->prev_sibling_c->next_sibling) + node->prev_sibling_c->next_sibling = node->next_sibling; + else + parent->first_child = node->next_sibling; + + node->parent = 0; + node->prev_sibling_c = 0; + node->next_sibling = 0; +} + +inline void append_attribute(xml_attribute_struct *attr, + xml_node_struct *node) { + xml_attribute_struct *head = node->first_attribute; + + if (head) { + xml_attribute_struct *tail = head->prev_attribute_c; + + tail->next_attribute = attr; + attr->prev_attribute_c = tail; + head->prev_attribute_c = attr; + } else { + node->first_attribute = attr; + attr->prev_attribute_c = attr; + } +} + +inline void prepend_attribute(xml_attribute_struct *attr, + xml_node_struct *node) { + xml_attribute_struct *head = node->first_attribute; + + if (head) { + attr->prev_attribute_c = head->prev_attribute_c; + head->prev_attribute_c = attr; + } else + attr->prev_attribute_c = attr; + + attr->next_attribute = head; + node->first_attribute = attr; +} + +inline void insert_attribute_after(xml_attribute_struct *attr, + xml_attribute_struct *place, + xml_node_struct *node) { + if (place->next_attribute) + place->next_attribute->prev_attribute_c = attr; + else + node->first_attribute->prev_attribute_c = attr; + + attr->next_attribute = place->next_attribute; + attr->prev_attribute_c = place; + place->next_attribute = attr; +} + +inline void insert_attribute_before(xml_attribute_struct *attr, + xml_attribute_struct *place, + xml_node_struct *node) { + if (place->prev_attribute_c->next_attribute) + place->prev_attribute_c->next_attribute = attr; + else + node->first_attribute = attr; + + attr->prev_attribute_c = place->prev_attribute_c; + attr->next_attribute = place; + place->prev_attribute_c = attr; +} + +inline void remove_attribute(xml_attribute_struct *attr, + xml_node_struct *node) { + if (attr->next_attribute) + attr->next_attribute->prev_attribute_c = attr->prev_attribute_c; + else + node->first_attribute->prev_attribute_c = attr->prev_attribute_c; + + if (attr->prev_attribute_c->next_attribute) + attr->prev_attribute_c->next_attribute = attr->next_attribute; + else + node->first_attribute = attr->next_attribute; + + attr->prev_attribute_c = 0; + attr->next_attribute = 0; +} + +PUGI__FN_NO_INLINE xml_node_struct * +append_new_node(xml_node_struct *node, xml_allocator &alloc, + xml_node_type type = node_element) { + if (!alloc.reserve()) + return 0; + + xml_node_struct *child = allocate_node(alloc, type); + if (!child) + return 0; + + append_node(child, node); + + return child; +} + +PUGI__FN_NO_INLINE xml_attribute_struct * +append_new_attribute(xml_node_struct *node, xml_allocator &alloc) { + if (!alloc.reserve()) + return 0; + + xml_attribute_struct *attr = allocate_attribute(alloc); + if (!attr) + return 0; + + append_attribute(attr, node); + + return attr; +} +PUGI__NS_END + +// Helper classes for code generation +PUGI__NS_BEGIN +struct opt_false { + enum { value = 0 }; +}; + +struct opt_true { + enum { value = 1 }; +}; +PUGI__NS_END + +// Unicode utilities +PUGI__NS_BEGIN +inline uint16_t endian_swap(uint16_t value) { + return static_cast(((value & 0xff) << 8) | (value >> 8)); +} + +inline uint32_t endian_swap(uint32_t value) { + return ((value & 0xff) << 24) | ((value & 0xff00) << 8) | + ((value & 0xff0000) >> 8) | (value >> 24); +} + +struct utf8_counter { + typedef size_t value_type; + + static value_type low(value_type result, uint32_t ch) { + // U+0000..U+007F + if (ch < 0x80) + return result + 1; + // U+0080..U+07FF + else if (ch < 0x800) + return result + 2; + // U+0800..U+FFFF + else + return result + 3; + } + + static value_type high(value_type result, uint32_t) { + // U+10000..U+10FFFF + return result + 4; + } +}; + +struct utf8_writer { + typedef uint8_t *value_type; + + static value_type low(value_type result, uint32_t ch) { + // U+0000..U+007F + if (ch < 0x80) { + *result = static_cast(ch); + return result + 1; + } + // U+0080..U+07FF + else if (ch < 0x800) { + result[0] = static_cast(0xC0 | (ch >> 6)); + result[1] = static_cast(0x80 | (ch & 0x3F)); + return result + 2; + } + // U+0800..U+FFFF + else { + result[0] = static_cast(0xE0 | (ch >> 12)); + result[1] = static_cast(0x80 | ((ch >> 6) & 0x3F)); + result[2] = static_cast(0x80 | (ch & 0x3F)); + return result + 3; + } + } + + static value_type high(value_type result, uint32_t ch) { + // U+10000..U+10FFFF + result[0] = static_cast(0xF0 | (ch >> 18)); + result[1] = static_cast(0x80 | ((ch >> 12) & 0x3F)); + result[2] = static_cast(0x80 | ((ch >> 6) & 0x3F)); + result[3] = static_cast(0x80 | (ch & 0x3F)); + return result + 4; + } + + static value_type any(value_type result, uint32_t ch) { + return (ch < 0x10000) ? low(result, ch) : high(result, ch); + } +}; + +struct utf16_counter { + typedef size_t value_type; + + static value_type low(value_type result, uint32_t) { return result + 1; } + + static value_type high(value_type result, uint32_t) { return result + 2; } +}; + +struct utf16_writer { + typedef uint16_t *value_type; + + static value_type low(value_type result, uint32_t ch) { + *result = static_cast(ch); + + return result + 1; + } + + static value_type high(value_type result, uint32_t ch) { + uint32_t msh = static_cast(ch - 0x10000) >> 10; + uint32_t lsh = static_cast(ch - 0x10000) & 0x3ff; + + result[0] = static_cast(0xD800 + msh); + result[1] = static_cast(0xDC00 + lsh); + + return result + 2; + } + + static value_type any(value_type result, uint32_t ch) { + return (ch < 0x10000) ? low(result, ch) : high(result, ch); + } +}; + +struct utf32_counter { + typedef size_t value_type; + + static value_type low(value_type result, uint32_t) { return result + 1; } + + static value_type high(value_type result, uint32_t) { return result + 1; } +}; + +struct utf32_writer { + typedef uint32_t *value_type; + + static value_type low(value_type result, uint32_t ch) { + *result = ch; + + return result + 1; + } + + static value_type high(value_type result, uint32_t ch) { + *result = ch; + + return result + 1; + } + + static value_type any(value_type result, uint32_t ch) { + *result = ch; + + return result + 1; + } +}; + +struct latin1_writer { + typedef uint8_t *value_type; + + static value_type low(value_type result, uint32_t ch) { + *result = static_cast(ch > 255 ? '?' : ch); + + return result + 1; + } + + static value_type high(value_type result, uint32_t ch) { + (void)ch; + + *result = '?'; + + return result + 1; + } +}; + +struct utf8_decoder { + typedef uint8_t type; + + template + static inline typename Traits::value_type + process(const uint8_t *data, size_t size, typename Traits::value_type result, + Traits) { + const uint8_t utf8_byte_mask = 0x3f; + + while (size) { + uint8_t lead = *data; + + // 0xxxxxxx -> U+0000..U+007F + if (lead < 0x80) { + result = Traits::low(result, lead); + data += 1; + size -= 1; + + // process aligned single-byte (ascii) blocks + if ((reinterpret_cast(data) & 3) == 0) { + // round-trip through void* to silence 'cast increases required + // alignment of target type' warnings + while (size >= 4 && (*static_cast( + static_cast(data)) & + 0x80808080) == 0) { + result = Traits::low(result, data[0]); + result = Traits::low(result, data[1]); + result = Traits::low(result, data[2]); + result = Traits::low(result, data[3]); + data += 4; + size -= 4; + } + } + } + // 110xxxxx -> U+0080..U+07FF + else if (static_cast(lead - 0xC0) < 0x20 && size >= 2 && + (data[1] & 0xc0) == 0x80) { + result = Traits::low(result, ((lead & ~0xC0) << 6) | + (data[1] & utf8_byte_mask)); + data += 2; + size -= 2; + } + // 1110xxxx -> U+0800-U+FFFF + else if (static_cast(lead - 0xE0) < 0x10 && size >= 3 && + (data[1] & 0xc0) == 0x80 && (data[2] & 0xc0) == 0x80) { + result = Traits::low(result, ((lead & ~0xE0) << 12) | + ((data[1] & utf8_byte_mask) << 6) | + (data[2] & utf8_byte_mask)); + data += 3; + size -= 3; + } + // 11110xxx -> U+10000..U+10FFFF + else if (static_cast(lead - 0xF0) < 0x08 && size >= 4 && + (data[1] & 0xc0) == 0x80 && (data[2] & 0xc0) == 0x80 && + (data[3] & 0xc0) == 0x80) { + result = Traits::high(result, ((lead & ~0xF0) << 18) | + ((data[1] & utf8_byte_mask) << 12) | + ((data[2] & utf8_byte_mask) << 6) | + (data[3] & utf8_byte_mask)); + data += 4; + size -= 4; + } + // 10xxxxxx or 11111xxx -> invalid + else { + data += 1; + size -= 1; + } + } + + return result; + } +}; + +template struct utf16_decoder { + typedef uint16_t type; + + template + static inline typename Traits::value_type + process(const uint16_t *data, size_t size, typename Traits::value_type result, + Traits) { + while (size) { + uint16_t lead = opt_swap::value ? endian_swap(*data) : *data; + + // U+0000..U+D7FF + if (lead < 0xD800) { + result = Traits::low(result, lead); + data += 1; + size -= 1; + } + // U+E000..U+FFFF + else if (static_cast(lead - 0xE000) < 0x2000) { + result = Traits::low(result, lead); + data += 1; + size -= 1; + } + // surrogate pair lead + else if (static_cast(lead - 0xD800) < 0x400 && size >= 2) { + uint16_t next = opt_swap::value ? endian_swap(data[1]) : data[1]; + + if (static_cast(next - 0xDC00) < 0x400) { + result = Traits::high(result, 0x10000 + ((lead & 0x3ff) << 10) + + (next & 0x3ff)); + data += 2; + size -= 2; + } else { + data += 1; + size -= 1; + } + } else { + data += 1; + size -= 1; + } + } + + return result; + } +}; + +template struct utf32_decoder { + typedef uint32_t type; + + template + static inline typename Traits::value_type + process(const uint32_t *data, size_t size, typename Traits::value_type result, + Traits) { + while (size) { + uint32_t lead = opt_swap::value ? endian_swap(*data) : *data; + + // U+0000..U+FFFF + if (lead < 0x10000) { + result = Traits::low(result, lead); + data += 1; + size -= 1; + } + // U+10000..U+10FFFF + else { + result = Traits::high(result, lead); + data += 1; + size -= 1; + } + } + + return result; + } +}; + +struct latin1_decoder { + typedef uint8_t type; + + template + static inline typename Traits::value_type + process(const uint8_t *data, size_t size, typename Traits::value_type result, + Traits) { + while (size) { + result = Traits::low(result, *data); + data += 1; + size -= 1; + } + + return result; + } +}; + +template struct wchar_selector; + +template <> struct wchar_selector<2> { + typedef uint16_t type; + typedef utf16_counter counter; + typedef utf16_writer writer; + typedef utf16_decoder decoder; +}; + +template <> struct wchar_selector<4> { + typedef uint32_t type; + typedef utf32_counter counter; + typedef utf32_writer writer; + typedef utf32_decoder decoder; +}; + +typedef wchar_selector::counter wchar_counter; +typedef wchar_selector::writer wchar_writer; + +struct wchar_decoder { + typedef wchar_t type; + + template + static inline typename Traits::value_type + process(const wchar_t *data, size_t size, typename Traits::value_type result, + Traits traits) { + typedef wchar_selector::decoder decoder; + + return decoder::process( + reinterpret_cast(data), size, result, + traits); + } +}; + +#ifdef PUGIXML_WCHAR_MODE +PUGI__FN void convert_wchar_endian_swap(wchar_t *result, const wchar_t *data, + size_t length) { + for (size_t i = 0; i < length; ++i) + result[i] = static_cast(endian_swap( + static_cast::type>(data[i]))); +} +#endif +PUGI__NS_END + +PUGI__NS_BEGIN +enum chartype_t { + ct_parse_pcdata = 1, // \0, &, \r, < + ct_parse_attr = 2, // \0, &, \r, ', " + ct_parse_attr_ws = 4, // \0, &, \r, ', ", \n, tab + ct_space = 8, // \r, \n, space, tab + ct_parse_cdata = 16, // \0, ], >, \r + ct_parse_comment = 32, // \0, -, >, \r + ct_symbol = 64, // Any symbol > 127, a-z, A-Z, 0-9, _, :, -, . + ct_start_symbol = 128 // Any symbol > 127, a-z, A-Z, _, : +}; + +static const unsigned char chartype_table[256] = { + 55, 0, 0, 0, 0, 0, 0, 0, 0, 12, 12, 0, 0, 63, + 0, 0, // 0-15 + 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, + 0, 0, // 16-31 + 8, 0, 6, 0, 0, 0, 7, 6, 0, 0, 0, 0, 0, 96, + 64, 0, // 32-47 + 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 192, 0, 1, 0, + 48, 0, // 48-63 + 0, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, // 64-79 + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 0, 0, 16, + 0, 192, // 80-95 + 0, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, // 96-111 + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 0, 0, 0, + 0, 0, // 112-127 + + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, // 128+ + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, + 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192}; + +enum chartypex_t { + ctx_special_pcdata = + 1, // Any symbol >= 0 and < 32 (except \t, \r, \n), &, <, > + ctx_special_attr = 2, // Any symbol >= 0 and < 32 (except \t), &, <, >, " + ctx_start_symbol = 4, // Any symbol > 127, a-z, A-Z, _ + ctx_digit = 8, // 0-9 + ctx_symbol = 16 // Any symbol > 127, a-z, A-Z, 0-9, _, -, . +}; + +static const unsigned char chartypex_table[256] = { + 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 2, 3, 3, // 0-15 + 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 16-31 + 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 16, 16, 0, // 32-47 + 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 0, 0, 3, 0, 3, 0, // 48-63 + + 0, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, // 64-79 + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 0, 0, 0, 0, 20, // 80-95 + 0, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, // 96-111 + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 0, 0, 0, 0, 0, // 112-127 + + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, // 128+ + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, + 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; + +#ifdef PUGIXML_WCHAR_MODE +#define PUGI__IS_CHARTYPE_IMPL(c, ct, table) \ + ((static_cast(c) < 128 ? table[static_cast(c)] \ + : table[128]) & \ + (ct)) +#else +#define PUGI__IS_CHARTYPE_IMPL(c, ct, table) \ + (table[static_cast(c)] & (ct)) +#endif + +#define PUGI__IS_CHARTYPE(c, ct) PUGI__IS_CHARTYPE_IMPL(c, ct, chartype_table) +#define PUGI__IS_CHARTYPEX(c, ct) PUGI__IS_CHARTYPE_IMPL(c, ct, chartypex_table) + +PUGI__FN bool is_little_endian() { + unsigned int ui = 1; + + return *reinterpret_cast(&ui) == 1; +} + +PUGI__FN xml_encoding get_wchar_encoding() { + PUGI__STATIC_ASSERT(sizeof(wchar_t) == 2 || sizeof(wchar_t) == 4); + + if (sizeof(wchar_t) == 2) + return is_little_endian() ? encoding_utf16_le : encoding_utf16_be; + else + return is_little_endian() ? encoding_utf32_le : encoding_utf32_be; +} + +PUGI__FN xml_encoding guess_buffer_encoding(uint8_t d0, uint8_t d1, uint8_t d2, + uint8_t d3) { + // look for BOM in first few bytes + if (d0 == 0 && d1 == 0 && d2 == 0xfe && d3 == 0xff) + return encoding_utf32_be; + if (d0 == 0xff && d1 == 0xfe && d2 == 0 && d3 == 0) + return encoding_utf32_le; + if (d0 == 0xfe && d1 == 0xff) + return encoding_utf16_be; + if (d0 == 0xff && d1 == 0xfe) + return encoding_utf16_le; + if (d0 == 0xef && d1 == 0xbb && d2 == 0xbf) + return encoding_utf8; + + // look for <, (contents); + + PUGI__DMC_VOLATILE uint8_t d0 = data[0], d1 = data[1], d2 = data[2], + d3 = data[3]; + + return guess_buffer_encoding(d0, d1, d2, d3); +} + +PUGI__FN bool get_mutable_buffer(char_t *&out_buffer, size_t &out_length, + const void *contents, size_t size, + bool is_mutable) { + size_t length = size / sizeof(char_t); + + if (is_mutable) { + out_buffer = static_cast(const_cast(contents)); + out_length = length; + } else { + char_t *buffer = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!buffer) + return false; + + if (contents) + memcpy(buffer, contents, length * sizeof(char_t)); + else + assert(length == 0); + + buffer[length] = 0; + + out_buffer = buffer; + out_length = length + 1; + } + + return true; +} + +#ifdef PUGIXML_WCHAR_MODE +PUGI__FN bool need_endian_swap_utf(xml_encoding le, xml_encoding re) { + return (le == encoding_utf16_be && re == encoding_utf16_le) || + (le == encoding_utf16_le && re == encoding_utf16_be) || + (le == encoding_utf32_be && re == encoding_utf32_le) || + (le == encoding_utf32_le && re == encoding_utf32_be); +} + +PUGI__FN bool convert_buffer_endian_swap(char_t *&out_buffer, + size_t &out_length, + const void *contents, size_t size, + bool is_mutable) { + const char_t *data = static_cast(contents); + size_t length = size / sizeof(char_t); + + if (is_mutable) { + char_t *buffer = const_cast(data); + + convert_wchar_endian_swap(buffer, data, length); + + out_buffer = buffer; + out_length = length; + } else { + char_t *buffer = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!buffer) + return false; + + convert_wchar_endian_swap(buffer, data, length); + buffer[length] = 0; + + out_buffer = buffer; + out_length = length + 1; + } + + return true; +} + +template +PUGI__FN bool convert_buffer_generic(char_t *&out_buffer, size_t &out_length, + const void *contents, size_t size, D) { + const typename D::type *data = + static_cast(contents); + size_t data_length = size / sizeof(typename D::type); + + // first pass: get length in wchar_t units + size_t length = D::process(data, data_length, 0, wchar_counter()); + + // allocate buffer of suitable length + char_t *buffer = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!buffer) + return false; + + // second pass: convert utf16 input to wchar_t + wchar_writer::value_type obegin = + reinterpret_cast(buffer); + wchar_writer::value_type oend = + D::process(data, data_length, obegin, wchar_writer()); + + assert(oend == obegin + length); + *oend = 0; + + out_buffer = buffer; + out_length = length + 1; + + return true; +} + +PUGI__FN bool convert_buffer(char_t *&out_buffer, size_t &out_length, + xml_encoding encoding, const void *contents, + size_t size, bool is_mutable) { + // get native encoding + xml_encoding wchar_encoding = get_wchar_encoding(); + + // fast path: no conversion required + if (encoding == wchar_encoding) + return get_mutable_buffer(out_buffer, out_length, contents, size, + is_mutable); + + // only endian-swapping is required + if (need_endian_swap_utf(encoding, wchar_encoding)) + return convert_buffer_endian_swap(out_buffer, out_length, contents, size, + is_mutable); + + // source encoding is utf8 + if (encoding == encoding_utf8) + return convert_buffer_generic(out_buffer, out_length, contents, size, + utf8_decoder()); + + // source encoding is utf16 + if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf16_le : encoding_utf16_be; + + return (native_encoding == encoding) + ? convert_buffer_generic(out_buffer, out_length, contents, size, + utf16_decoder()) + : convert_buffer_generic(out_buffer, out_length, contents, size, + utf16_decoder()); + } + + // source encoding is utf32 + if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf32_le : encoding_utf32_be; + + return (native_encoding == encoding) + ? convert_buffer_generic(out_buffer, out_length, contents, size, + utf32_decoder()) + : convert_buffer_generic(out_buffer, out_length, contents, size, + utf32_decoder()); + } + + // source encoding is latin1 + if (encoding == encoding_latin1) + return convert_buffer_generic(out_buffer, out_length, contents, size, + latin1_decoder()); + + assert(!"Invalid encoding"); + return false; +} +#else +template +PUGI__FN bool convert_buffer_generic(char_t *&out_buffer, size_t &out_length, + const void *contents, size_t size, D) { + const typename D::type *data = + static_cast(contents); + size_t data_length = size / sizeof(typename D::type); + + // first pass: get length in utf8 units + size_t length = D::process(data, data_length, 0, utf8_counter()); + + // allocate buffer of suitable length + char_t *buffer = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!buffer) + return false; + + // second pass: convert utf16 input to utf8 + uint8_t *obegin = reinterpret_cast(buffer); + uint8_t *oend = D::process(data, data_length, obegin, utf8_writer()); + + assert(oend == obegin + length); + *oend = 0; + + out_buffer = buffer; + out_length = length + 1; + + return true; +} + +PUGI__FN size_t get_latin1_7bit_prefix_length(const uint8_t *data, + size_t size) { + for (size_t i = 0; i < size; ++i) + if (data[i] > 127) + return i; + + return size; +} + +PUGI__FN bool convert_buffer_latin1(char_t *&out_buffer, size_t &out_length, + const void *contents, size_t size, + bool is_mutable) { + const uint8_t *data = static_cast(contents); + size_t data_length = size; + + // get size of prefix that does not need utf8 conversion + size_t prefix_length = get_latin1_7bit_prefix_length(data, data_length); + assert(prefix_length <= data_length); + + const uint8_t *postfix = data + prefix_length; + size_t postfix_length = data_length - prefix_length; + + // if no conversion is needed, just return the original buffer + if (postfix_length == 0) + return get_mutable_buffer(out_buffer, out_length, contents, size, + is_mutable); + + // first pass: get length in utf8 units + size_t length = + prefix_length + + latin1_decoder::process(postfix, postfix_length, 0, utf8_counter()); + + // allocate buffer of suitable length + char_t *buffer = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!buffer) + return false; + + // second pass: convert latin1 input to utf8 + memcpy(buffer, data, prefix_length); + + uint8_t *obegin = reinterpret_cast(buffer); + uint8_t *oend = latin1_decoder::process( + postfix, postfix_length, obegin + prefix_length, utf8_writer()); + + assert(oend == obegin + length); + *oend = 0; + + out_buffer = buffer; + out_length = length + 1; + + return true; +} + +PUGI__FN bool convert_buffer(char_t *&out_buffer, size_t &out_length, + xml_encoding encoding, const void *contents, + size_t size, bool is_mutable) { + // fast path: no conversion required + if (encoding == encoding_utf8) + return get_mutable_buffer(out_buffer, out_length, contents, size, + is_mutable); + + // source encoding is utf16 + if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf16_le : encoding_utf16_be; + + return (native_encoding == encoding) + ? convert_buffer_generic(out_buffer, out_length, contents, size, + utf16_decoder()) + : convert_buffer_generic(out_buffer, out_length, contents, size, + utf16_decoder()); + } + + // source encoding is utf32 + if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf32_le : encoding_utf32_be; + + return (native_encoding == encoding) + ? convert_buffer_generic(out_buffer, out_length, contents, size, + utf32_decoder()) + : convert_buffer_generic(out_buffer, out_length, contents, size, + utf32_decoder()); + } + + // source encoding is latin1 + if (encoding == encoding_latin1) + return convert_buffer_latin1(out_buffer, out_length, contents, size, + is_mutable); + + assert(!"Invalid encoding"); + return false; +} +#endif + +PUGI__FN size_t as_utf8_begin(const wchar_t *str, size_t length) { + // get length in utf8 characters + return wchar_decoder::process(str, length, 0, utf8_counter()); +} + +PUGI__FN void as_utf8_end(char *buffer, size_t size, const wchar_t *str, + size_t length) { + // convert to utf8 + uint8_t *begin = reinterpret_cast(buffer); + uint8_t *end = wchar_decoder::process(str, length, begin, utf8_writer()); + + assert(begin + size == end); + (void)!end; + (void)!size; +} + +#ifndef PUGIXML_NO_STL +PUGI__FN std::string as_utf8_impl(const wchar_t *str, size_t length) { + // first pass: get length in utf8 characters + size_t size = as_utf8_begin(str, length); + + // allocate resulting string + std::string result; + result.resize(size); + + // second pass: convert to utf8 + if (size > 0) + as_utf8_end(&result[0], size, str, length); + + return result; +} + +PUGI__FN std::basic_string as_wide_impl(const char *str, size_t size) { + const uint8_t *data = reinterpret_cast(str); + + // first pass: get length in wchar_t units + size_t length = utf8_decoder::process(data, size, 0, wchar_counter()); + + // allocate resulting string + std::basic_string result; + result.resize(length); + + // second pass: convert to wchar_t + if (length > 0) { + wchar_writer::value_type begin = + reinterpret_cast(&result[0]); + wchar_writer::value_type end = + utf8_decoder::process(data, size, begin, wchar_writer()); + + assert(begin + length == end); + (void)!end; + } + + return result; +} +#endif + +template +inline bool strcpy_insitu_allow(size_t length, const Header &header, + uintptr_t header_mask, char_t *target) { + // never reuse shared memory + if (header & xml_memory_page_contents_shared_mask) + return false; + + size_t target_length = strlength(target); + + // always reuse document buffer memory if possible + if ((header & header_mask) == 0) + return target_length >= length; + + // reuse heap memory if waste is not too great + const size_t reuse_threshold = 32; + + return target_length >= length && + (target_length < reuse_threshold || + target_length - length < target_length / 2); +} + +template +PUGI__FN bool strcpy_insitu(String &dest, Header &header, uintptr_t header_mask, + const char_t *source, size_t source_length) { + if (source_length == 0) { + // empty string and null pointer are equivalent, so just deallocate old + // memory + xml_allocator *alloc = PUGI__GETPAGE_IMPL(header)->allocator; + + if (header & header_mask) + alloc->deallocate_string(dest); + + // mark the string as not allocated + dest = 0; + header &= ~header_mask; + + return true; + } else if (dest && + strcpy_insitu_allow(source_length, header, header_mask, dest)) { + // we can reuse old buffer, so just copy the new data (including zero + // terminator) + memcpy(dest, source, source_length * sizeof(char_t)); + dest[source_length] = 0; + + return true; + } else { + xml_allocator *alloc = PUGI__GETPAGE_IMPL(header)->allocator; + + if (!alloc->reserve()) + return false; + + // allocate new buffer + char_t *buf = alloc->allocate_string(source_length + 1); + if (!buf) + return false; + + // copy the string (including zero terminator) + memcpy(buf, source, source_length * sizeof(char_t)); + buf[source_length] = 0; + + // deallocate old buffer (*after* the above to protect against overlapping + // memory and/or allocation failures) + if (header & header_mask) + alloc->deallocate_string(dest); + + // the string is now allocated, so set the flag + dest = buf; + header |= header_mask; + + return true; + } +} + +struct gap { + char_t *end; + size_t size; + + gap() : end(0), size(0) {} + + // Push new gap, move s count bytes further (skipping the gap). + // Collapse previous gap. + void push(char_t *&s, size_t count) { + if (end) // there was a gap already; collapse it + { + // Move [old_gap_end, new_gap_start) to [old_gap_start, ...) + assert(s >= end); + memmove(end - size, end, + reinterpret_cast(s) - reinterpret_cast(end)); + } + + s += count; // end of current gap + + // "merge" two gaps + end = s; + size += count; + } + + // Collapse all gaps, return past-the-end pointer + char_t *flush(char_t *s) { + if (end) { + // Move [old_gap_end, current_pos) to [old_gap_start, ...) + assert(s >= end); + memmove(end - size, end, + reinterpret_cast(s) - reinterpret_cast(end)); + + return s - size; + } else + return s; + } +}; + +PUGI__FN char_t *strconv_escape(char_t *s, gap &g) { + char_t *stre = s + 1; + + switch (*stre) { + case '#': // &#... + { + unsigned int ucsc = 0; + + if (stre[1] == 'x') // &#x... (hex code) + { + stre += 2; + + char_t ch = *stre; + + if (ch == ';') + return stre; + + for (;;) { + if (static_cast(ch - '0') <= 9) + ucsc = 16 * ucsc + (ch - '0'); + else if (static_cast((ch | ' ') - 'a') <= 5) + ucsc = 16 * ucsc + ((ch | ' ') - 'a' + 10); + else if (ch == ';') + break; + else // cancel + return stre; + + ch = *++stre; + } + + ++stre; + } else // &#... (dec code) + { + char_t ch = *++stre; + + if (ch == ';') + return stre; + + for (;;) { + if (static_cast(static_cast(ch) - '0') <= 9) + ucsc = 10 * ucsc + (ch - '0'); + else if (ch == ';') + break; + else // cancel + return stre; + + ch = *++stre; + } + + ++stre; + } + +#ifdef PUGIXML_WCHAR_MODE + s = reinterpret_cast( + wchar_writer::any(reinterpret_cast(s), ucsc)); +#else + s = reinterpret_cast( + utf8_writer::any(reinterpret_cast(s), ucsc)); +#endif + + g.push(s, stre - s); + return stre; + } + + case 'a': // &a + { + ++stre; + + if (*stre == 'm') // &am + { + if (*++stre == 'p' && *++stre == ';') // & + { + *s++ = '&'; + ++stre; + + g.push(s, stre - s); + return stre; + } + } else if (*stre == 'p') // &ap + { + if (*++stre == 'o' && *++stre == 's' && *++stre == ';') // ' + { + *s++ = '\''; + ++stre; + + g.push(s, stre - s); + return stre; + } + } + break; + } + + case 'g': // &g + { + if (*++stre == 't' && *++stre == ';') // > + { + *s++ = '>'; + ++stre; + + g.push(s, stre - s); + return stre; + } + break; + } + + case 'l': // &l + { + if (*++stre == 't' && *++stre == ';') // < + { + *s++ = '<'; + ++stre; + + g.push(s, stre - s); + return stre; + } + break; + } + + case 'q': // &q + { + if (*++stre == 'u' && *++stre == 'o' && *++stre == 't' && + *++stre == ';') // " + { + *s++ = '"'; + ++stre; + + g.push(s, stre - s); + return stre; + } + break; + } + + default: + break; + } + + return stre; +} + +// Parser utilities +#define PUGI__ENDSWITH(c, e) ((c) == (e) || ((c) == 0 && endch == (e))) +#define PUGI__SKIPWS() \ + { \ + while (PUGI__IS_CHARTYPE(*s, ct_space)) \ + ++s; \ + } +#define PUGI__OPTSET(OPT) (optmsk & (OPT)) +#define PUGI__PUSHNODE(TYPE) \ + { \ + cursor = append_new_node(cursor, alloc, TYPE); \ + if (!cursor) \ + PUGI__THROW_ERROR(status_out_of_memory, s); \ + } +#define PUGI__POPNODE() \ + { cursor = cursor->parent; } +#define PUGI__SCANFOR(X) \ + { \ + while (*s != 0 && !(X)) \ + ++s; \ + } +#define PUGI__SCANWHILE(X) \ + { \ + while (X) \ + ++s; \ + } +#define PUGI__SCANWHILE_UNROLL(X) \ + { \ + for (;;) { \ + char_t ss = s[0]; \ + if (PUGI__UNLIKELY(!(X))) { \ + break; \ + } \ + ss = s[1]; \ + if (PUGI__UNLIKELY(!(X))) { \ + s += 1; \ + break; \ + } \ + ss = s[2]; \ + if (PUGI__UNLIKELY(!(X))) { \ + s += 2; \ + break; \ + } \ + ss = s[3]; \ + if (PUGI__UNLIKELY(!(X))) { \ + s += 3; \ + break; \ + } \ + s += 4; \ + } \ + } +#define PUGI__ENDSEG() \ + { \ + ch = *s; \ + *s = 0; \ + ++s; \ + } +#define PUGI__THROW_ERROR(err, m) \ + return error_offset = m, error_status = err, static_cast(0) +#define PUGI__CHECK_ERROR(err, m) \ + { \ + if (*s == 0) \ + PUGI__THROW_ERROR(err, m); \ + } + +PUGI__FN char_t *strconv_comment(char_t *s, char_t endch) { + gap g; + + while (true) { + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_comment)); + + if (*s == '\r') // Either a single 0x0d or 0x0d 0x0a pair + { + *s++ = '\n'; // replace first one with 0x0a + + if (*s == '\n') + g.push(s, 1); + } else if (s[0] == '-' && s[1] == '-' && + PUGI__ENDSWITH(s[2], '>')) // comment ends here + { + *g.flush(s) = 0; + + return s + (s[2] == '>' ? 3 : 2); + } else if (*s == 0) { + return 0; + } else + ++s; + } +} + +PUGI__FN char_t *strconv_cdata(char_t *s, char_t endch) { + gap g; + + while (true) { + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_cdata)); + + if (*s == '\r') // Either a single 0x0d or 0x0d 0x0a pair + { + *s++ = '\n'; // replace first one with 0x0a + + if (*s == '\n') + g.push(s, 1); + } else if (s[0] == ']' && s[1] == ']' && + PUGI__ENDSWITH(s[2], '>')) // CDATA ends here + { + *g.flush(s) = 0; + + return s + 1; + } else if (*s == 0) { + return 0; + } else + ++s; + } +} + +typedef char_t *(*strconv_pcdata_t)(char_t *); + +template +struct strconv_pcdata_impl { + static char_t *parse(char_t *s) { + gap g; + + char_t *begin = s; + + while (true) { + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_pcdata)); + + if (*s == '<') // PCDATA ends here + { + char_t *end = g.flush(s); + + if (opt_trim::value) + while (end > begin && PUGI__IS_CHARTYPE(end[-1], ct_space)) + --end; + + *end = 0; + + return s + 1; + } else if (opt_eol::value && + *s == '\r') // Either a single 0x0d or 0x0d 0x0a pair + { + *s++ = '\n'; // replace first one with 0x0a + + if (*s == '\n') + g.push(s, 1); + } else if (opt_escape::value && *s == '&') { + s = strconv_escape(s, g); + } else if (*s == 0) { + char_t *end = g.flush(s); + + if (opt_trim::value) + while (end > begin && PUGI__IS_CHARTYPE(end[-1], ct_space)) + --end; + + *end = 0; + + return s; + } else + ++s; + } + } +}; + +PUGI__FN strconv_pcdata_t get_strconv_pcdata(unsigned int optmask) { + PUGI__STATIC_ASSERT(parse_escapes == 0x10 && parse_eol == 0x20 && + parse_trim_pcdata == 0x0800); + + switch (((optmask >> 4) & 3) | + ((optmask >> 9) & 4)) // get bitmask for flags (eol escapes trim) + { + case 0: + return strconv_pcdata_impl::parse; + case 1: + return strconv_pcdata_impl::parse; + case 2: + return strconv_pcdata_impl::parse; + case 3: + return strconv_pcdata_impl::parse; + case 4: + return strconv_pcdata_impl::parse; + case 5: + return strconv_pcdata_impl::parse; + case 6: + return strconv_pcdata_impl::parse; + case 7: + return strconv_pcdata_impl::parse; + default: + assert(false); + return 0; // should not get here + } +} + +typedef char_t *(*strconv_attribute_t)(char_t *, char_t); + +template struct strconv_attribute_impl { + static char_t *parse_wnorm(char_t *s, char_t end_quote) { + gap g; + + // trim leading whitespaces + if (PUGI__IS_CHARTYPE(*s, ct_space)) { + char_t *str = s; + + do + ++str; + while (PUGI__IS_CHARTYPE(*str, ct_space)); + + g.push(s, str - s); + } + + while (true) { + PUGI__SCANWHILE_UNROLL( + !PUGI__IS_CHARTYPE(ss, ct_parse_attr_ws | ct_space)); + + if (*s == end_quote) { + char_t *str = g.flush(s); + + do + *str-- = 0; + while (PUGI__IS_CHARTYPE(*str, ct_space)); + + return s + 1; + } else if (PUGI__IS_CHARTYPE(*s, ct_space)) { + *s++ = ' '; + + if (PUGI__IS_CHARTYPE(*s, ct_space)) { + char_t *str = s + 1; + while (PUGI__IS_CHARTYPE(*str, ct_space)) + ++str; + + g.push(s, str - s); + } + } else if (opt_escape::value && *s == '&') { + s = strconv_escape(s, g); + } else if (!*s) { + return 0; + } else + ++s; + } + } + + static char_t *parse_wconv(char_t *s, char_t end_quote) { + gap g; + + while (true) { + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr_ws)); + + if (*s == end_quote) { + *g.flush(s) = 0; + + return s + 1; + } else if (PUGI__IS_CHARTYPE(*s, ct_space)) { + if (*s == '\r') { + *s++ = ' '; + + if (*s == '\n') + g.push(s, 1); + } else + *s++ = ' '; + } else if (opt_escape::value && *s == '&') { + s = strconv_escape(s, g); + } else if (!*s) { + return 0; + } else + ++s; + } + } + + static char_t *parse_eol(char_t *s, char_t end_quote) { + gap g; + + while (true) { + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr)); + + if (*s == end_quote) { + *g.flush(s) = 0; + + return s + 1; + } else if (*s == '\r') { + *s++ = '\n'; + + if (*s == '\n') + g.push(s, 1); + } else if (opt_escape::value && *s == '&') { + s = strconv_escape(s, g); + } else if (!*s) { + return 0; + } else + ++s; + } + } + + static char_t *parse_simple(char_t *s, char_t end_quote) { + gap g; + + while (true) { + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr)); + + if (*s == end_quote) { + *g.flush(s) = 0; + + return s + 1; + } else if (opt_escape::value && *s == '&') { + s = strconv_escape(s, g); + } else if (!*s) { + return 0; + } else + ++s; + } + } +}; + +PUGI__FN strconv_attribute_t get_strconv_attribute(unsigned int optmask) { + PUGI__STATIC_ASSERT(parse_escapes == 0x10 && parse_eol == 0x20 && + parse_wconv_attribute == 0x40 && + parse_wnorm_attribute == 0x80); + + switch ((optmask >> 4) & + 15) // get bitmask for flags (wconv wnorm eol escapes) + { + case 0: + return strconv_attribute_impl::parse_simple; + case 1: + return strconv_attribute_impl::parse_simple; + case 2: + return strconv_attribute_impl::parse_eol; + case 3: + return strconv_attribute_impl::parse_eol; + case 4: + return strconv_attribute_impl::parse_wconv; + case 5: + return strconv_attribute_impl::parse_wconv; + case 6: + return strconv_attribute_impl::parse_wconv; + case 7: + return strconv_attribute_impl::parse_wconv; + case 8: + return strconv_attribute_impl::parse_wnorm; + case 9: + return strconv_attribute_impl::parse_wnorm; + case 10: + return strconv_attribute_impl::parse_wnorm; + case 11: + return strconv_attribute_impl::parse_wnorm; + case 12: + return strconv_attribute_impl::parse_wnorm; + case 13: + return strconv_attribute_impl::parse_wnorm; + case 14: + return strconv_attribute_impl::parse_wnorm; + case 15: + return strconv_attribute_impl::parse_wnorm; + default: + assert(false); + return 0; // should not get here + } +} + +inline xml_parse_result make_parse_result(xml_parse_status status, + ptrdiff_t offset = 0) { + xml_parse_result result; + result.status = status; + result.offset = offset; + + return result; +} + +struct xml_parser { + xml_allocator alloc; + xml_allocator *alloc_state; + char_t *error_offset; + xml_parse_status error_status; + + xml_parser(xml_allocator *alloc_) + : alloc(*alloc_), alloc_state(alloc_), error_offset(0), + error_status(status_ok) {} + + ~xml_parser() { *alloc_state = alloc; } + + // DOCTYPE consists of nested sections of the following possible types: + // , , "...", '...' + // + // + // First group can not contain nested groups + // Second group can contain nested groups of the same type + // Third group can contain all other groups + char_t *parse_doctype_primitive(char_t *s) { + if (*s == '"' || *s == '\'') { + // quoted string + char_t ch = *s++; + PUGI__SCANFOR(*s == ch); + if (!*s) + PUGI__THROW_ERROR(status_bad_doctype, s); + + s++; + } else if (s[0] == '<' && s[1] == '?') { + // + s += 2; + PUGI__SCANFOR(s[0] == '?' && + s[1] == '>'); // no need for ENDSWITH because ?> can't + // terminate proper doctype + if (!*s) + PUGI__THROW_ERROR(status_bad_doctype, s); + + s += 2; + } else if (s[0] == '<' && s[1] == '!' && s[2] == '-' && s[3] == '-') { + s += 4; + PUGI__SCANFOR(s[0] == '-' && s[1] == '-' && + s[2] == '>'); // no need for ENDSWITH because --> can't + // terminate proper doctype + if (!*s) + PUGI__THROW_ERROR(status_bad_doctype, s); + + s += 3; + } else + PUGI__THROW_ERROR(status_bad_doctype, s); + + return s; + } + + char_t *parse_doctype_ignore(char_t *s) { + size_t depth = 0; + + assert(s[0] == '<' && s[1] == '!' && s[2] == '['); + s += 3; + + while (*s) { + if (s[0] == '<' && s[1] == '!' && s[2] == '[') { + // nested ignore section + s += 3; + depth++; + } else if (s[0] == ']' && s[1] == ']' && s[2] == '>') { + // ignore section end + s += 3; + + if (depth == 0) + return s; + + depth--; + } else + s++; + } + + PUGI__THROW_ERROR(status_bad_doctype, s); + } + + char_t *parse_doctype_group(char_t *s, char_t endch) { + size_t depth = 0; + + assert((s[0] == '<' || s[0] == 0) && s[1] == '!'); + s += 2; + + while (*s) { + if (s[0] == '<' && s[1] == '!' && s[2] != '-') { + if (s[2] == '[') { + // ignore + s = parse_doctype_ignore(s); + if (!s) + return s; + } else { + // some control group + s += 2; + depth++; + } + } else if (s[0] == '<' || s[0] == '"' || s[0] == '\'') { + // unknown tag (forbidden), or some primitive group + s = parse_doctype_primitive(s); + if (!s) + return s; + } else if (*s == '>') { + if (depth == 0) + return s; + + depth--; + s++; + } else + s++; + } + + if (depth != 0 || endch != '>') + PUGI__THROW_ERROR(status_bad_doctype, s); + + return s; + } + + char_t *parse_exclamation(char_t *s, xml_node_struct *cursor, + unsigned int optmsk, char_t endch) { + // parse node contents, starting with exclamation mark + ++s; + + if (*s == '-') // 'value = s; // Save the offset. + } + + if (PUGI__OPTSET(parse_eol) && PUGI__OPTSET(parse_comments)) { + s = strconv_comment(s, endch); + + if (!s) + PUGI__THROW_ERROR(status_bad_comment, cursor->value); + } else { + // Scan for terminating '-->'. + PUGI__SCANFOR(s[0] == '-' && s[1] == '-' && + PUGI__ENDSWITH(s[2], '>')); + PUGI__CHECK_ERROR(status_bad_comment, s); + + if (PUGI__OPTSET(parse_comments)) + *s = 0; // Zero-terminate this segment at the first terminating '-'. + + s += (s[2] == '>' ? 3 : 2); // Step over the '\0->'. + } + } else + PUGI__THROW_ERROR(status_bad_comment, s); + } else if (*s == '[') { + // 'value = s; // Save the offset. + + if (PUGI__OPTSET(parse_eol)) { + s = strconv_cdata(s, endch); + + if (!s) + PUGI__THROW_ERROR(status_bad_cdata, cursor->value); + } else { + // Scan for terminating ']]>'. + PUGI__SCANFOR(s[0] == ']' && s[1] == ']' && + PUGI__ENDSWITH(s[2], '>')); + PUGI__CHECK_ERROR(status_bad_cdata, s); + + *s++ = 0; // Zero-terminate this segment. + } + } else // Flagged for discard, but we still have to scan for the + // terminator. + { + // Scan for terminating ']]>'. + PUGI__SCANFOR(s[0] == ']' && s[1] == ']' && + PUGI__ENDSWITH(s[2], '>')); + PUGI__CHECK_ERROR(status_bad_cdata, s); + + ++s; + } + + s += (s[1] == '>' ? 2 : 1); // Step over the last ']>'. + } else + PUGI__THROW_ERROR(status_bad_cdata, s); + } else if (s[0] == 'D' && s[1] == 'O' && s[2] == 'C' && s[3] == 'T' && + s[4] == 'Y' && s[5] == 'P' && PUGI__ENDSWITH(s[6], 'E')) { + s -= 2; + + if (cursor->parent) + PUGI__THROW_ERROR(status_bad_doctype, s); + + char_t *mark = s + 9; + + s = parse_doctype_group(s, endch); + if (!s) + return s; + + assert((*s == 0 && endch == '>') || *s == '>'); + if (*s) + *s++ = 0; + + if (PUGI__OPTSET(parse_doctype)) { + while (PUGI__IS_CHARTYPE(*mark, ct_space)) + ++mark; + + PUGI__PUSHNODE(node_doctype); + + cursor->value = mark; + } + } else if (*s == 0 && endch == '-') + PUGI__THROW_ERROR(status_bad_comment, s); + else if (*s == 0 && endch == '[') + PUGI__THROW_ERROR(status_bad_cdata, s); + else + PUGI__THROW_ERROR(status_unrecognized_tag, s); + + return s; + } + + char_t *parse_question(char_t *s, xml_node_struct *&ref_cursor, + unsigned int optmsk, char_t endch) { + // load into registers + xml_node_struct *cursor = ref_cursor; + char_t ch = 0; + + // parse node contents, starting with question mark + ++s; + + // read PI target + char_t *target = s; + + if (!PUGI__IS_CHARTYPE(*s, ct_start_symbol)) + PUGI__THROW_ERROR(status_bad_pi, s); + + PUGI__SCANWHILE(PUGI__IS_CHARTYPE(*s, ct_symbol)); + PUGI__CHECK_ERROR(status_bad_pi, s); + + // determine node type; stricmp / strcasecmp is not portable + bool declaration = (target[0] | ' ') == 'x' && (target[1] | ' ') == 'm' && + (target[2] | ' ') == 'l' && target + 3 == s; + + if (declaration ? PUGI__OPTSET(parse_declaration) + : PUGI__OPTSET(parse_pi)) { + if (declaration) { + // disallow non top-level declarations + if (cursor->parent) + PUGI__THROW_ERROR(status_bad_pi, s); + + PUGI__PUSHNODE(node_declaration); + } else { + PUGI__PUSHNODE(node_pi); + } + + cursor->name = target; + + PUGI__ENDSEG(); + + // parse value/attributes + if (ch == '?') { + // empty node + if (!PUGI__ENDSWITH(*s, '>')) + PUGI__THROW_ERROR(status_bad_pi, s); + s += (*s == '>'); + + PUGI__POPNODE(); + } else if (PUGI__IS_CHARTYPE(ch, ct_space)) { + PUGI__SKIPWS(); + + // scan for tag end + char_t *value = s; + + PUGI__SCANFOR(s[0] == '?' && PUGI__ENDSWITH(s[1], '>')); + PUGI__CHECK_ERROR(status_bad_pi, s); + + if (declaration) { + // replace ending ? with / so that 'element' terminates properly + *s = '/'; + + // we exit from this function with cursor at node_declaration, which + // is a signal to parse() to go to LOC_ATTRIBUTES + s = value; + } else { + // store value and step over > + cursor->value = value; + + PUGI__POPNODE(); + + PUGI__ENDSEG(); + + s += (*s == '>'); + } + } else + PUGI__THROW_ERROR(status_bad_pi, s); + } else { + // scan for tag end + PUGI__SCANFOR(s[0] == '?' && PUGI__ENDSWITH(s[1], '>')); + PUGI__CHECK_ERROR(status_bad_pi, s); + + s += (s[1] == '>' ? 2 : 1); + } + + // store from registers + ref_cursor = cursor; + + return s; + } + + char_t *parse_tree(char_t *s, xml_node_struct *root, unsigned int optmsk, + char_t endch) { + strconv_attribute_t strconv_attribute = get_strconv_attribute(optmsk); + strconv_pcdata_t strconv_pcdata = get_strconv_pcdata(optmsk); + + char_t ch = 0; + xml_node_struct *cursor = root; + char_t *mark = s; + + while (*s != 0) { + if (*s == '<') { + ++s; + + LOC_TAG: + if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) // '<#...' + { + PUGI__PUSHNODE(node_element); // Append a new node to the tree. + + cursor->name = s; + + PUGI__SCANWHILE_UNROLL( + PUGI__IS_CHARTYPE(ss, ct_symbol)); // Scan for a terminator. + PUGI__ENDSEG(); // Save char in 'ch', terminate & step over. + + if (ch == '>') { + // end of tag + } else if (PUGI__IS_CHARTYPE(ch, ct_space)) { + LOC_ATTRIBUTES: + while (true) { + PUGI__SKIPWS(); // Eat any whitespace. + + if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) // <... #... + { + xml_attribute_struct *a = append_new_attribute( + cursor, alloc); // Make space for this attribute. + if (!a) + PUGI__THROW_ERROR(status_out_of_memory, s); + + a->name = s; // Save the offset. + + PUGI__SCANWHILE_UNROLL( + PUGI__IS_CHARTYPE(ss, ct_symbol)); // Scan for a terminator. + PUGI__ENDSEG(); // Save char in 'ch', terminate & step over. + + if (PUGI__IS_CHARTYPE(ch, ct_space)) { + PUGI__SKIPWS(); // Eat any whitespace. + + ch = *s; + ++s; + } + + if (ch == '=') // '<... #=...' + { + PUGI__SKIPWS(); // Eat any whitespace. + + if (*s == '"' || *s == '\'') // '<... #="...' + { + ch = *s; // Save quote char to avoid breaking on "''" -or- + // '""'. + ++s; // Step over the quote. + a->value = s; // Save the offset. + + s = strconv_attribute(s, ch); + + if (!s) + PUGI__THROW_ERROR(status_bad_attribute, a->value); + + // After this line the loop continues from the start; + // Whitespaces, / and > are ok, symbols and EOF are wrong, + // everything else will be detected + if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) + PUGI__THROW_ERROR(status_bad_attribute, s); + } else + PUGI__THROW_ERROR(status_bad_attribute, s); + } else + PUGI__THROW_ERROR(status_bad_attribute, s); + } else if (*s == '/') { + ++s; + + if (*s == '>') { + PUGI__POPNODE(); + s++; + break; + } else if (*s == 0 && endch == '>') { + PUGI__POPNODE(); + break; + } else + PUGI__THROW_ERROR(status_bad_start_element, s); + } else if (*s == '>') { + ++s; + + break; + } else if (*s == 0 && endch == '>') { + break; + } else + PUGI__THROW_ERROR(status_bad_start_element, s); + } + + // !!! + } else if (ch == '/') // '<#.../' + { + if (!PUGI__ENDSWITH(*s, '>')) + PUGI__THROW_ERROR(status_bad_start_element, s); + + PUGI__POPNODE(); // Pop. + + s += (*s == '>'); + } else if (ch == 0) { + // we stepped over null terminator, backtrack & handle closing tag + --s; + + if (endch != '>') + PUGI__THROW_ERROR(status_bad_start_element, s); + } else + PUGI__THROW_ERROR(status_bad_start_element, s); + } else if (*s == '/') { + ++s; + + char_t *name = cursor->name; + if (!name) + PUGI__THROW_ERROR(status_end_element_mismatch, s); + + while (PUGI__IS_CHARTYPE(*s, ct_symbol)) { + if (*s++ != *name++) + PUGI__THROW_ERROR(status_end_element_mismatch, s); + } + + if (*name) { + if (*s == 0 && name[0] == endch && name[1] == 0) + PUGI__THROW_ERROR(status_bad_end_element, s); + else + PUGI__THROW_ERROR(status_end_element_mismatch, s); + } + + PUGI__POPNODE(); // Pop. + + PUGI__SKIPWS(); + + if (*s == 0) { + if (endch != '>') + PUGI__THROW_ERROR(status_bad_end_element, s); + } else { + if (*s != '>') + PUGI__THROW_ERROR(status_bad_end_element, s); + ++s; + } + } else if (*s == '?') // 'first_child) + continue; + } + } + + if (!PUGI__OPTSET(parse_trim_pcdata)) + s = mark; + + if (cursor->parent || PUGI__OPTSET(parse_fragment)) { + PUGI__PUSHNODE(node_pcdata); // Append a new node on the tree. + cursor->value = s; // Save the offset. + + s = strconv_pcdata(s); + + PUGI__POPNODE(); // Pop since this is a standalone. + + if (!*s) + break; + } else { + PUGI__SCANFOR(*s == '<'); // '...<' + if (!*s) + break; + + ++s; + } + + // We're after '<' + goto LOC_TAG; + } + } + + // check that last tag is closed + if (cursor != root) + PUGI__THROW_ERROR(status_end_element_mismatch, s); + + return s; + } + +#ifdef PUGIXML_WCHAR_MODE + static char_t *parse_skip_bom(char_t *s) { + unsigned int bom = 0xfeff; + return (s[0] == static_cast(bom)) ? s + 1 : s; + } +#else + static char_t *parse_skip_bom(char_t *s) { + return (s[0] == '\xef' && s[1] == '\xbb' && s[2] == '\xbf') ? s + 3 : s; + } +#endif + + static bool has_element_node_siblings(xml_node_struct *node) { + while (node) { + if (PUGI__NODETYPE(node) == node_element) + return true; + + node = node->next_sibling; + } + + return false; + } + + static xml_parse_result parse(char_t *buffer, size_t length, + xml_document_struct *xmldoc, + xml_node_struct *root, unsigned int optmsk) { + // early-out for empty documents + if (length == 0) + return make_parse_result(PUGI__OPTSET(parse_fragment) + ? status_ok + : status_no_document_element); + + // get last child of the root before parsing + xml_node_struct *last_root_child = + root->first_child ? root->first_child->prev_sibling_c + 0 : 0; + + // create parser on stack + xml_parser parser(static_cast(xmldoc)); + + // save last character and make buffer zero-terminated (speeds up parsing) + char_t endch = buffer[length - 1]; + buffer[length - 1] = 0; + + // skip BOM to make sure it does not end up as part of parse output + char_t *buffer_data = parse_skip_bom(buffer); + + // perform actual parsing + parser.parse_tree(buffer_data, root, optmsk, endch); + + xml_parse_result result = make_parse_result( + parser.error_status, + parser.error_offset ? parser.error_offset - buffer : 0); + assert(result.offset >= 0 && static_cast(result.offset) <= length); + + if (result) { + // since we removed last character, we have to handle the only possible + // false positive (stray <) + if (endch == '<') + return make_parse_result(status_unrecognized_tag, length - 1); + + // check if there are any element nodes parsed + xml_node_struct *first_root_child_parsed = + last_root_child ? last_root_child->next_sibling + 0 + : root->first_child + 0; + + if (!PUGI__OPTSET(parse_fragment) && + !has_element_node_siblings(first_root_child_parsed)) + return make_parse_result(status_no_document_element, length - 1); + } else { + // roll back offset if it occurs on a null terminator in the source buffer + if (result.offset > 0 && + static_cast(result.offset) == length - 1 && endch == 0) + result.offset--; + } + + return result; + } +}; + +// Output facilities +PUGI__FN xml_encoding get_write_native_encoding() { +#ifdef PUGIXML_WCHAR_MODE + return get_wchar_encoding(); +#else + return encoding_utf8; +#endif +} + +PUGI__FN xml_encoding get_write_encoding(xml_encoding encoding) { + // replace wchar encoding with utf implementation + if (encoding == encoding_wchar) + return get_wchar_encoding(); + + // replace utf16 encoding with utf16 with specific endianness + if (encoding == encoding_utf16) + return is_little_endian() ? encoding_utf16_le : encoding_utf16_be; + + // replace utf32 encoding with utf32 with specific endianness + if (encoding == encoding_utf32) + return is_little_endian() ? encoding_utf32_le : encoding_utf32_be; + + // only do autodetection if no explicit encoding is requested + if (encoding != encoding_auto) + return encoding; + + // assume utf8 encoding + return encoding_utf8; +} + +template +PUGI__FN size_t convert_buffer_output_generic(typename T::value_type dest, + const char_t *data, size_t length, + D, T) { + PUGI__STATIC_ASSERT(sizeof(char_t) == sizeof(typename D::type)); + + typename T::value_type end = D::process( + reinterpret_cast(data), length, dest, T()); + + return static_cast(end - dest) * sizeof(*dest); +} + +template +PUGI__FN size_t convert_buffer_output_generic(typename T::value_type dest, + const char_t *data, size_t length, + D, T, bool opt_swap) { + PUGI__STATIC_ASSERT(sizeof(char_t) == sizeof(typename D::type)); + + typename T::value_type end = D::process( + reinterpret_cast(data), length, dest, T()); + + if (opt_swap) { + for (typename T::value_type i = dest; i != end; ++i) + *i = endian_swap(*i); + } + + return static_cast(end - dest) * sizeof(*dest); +} + +#ifdef PUGIXML_WCHAR_MODE +PUGI__FN size_t get_valid_length(const char_t *data, size_t length) { + if (length < 1) + return 0; + + // discard last character if it's the lead of a surrogate pair + return (sizeof(wchar_t) == 2 && + static_cast(static_cast(data[length - 1]) - + 0xD800) < 0x400) + ? length - 1 + : length; +} + +PUGI__FN size_t convert_buffer_output(char_t *r_char, uint8_t *r_u8, + uint16_t *r_u16, uint32_t *r_u32, + const char_t *data, size_t length, + xml_encoding encoding) { + // only endian-swapping is required + if (need_endian_swap_utf(encoding, get_wchar_encoding())) { + convert_wchar_endian_swap(r_char, data, length); + + return length * sizeof(char_t); + } + + // convert to utf8 + if (encoding == encoding_utf8) + return convert_buffer_output_generic(r_u8, data, length, wchar_decoder(), + utf8_writer()); + + // convert to utf16 + if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf16_le : encoding_utf16_be; + + return convert_buffer_output_generic(r_u16, data, length, wchar_decoder(), + utf16_writer(), + native_encoding != encoding); + } + + // convert to utf32 + if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf32_le : encoding_utf32_be; + + return convert_buffer_output_generic(r_u32, data, length, wchar_decoder(), + utf32_writer(), + native_encoding != encoding); + } + + // convert to latin1 + if (encoding == encoding_latin1) + return convert_buffer_output_generic(r_u8, data, length, wchar_decoder(), + latin1_writer()); + + assert(!"Invalid encoding"); + return 0; +} +#else +PUGI__FN size_t get_valid_length(const char_t *data, size_t length) { + if (length < 5) + return 0; + + for (size_t i = 1; i <= 4; ++i) { + uint8_t ch = static_cast(data[length - i]); + + // either a standalone character or a leading one + if ((ch & 0xc0) != 0x80) + return length - i; + } + + // there are four non-leading characters at the end, sequence tail is broken + // so might as well process the whole chunk + return length; +} + +PUGI__FN size_t convert_buffer_output(char_t * /* r_char */, uint8_t *r_u8, + uint16_t *r_u16, uint32_t *r_u32, + const char_t *data, size_t length, + xml_encoding encoding) { + if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf16_le : encoding_utf16_be; + + return convert_buffer_output_generic(r_u16, data, length, utf8_decoder(), + utf16_writer(), + native_encoding != encoding); + } + + if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { + xml_encoding native_encoding = + is_little_endian() ? encoding_utf32_le : encoding_utf32_be; + + return convert_buffer_output_generic(r_u32, data, length, utf8_decoder(), + utf32_writer(), + native_encoding != encoding); + } + + if (encoding == encoding_latin1) + return convert_buffer_output_generic(r_u8, data, length, utf8_decoder(), + latin1_writer()); + + assert(!"Invalid encoding"); + return 0; +} +#endif + +class xml_buffered_writer { + xml_buffered_writer(const xml_buffered_writer &); + xml_buffered_writer &operator=(const xml_buffered_writer &); + +public: + xml_buffered_writer(xml_writer &writer_, xml_encoding user_encoding) + : writer(writer_), bufsize(0), + encoding(get_write_encoding(user_encoding)) { + PUGI__STATIC_ASSERT(bufcapacity >= 8); + } + + size_t flush() { + flush(buffer, bufsize); + bufsize = 0; + return 0; + } + + void flush(const char_t *data, size_t size) { + if (size == 0) + return; + + // fast path, just write data + if (encoding == get_write_native_encoding()) + writer.write(data, size * sizeof(char_t)); + else { + // convert chunk + size_t result = convert_buffer_output(scratch.data_char, scratch.data_u8, + scratch.data_u16, scratch.data_u32, + data, size, encoding); + assert(result <= sizeof(scratch)); + + // write data + writer.write(scratch.data_u8, result); + } + } + + void write_direct(const char_t *data, size_t length) { + // flush the remaining buffer contents + flush(); + + // handle large chunks + if (length > bufcapacity) { + if (encoding == get_write_native_encoding()) { + // fast path, can just write data chunk + writer.write(data, length * sizeof(char_t)); + return; + } + + // need to convert in suitable chunks + while (length > bufcapacity) { + // get chunk size by selecting such number of characters that are + // guaranteed to fit into scratch buffer and form a complete codepoint + // sequence (i.e. discard start of last codepoint if necessary) + size_t chunk_size = get_valid_length(data, bufcapacity); + assert(chunk_size); + + // convert chunk and write + flush(data, chunk_size); + + // iterate + data += chunk_size; + length -= chunk_size; + } + + // small tail is copied below + bufsize = 0; + } + + memcpy(buffer + bufsize, data, length * sizeof(char_t)); + bufsize += length; + } + + void write_buffer(const char_t *data, size_t length) { + size_t offset = bufsize; + + if (offset + length <= bufcapacity) { + memcpy(buffer + offset, data, length * sizeof(char_t)); + bufsize = offset + length; + } else { + write_direct(data, length); + } + } + + void write_string(const char_t *data) { + // write the part of the string that fits in the buffer + size_t offset = bufsize; + + while (*data && offset < bufcapacity) + buffer[offset++] = *data++; + + // write the rest + if (offset < bufcapacity) { + bufsize = offset; + } else { + // backtrack a bit if we have split the codepoint + size_t length = offset - bufsize; + size_t extra = length - get_valid_length(data - length, length); + + bufsize = offset - extra; + + write_direct(data - extra, strlength(data) + extra); + } + } + + void write(char_t d0) { + size_t offset = bufsize; + if (offset > bufcapacity - 1) + offset = flush(); + + buffer[offset + 0] = d0; + bufsize = offset + 1; + } + + void write(char_t d0, char_t d1) { + size_t offset = bufsize; + if (offset > bufcapacity - 2) + offset = flush(); + + buffer[offset + 0] = d0; + buffer[offset + 1] = d1; + bufsize = offset + 2; + } + + void write(char_t d0, char_t d1, char_t d2) { + size_t offset = bufsize; + if (offset > bufcapacity - 3) + offset = flush(); + + buffer[offset + 0] = d0; + buffer[offset + 1] = d1; + buffer[offset + 2] = d2; + bufsize = offset + 3; + } + + void write(char_t d0, char_t d1, char_t d2, char_t d3) { + size_t offset = bufsize; + if (offset > bufcapacity - 4) + offset = flush(); + + buffer[offset + 0] = d0; + buffer[offset + 1] = d1; + buffer[offset + 2] = d2; + buffer[offset + 3] = d3; + bufsize = offset + 4; + } + + void write(char_t d0, char_t d1, char_t d2, char_t d3, char_t d4) { + size_t offset = bufsize; + if (offset > bufcapacity - 5) + offset = flush(); + + buffer[offset + 0] = d0; + buffer[offset + 1] = d1; + buffer[offset + 2] = d2; + buffer[offset + 3] = d3; + buffer[offset + 4] = d4; + bufsize = offset + 5; + } + + void write(char_t d0, char_t d1, char_t d2, char_t d3, char_t d4, char_t d5) { + size_t offset = bufsize; + if (offset > bufcapacity - 6) + offset = flush(); + + buffer[offset + 0] = d0; + buffer[offset + 1] = d1; + buffer[offset + 2] = d2; + buffer[offset + 3] = d3; + buffer[offset + 4] = d4; + buffer[offset + 5] = d5; + bufsize = offset + 6; + } + + // utf8 maximum expansion: x4 (-> utf32) + // utf16 maximum expansion: x2 (-> utf32) + // utf32 maximum expansion: x1 + enum { + bufcapacitybytes = +#ifdef PUGIXML_MEMORY_OUTPUT_STACK + PUGIXML_MEMORY_OUTPUT_STACK +#else + 10240 +#endif + , + bufcapacity = bufcapacitybytes / (sizeof(char_t) + 4) + }; + + char_t buffer[bufcapacity]; + + union { + uint8_t data_u8[4 * bufcapacity]; + uint16_t data_u16[2 * bufcapacity]; + uint32_t data_u32[bufcapacity]; + char_t data_char[bufcapacity]; + } scratch; + + xml_writer &writer; + size_t bufsize; + xml_encoding encoding; +}; + +PUGI__FN void text_output_escaped(xml_buffered_writer &writer, const char_t *s, + chartypex_t type) { + while (*s) { + const char_t *prev = s; + + // While *s is a usual symbol + PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPEX(ss, type)); + + writer.write_buffer(prev, static_cast(s - prev)); + + switch (*s) { + case 0: + break; + case '&': + writer.write('&', 'a', 'm', 'p', ';'); + ++s; + break; + case '<': + writer.write('&', 'l', 't', ';'); + ++s; + break; + case '>': + writer.write('&', 'g', 't', ';'); + ++s; + break; + case '"': + writer.write('&', 'q', 'u', 'o', 't', ';'); + ++s; + break; + default: // s is not a usual symbol + { + unsigned int ch = static_cast(*s++); + assert(ch < 32); + + writer.write('&', '#', static_cast((ch / 10) + '0'), + static_cast((ch % 10) + '0'), ';'); + } + } + } +} + +PUGI__FN void text_output(xml_buffered_writer &writer, const char_t *s, + chartypex_t type, unsigned int flags) { + if (flags & format_no_escapes) + writer.write_string(s); + else + text_output_escaped(writer, s, type); +} + +PUGI__FN void text_output_cdata(xml_buffered_writer &writer, const char_t *s) { + do { + writer.write('<', '!', '[', 'C', 'D'); + writer.write('A', 'T', 'A', '['); + + const char_t *prev = s; + + // look for ]]> sequence - we can't output it as is since it terminates + // CDATA + while (*s && !(s[0] == ']' && s[1] == ']' && s[2] == '>')) + ++s; + + // skip ]] if we stopped at ]]>, > will go to the next CDATA section + if (*s) + s += 2; + + writer.write_buffer(prev, static_cast(s - prev)); + + writer.write(']', ']', '>'); + } while (*s); +} + +PUGI__FN void text_output_indent(xml_buffered_writer &writer, + const char_t *indent, size_t indent_length, + unsigned int depth) { + switch (indent_length) { + case 1: { + for (unsigned int i = 0; i < depth; ++i) + writer.write(indent[0]); + break; + } + + case 2: { + for (unsigned int i = 0; i < depth; ++i) + writer.write(indent[0], indent[1]); + break; + } + + case 3: { + for (unsigned int i = 0; i < depth; ++i) + writer.write(indent[0], indent[1], indent[2]); + break; + } + + case 4: { + for (unsigned int i = 0; i < depth; ++i) + writer.write(indent[0], indent[1], indent[2], indent[3]); + break; + } + + default: { + for (unsigned int i = 0; i < depth; ++i) + writer.write_buffer(indent, indent_length); + } + } +} + +PUGI__FN void node_output_comment(xml_buffered_writer &writer, + const char_t *s) { + writer.write('<', '!', '-', '-'); + + while (*s) { + const char_t *prev = s; + + // look for -\0 or -- sequence - we can't output it since -- is illegal in + // comment body + while (*s && !(s[0] == '-' && (s[1] == '-' || s[1] == 0))) + ++s; + + writer.write_buffer(prev, static_cast(s - prev)); + + if (*s) { + assert(*s == '-'); + + writer.write('-', ' '); + ++s; + } + } + + writer.write('-', '-', '>'); +} + +PUGI__FN void node_output_pi_value(xml_buffered_writer &writer, + const char_t *s) { + while (*s) { + const char_t *prev = s; + + // look for ?> sequence - we can't output it since ?> terminates PI + while (*s && !(s[0] == '?' && s[1] == '>')) + ++s; + + writer.write_buffer(prev, static_cast(s - prev)); + + if (*s) { + assert(s[0] == '?' && s[1] == '>'); + + writer.write('?', ' ', '>'); + s += 2; + } + } +} + +PUGI__FN void node_output_attributes(xml_buffered_writer &writer, + xml_node_struct *node, + const char_t *indent, size_t indent_length, + unsigned int flags, unsigned int depth) { + const char_t *default_name = PUGIXML_TEXT(":anonymous"); + + for (xml_attribute_struct *a = node->first_attribute; a; + a = a->next_attribute) { + if ((flags & (format_indent_attributes | format_raw)) == + format_indent_attributes) { + writer.write('\n'); + + text_output_indent(writer, indent, indent_length, depth + 1); + } else { + writer.write(' '); + } + + writer.write_string(a->name ? a->name + 0 : default_name); + writer.write('=', '"'); + + if (a->value) + text_output(writer, a->value, ctx_special_attr, flags); + + writer.write('"'); + } +} + +PUGI__FN bool node_output_start(xml_buffered_writer &writer, + xml_node_struct *node, const char_t *indent, + size_t indent_length, unsigned int flags, + unsigned int depth) { + const char_t *default_name = PUGIXML_TEXT(":anonymous"); + const char_t *name = node->name ? node->name + 0 : default_name; + + writer.write('<'); + writer.write_string(name); + + if (node->first_attribute) + node_output_attributes(writer, node, indent, indent_length, flags, depth); + + if (!node->first_child) { + writer.write(' ', '/', '>'); + + return false; + } else { + writer.write('>'); + + return true; + } +} + +PUGI__FN void node_output_end(xml_buffered_writer &writer, + xml_node_struct *node) { + const char_t *default_name = PUGIXML_TEXT(":anonymous"); + const char_t *name = node->name ? node->name + 0 : default_name; + + writer.write('<', '/'); + writer.write_string(name); + writer.write('>'); +} + +PUGI__FN void node_output_simple(xml_buffered_writer &writer, + xml_node_struct *node, unsigned int flags) { + const char_t *default_name = PUGIXML_TEXT(":anonymous"); + + switch (PUGI__NODETYPE(node)) { + case node_pcdata: + text_output(writer, node->value ? node->value + 0 : PUGIXML_TEXT(""), + ctx_special_pcdata, flags); + break; + + case node_cdata: + text_output_cdata(writer, node->value ? node->value + 0 : PUGIXML_TEXT("")); + break; + + case node_comment: + node_output_comment(writer, + node->value ? node->value + 0 : PUGIXML_TEXT("")); + break; + + case node_pi: + writer.write('<', '?'); + writer.write_string(node->name ? node->name + 0 : default_name); + + if (node->value) { + writer.write(' '); + node_output_pi_value(writer, node->value); + } + + writer.write('?', '>'); + break; + + case node_declaration: + writer.write('<', '?'); + writer.write_string(node->name ? node->name + 0 : default_name); + node_output_attributes(writer, node, PUGIXML_TEXT(""), 0, + flags | format_raw, 0); + writer.write('?', '>'); + break; + + case node_doctype: + writer.write('<', '!', 'D', 'O', 'C'); + writer.write('T', 'Y', 'P', 'E'); + + if (node->value) { + writer.write(' '); + writer.write_string(node->value); + } + + writer.write('>'); + break; + + default: + assert(!"Invalid node type"); + } +} + +enum indent_flags_t { indent_newline = 1, indent_indent = 2 }; + +PUGI__FN void node_output(xml_buffered_writer &writer, xml_node_struct *root, + const char_t *indent, unsigned int flags, + unsigned int depth) { + size_t indent_length = + ((flags & (format_indent | format_indent_attributes)) && + (flags & format_raw) == 0) + ? strlength(indent) + : 0; + unsigned int indent_flags = indent_indent; + + xml_node_struct *node = root; + + do { + assert(node); + + // begin writing current node + if (PUGI__NODETYPE(node) == node_pcdata || + PUGI__NODETYPE(node) == node_cdata) { + node_output_simple(writer, node, flags); + + indent_flags = 0; + } else { + if ((indent_flags & indent_newline) && (flags & format_raw) == 0) + writer.write('\n'); + + if ((indent_flags & indent_indent) && indent_length) + text_output_indent(writer, indent, indent_length, depth); + + if (PUGI__NODETYPE(node) == node_element) { + indent_flags = indent_newline | indent_indent; + + if (node_output_start(writer, node, indent, indent_length, flags, + depth)) { + node = node->first_child; + depth++; + continue; + } + } else if (PUGI__NODETYPE(node) == node_document) { + indent_flags = indent_indent; + + if (node->first_child) { + node = node->first_child; + continue; + } + } else { + node_output_simple(writer, node, flags); + + indent_flags = indent_newline | indent_indent; + } + } + + // continue to the next node + while (node != root) { + if (node->next_sibling) { + node = node->next_sibling; + break; + } + + node = node->parent; + + // write closing node + if (PUGI__NODETYPE(node) == node_element) { + depth--; + + if ((indent_flags & indent_newline) && (flags & format_raw) == 0) + writer.write('\n'); + + if ((indent_flags & indent_indent) && indent_length) + text_output_indent(writer, indent, indent_length, depth); + + node_output_end(writer, node); + + indent_flags = indent_newline | indent_indent; + } + } + } while (node != root); + + if ((indent_flags & indent_newline) && (flags & format_raw) == 0) + writer.write('\n'); +} + +PUGI__FN bool has_declaration(xml_node_struct *node) { + for (xml_node_struct *child = node->first_child; child; + child = child->next_sibling) { + xml_node_type type = PUGI__NODETYPE(child); + + if (type == node_declaration) + return true; + if (type == node_element) + return false; + } + + return false; +} + +PUGI__FN bool is_attribute_of(xml_attribute_struct *attr, + xml_node_struct *node) { + for (xml_attribute_struct *a = node->first_attribute; a; + a = a->next_attribute) + if (a == attr) + return true; + + return false; +} + +PUGI__FN bool allow_insert_attribute(xml_node_type parent) { + return parent == node_element || parent == node_declaration; +} + +PUGI__FN bool allow_insert_child(xml_node_type parent, xml_node_type child) { + if (parent != node_document && parent != node_element) + return false; + if (child == node_document || child == node_null) + return false; + if (parent != node_document && + (child == node_declaration || child == node_doctype)) + return false; + + return true; +} + +PUGI__FN bool allow_move(xml_node parent, xml_node child) { + // check that child can be a child of parent + if (!allow_insert_child(parent.type(), child.type())) + return false; + + // check that node is not moved between documents + if (parent.root() != child.root()) + return false; + + // check that new parent is not in the child subtree + xml_node cur = parent; + + while (cur) { + if (cur == child) + return false; + + cur = cur.parent(); + } + + return true; +} + +template +PUGI__FN void node_copy_string(String &dest, Header &header, + uintptr_t header_mask, char_t *source, + Header &source_header, xml_allocator *alloc) { + assert(!dest && (header & header_mask) == 0); + + if (source) { + if (alloc && (source_header & header_mask) == 0) { + dest = source; + + // since strcpy_insitu can reuse document buffer memory we need to mark + // both source and dest as shared + header |= xml_memory_page_contents_shared_mask; + source_header |= xml_memory_page_contents_shared_mask; + } else + strcpy_insitu(dest, header, header_mask, source, strlength(source)); + } +} + +PUGI__FN void node_copy_contents(xml_node_struct *dn, xml_node_struct *sn, + xml_allocator *shared_alloc) { + node_copy_string(dn->name, dn->header, xml_memory_page_name_allocated_mask, + sn->name, sn->header, shared_alloc); + node_copy_string(dn->value, dn->header, xml_memory_page_value_allocated_mask, + sn->value, sn->header, shared_alloc); + + for (xml_attribute_struct *sa = sn->first_attribute; sa; + sa = sa->next_attribute) { + xml_attribute_struct *da = append_new_attribute(dn, get_allocator(dn)); + + if (da) { + node_copy_string(da->name, da->header, + xml_memory_page_name_allocated_mask, sa->name, + sa->header, shared_alloc); + node_copy_string(da->value, da->header, + xml_memory_page_value_allocated_mask, sa->value, + sa->header, shared_alloc); + } + } +} + +PUGI__FN void node_copy_tree(xml_node_struct *dn, xml_node_struct *sn) { + xml_allocator &alloc = get_allocator(dn); + xml_allocator *shared_alloc = (&alloc == &get_allocator(sn)) ? &alloc : 0; + + node_copy_contents(dn, sn, shared_alloc); + + xml_node_struct *dit = dn; + xml_node_struct *sit = sn->first_child; + + while (sit && sit != sn) { + if (sit != dn) { + xml_node_struct *copy = append_new_node(dit, alloc, PUGI__NODETYPE(sit)); + + if (copy) { + node_copy_contents(copy, sit, shared_alloc); + + if (sit->first_child) { + dit = copy; + sit = sit->first_child; + continue; + } + } + } + + // continue to the next node + do { + if (sit->next_sibling) { + sit = sit->next_sibling; + break; + } + + sit = sit->parent; + dit = dit->parent; + } while (sit != sn); + } +} + +PUGI__FN void node_copy_attribute(xml_attribute_struct *da, + xml_attribute_struct *sa) { + xml_allocator &alloc = get_allocator(da); + xml_allocator *shared_alloc = (&alloc == &get_allocator(sa)) ? &alloc : 0; + + node_copy_string(da->name, da->header, xml_memory_page_name_allocated_mask, + sa->name, sa->header, shared_alloc); + node_copy_string(da->value, da->header, xml_memory_page_value_allocated_mask, + sa->value, sa->header, shared_alloc); +} + +inline bool is_text_node(xml_node_struct *node) { + xml_node_type type = PUGI__NODETYPE(node); + + return type == node_pcdata || type == node_cdata; +} + +// get value with conversion functions +template +U string_to_integer(const char_t *value, U minneg, U maxpos) { + U result = 0; + const char_t *s = value; + + while (PUGI__IS_CHARTYPE(*s, ct_space)) + s++; + + bool negative = (*s == '-'); + + s += (*s == '+' || *s == '-'); + + bool overflow = false; + + if (s[0] == '0' && (s[1] | ' ') == 'x') { + s += 2; + + // since overflow detection relies on length of the sequence skip leading + // zeros + while (*s == '0') + s++; + + const char_t *start = s; + + for (;;) { + if (static_cast(*s - '0') < 10) + result = result * 16 + (*s - '0'); + else if (static_cast((*s | ' ') - 'a') < 6) + result = result * 16 + ((*s | ' ') - 'a' + 10); + else + break; + + s++; + } + + size_t digits = static_cast(s - start); + + overflow = digits > sizeof(U) * 2; + } else { + // since overflow detection relies on length of the sequence skip leading + // zeros + while (*s == '0') + s++; + + const char_t *start = s; + + for (;;) { + if (static_cast(*s - '0') < 10) + result = result * 10 + (*s - '0'); + else + break; + + s++; + } + + size_t digits = static_cast(s - start); + + PUGI__STATIC_ASSERT(sizeof(U) == 8 || sizeof(U) == 4 || sizeof(U) == 2); + + const size_t max_digits10 = sizeof(U) == 8 ? 20 : sizeof(U) == 4 ? 10 : 5; + const char_t max_lead = sizeof(U) == 8 ? '1' : sizeof(U) == 4 ? '4' : '6'; + const size_t high_bit = sizeof(U) * 8 - 1; + + overflow = + digits >= max_digits10 && + !(digits == max_digits10 && + (*start < max_lead || (*start == max_lead && result >> high_bit))); + } + + if (negative) + return (overflow || result > minneg) ? 0 - minneg : 0 - result; + else + return (overflow || result > maxpos) ? maxpos : result; +} + +PUGI__FN int get_value_int(const char_t *value) { + return string_to_integer( + value, 0 - static_cast(INT_MIN), INT_MAX); +} + +PUGI__FN unsigned int get_value_uint(const char_t *value) { + return string_to_integer(value, 0, UINT_MAX); +} + +PUGI__FN double get_value_double(const char_t *value) { +#ifdef PUGIXML_WCHAR_MODE + return wcstod(value, 0); +#else + return strtod(value, 0); +#endif +} + +PUGI__FN float get_value_float(const char_t *value) { +#ifdef PUGIXML_WCHAR_MODE + return static_cast(wcstod(value, 0)); +#else + return static_cast(strtod(value, 0)); +#endif +} + +PUGI__FN bool get_value_bool(const char_t *value) { + // only look at first char + char_t first = *value; + + // 1*, t* (true), T* (True), y* (yes), Y* (YES) + return (first == '1' || first == 't' || first == 'T' || first == 'y' || + first == 'Y'); +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN long long get_value_llong(const char_t *value) { + return string_to_integer( + value, 0 - static_cast(LLONG_MIN), LLONG_MAX); +} + +PUGI__FN unsigned long long get_value_ullong(const char_t *value) { + return string_to_integer(value, 0, ULLONG_MAX); +} +#endif + +template +PUGI__FN char_t *integer_to_string(char_t *begin, char_t *end, U value, + bool negative) { + char_t *result = end - 1; + U rest = negative ? 0 - value : value; + + do { + *result-- = static_cast('0' + (rest % 10)); + rest /= 10; + } while (rest); + + assert(result >= begin); + (void)begin; + + *result = '-'; + + return result + !negative; +} + +// set value with conversion functions +template +PUGI__FN bool set_value_ascii(String &dest, Header &header, + uintptr_t header_mask, char *buf) { +#ifdef PUGIXML_WCHAR_MODE + char_t wbuf[128]; + assert(strlen(buf) < sizeof(wbuf) / sizeof(wbuf[0])); + + size_t offset = 0; + for (; buf[offset]; ++offset) + wbuf[offset] = buf[offset]; + + return strcpy_insitu(dest, header, header_mask, wbuf, offset); +#else + return strcpy_insitu(dest, header, header_mask, buf, strlen(buf)); +#endif +} + +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, int value) { + char_t buf[64]; + char_t *end = buf + sizeof(buf) / sizeof(buf[0]); + char_t *begin = integer_to_string(buf, end, value, value < 0); + + return strcpy_insitu(dest, header, header_mask, begin, end - begin); +} + +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, unsigned int value) { + char_t buf[64]; + char_t *end = buf + sizeof(buf) / sizeof(buf[0]); + char_t *begin = integer_to_string(buf, end, value, false); + + return strcpy_insitu(dest, header, header_mask, begin, end - begin); +} + +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, float value) { + char buf[128]; + sprintf(buf, "%.9g", value); + + return set_value_ascii(dest, header, header_mask, buf); +} + +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, double value) { + char buf[128]; + sprintf(buf, "%.17g", value); + + return set_value_ascii(dest, header, header_mask, buf); +} + +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, bool value) { + return strcpy_insitu(dest, header, header_mask, + value ? PUGIXML_TEXT("true") : PUGIXML_TEXT("false"), + value ? 4 : 5); +} + +#ifdef PUGIXML_HAS_LONG_LONG +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, long long value) { + char_t buf[64]; + char_t *end = buf + sizeof(buf) / sizeof(buf[0]); + char_t *begin = + integer_to_string(buf, end, value, value < 0); + + return strcpy_insitu(dest, header, header_mask, begin, end - begin); +} + +template +PUGI__FN bool set_value_convert(String &dest, Header &header, + uintptr_t header_mask, + unsigned long long value) { + char_t buf[64]; + char_t *end = buf + sizeof(buf) / sizeof(buf[0]); + char_t *begin = integer_to_string(buf, end, value, false); + + return strcpy_insitu(dest, header, header_mask, begin, end - begin); +} +#endif + +PUGI__FN xml_parse_result load_buffer_impl( + xml_document_struct *doc, xml_node_struct *root, void *contents, + size_t size, unsigned int options, xml_encoding encoding, bool is_mutable, + bool own, char_t **out_buffer) { + // check input buffer + if (!contents && size) + return make_parse_result(status_io_error); + + // get actual encoding + xml_encoding buffer_encoding = + impl::get_buffer_encoding(encoding, contents, size); + + // get private buffer + char_t *buffer = 0; + size_t length = 0; + + if (!impl::convert_buffer(buffer, length, buffer_encoding, contents, size, + is_mutable)) + return impl::make_parse_result(status_out_of_memory); + + // delete original buffer if we performed a conversion + if (own && buffer != contents && contents) + impl::xml_memory::deallocate(contents); + + // grab onto buffer if it's our buffer, user is responsible for deallocating + // contents himself + if (own || buffer != contents) + *out_buffer = buffer; + + // store buffer for offset_debug + doc->buffer = buffer; + + // parse + xml_parse_result res = + impl::xml_parser::parse(buffer, length, doc, root, options); + + // remember encoding + res.encoding = buffer_encoding; + + return res; +} + +// we need to get length of entire file to load it in memory; the only +// (relatively) sane way to do it is via seek/tell trick +PUGI__FN xml_parse_status get_file_size(FILE *file, size_t &out_result) { +#if defined(PUGI__MSVC_CRT_VERSION) && PUGI__MSVC_CRT_VERSION >= 1400 && \ + !defined(_WIN32_WCE) + // there are 64-bit versions of fseek/ftell, let's use them + typedef __int64 length_type; + + _fseeki64(file, 0, SEEK_END); + length_type length = _ftelli64(file); + _fseeki64(file, 0, SEEK_SET); +#elif defined(__MINGW32__) && !defined(__NO_MINGW_LFS) && \ + (!defined(__STRICT_ANSI__) || defined(__MINGW64_VERSION_MAJOR)) + // there are 64-bit versions of fseek/ftell, let's use them + typedef off64_t length_type; + + fseeko64(file, 0, SEEK_END); + length_type length = ftello64(file); + fseeko64(file, 0, SEEK_SET); +#else + // if this is a 32-bit OS, long is enough; if this is a unix system, long is + // 64-bit, which is enough; otherwise we can't do anything anyway. + typedef long length_type; + + fseek(file, 0, SEEK_END); + length_type length = ftell(file); + fseek(file, 0, SEEK_SET); +#endif + + // check for I/O errors + if (length < 0) + return status_io_error; + + // check for overflow + size_t result = static_cast(length); + + if (static_cast(result) != length) + return status_out_of_memory; + + // finalize + out_result = result; + + return status_ok; +} + +// This function assumes that buffer has extra sizeof(char_t) writable bytes +// after size +PUGI__FN size_t zero_terminate_buffer(void *buffer, size_t size, + xml_encoding encoding) { + // We only need to zero-terminate if encoding conversion does not do it for us +#ifdef PUGIXML_WCHAR_MODE + xml_encoding wchar_encoding = get_wchar_encoding(); + + if (encoding == wchar_encoding || + need_endian_swap_utf(encoding, wchar_encoding)) { + size_t length = size / sizeof(char_t); + + static_cast(buffer)[length] = 0; + return (length + 1) * sizeof(char_t); + } +#else + if (encoding == encoding_utf8) { + static_cast(buffer)[size] = 0; + return size + 1; + } +#endif + + return size; +} + +PUGI__FN xml_parse_result load_file_impl(xml_document_struct *doc, FILE *file, + unsigned int options, + xml_encoding encoding, + char_t **out_buffer) { + if (!file) + return make_parse_result(status_file_not_found); + + // get file size (can result in I/O errors) + size_t size = 0; + xml_parse_status size_status = get_file_size(file, size); + if (size_status != status_ok) + return make_parse_result(size_status); + + size_t max_suffix_size = sizeof(char_t); + + // allocate buffer for the whole file + char *contents = + static_cast(xml_memory::allocate(size + max_suffix_size)); + if (!contents) + return make_parse_result(status_out_of_memory); + + // read file in memory + size_t read_size = fread(contents, 1, size, file); + + if (read_size != size) { + xml_memory::deallocate(contents); + return make_parse_result(status_io_error); + } + + xml_encoding real_encoding = get_buffer_encoding(encoding, contents, size); + + return load_buffer_impl(doc, doc, contents, + zero_terminate_buffer(contents, size, real_encoding), + options, real_encoding, true, true, out_buffer); +} + +#ifndef PUGIXML_NO_STL +template struct xml_stream_chunk { + static xml_stream_chunk *create() { + void *memory = xml_memory::allocate(sizeof(xml_stream_chunk)); + if (!memory) + return 0; + + return new (memory) xml_stream_chunk(); + } + + static void destroy(xml_stream_chunk *chunk) { + // free chunk chain + while (chunk) { + xml_stream_chunk *next_ = chunk->next; + + xml_memory::deallocate(chunk); + + chunk = next_; + } + } + + xml_stream_chunk() : next(0), size(0) {} + + xml_stream_chunk *next; + size_t size; + + T data[xml_memory_page_size / sizeof(T)]; +}; + +template +PUGI__FN xml_parse_status load_stream_data_noseek(std::basic_istream &stream, + void **out_buffer, + size_t *out_size) { + auto_deleter> chunks(0, xml_stream_chunk::destroy); + + // read file to a chunk list + size_t total = 0; + xml_stream_chunk *last = 0; + + while (!stream.eof()) { + // allocate new chunk + xml_stream_chunk *chunk = xml_stream_chunk::create(); + if (!chunk) + return status_out_of_memory; + + // append chunk to list + if (last) + last = last->next = chunk; + else + chunks.data = last = chunk; + + // read data to chunk + stream.read(chunk->data, + static_cast(sizeof(chunk->data) / sizeof(T))); + chunk->size = static_cast(stream.gcount()) * sizeof(T); + + // read may set failbit | eofbit in case gcount() is less than read length, + // so check for other I/O errors + if (stream.bad() || (!stream.eof() && stream.fail())) + return status_io_error; + + // guard against huge files (chunk size is small enough to make this + // overflow check work) + if (total + chunk->size < total) + return status_out_of_memory; + total += chunk->size; + } + + size_t max_suffix_size = sizeof(char_t); + + // copy chunk list to a contiguous buffer + char *buffer = + static_cast(xml_memory::allocate(total + max_suffix_size)); + if (!buffer) + return status_out_of_memory; + + char *write = buffer; + + for (xml_stream_chunk *chunk = chunks.data; chunk; chunk = chunk->next) { + assert(write + chunk->size <= buffer + total); + memcpy(write, chunk->data, chunk->size); + write += chunk->size; + } + + assert(write == buffer + total); + + // return buffer + *out_buffer = buffer; + *out_size = total; + + return status_ok; +} + +template +PUGI__FN xml_parse_status load_stream_data_seek(std::basic_istream &stream, + void **out_buffer, + size_t *out_size) { + // get length of remaining data in stream + typename std::basic_istream::pos_type pos = stream.tellg(); + stream.seekg(0, std::ios::end); + std::streamoff length = stream.tellg() - pos; + stream.seekg(pos); + + if (stream.fail() || pos < 0) + return status_io_error; + + // guard against huge files + size_t read_length = static_cast(length); + + if (static_cast(read_length) != length || length < 0) + return status_out_of_memory; + + size_t max_suffix_size = sizeof(char_t); + + // read stream data into memory (guard against stream exceptions with buffer + // holder) + auto_deleter buffer( + xml_memory::allocate(read_length * sizeof(T) + max_suffix_size), + xml_memory::deallocate); + if (!buffer.data) + return status_out_of_memory; + + stream.read(static_cast(buffer.data), + static_cast(read_length)); + + // read may set failbit | eofbit in case gcount() is less than read_length + // (i.e. line ending conversion), so check for other I/O errors + if (stream.bad() || (!stream.eof() && stream.fail())) + return status_io_error; + + // return buffer + size_t actual_length = static_cast(stream.gcount()); + assert(actual_length <= read_length); + + *out_buffer = buffer.release(); + *out_size = actual_length * sizeof(T); + + return status_ok; +} + +template +PUGI__FN xml_parse_result load_stream_impl(xml_document_struct *doc, + std::basic_istream &stream, + unsigned int options, + xml_encoding encoding, + char_t **out_buffer) { + void *buffer = 0; + size_t size = 0; + xml_parse_status status = status_ok; + + // if stream has an error bit set, bail out (otherwise tellg() can fail and + // we'll clear error bits) + if (stream.fail()) + return make_parse_result(status_io_error); + + // load stream to memory (using seek-based implementation if possible, since + // it's faster and takes less memory) + if (stream.tellg() < 0) { + stream.clear(); // clear error flags that could be set by a failing tellg + status = load_stream_data_noseek(stream, &buffer, &size); + } else + status = load_stream_data_seek(stream, &buffer, &size); + + if (status != status_ok) + return make_parse_result(status); + + xml_encoding real_encoding = get_buffer_encoding(encoding, buffer, size); + + return load_buffer_impl(doc, doc, buffer, + zero_terminate_buffer(buffer, size, real_encoding), + options, real_encoding, true, true, out_buffer); +} +#endif + +#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) || \ + (defined(__MINGW32__) && \ + (!defined(__STRICT_ANSI__) || defined(__MINGW64_VERSION_MAJOR))) +PUGI__FN FILE *open_file_wide(const wchar_t *path, const wchar_t *mode) { + return _wfopen(path, mode); +} +#else +PUGI__FN char *convert_path_heap(const wchar_t *str) { + assert(str); + + // first pass: get length in utf8 characters + size_t length = strlength_wide(str); + size_t size = as_utf8_begin(str, length); + + // allocate resulting string + char *result = static_cast(xml_memory::allocate(size + 1)); + if (!result) + return 0; + + // second pass: convert to utf8 + as_utf8_end(result, size, str, length); + + // zero-terminate + result[size] = 0; + + return result; +} + +PUGI__FN FILE *open_file_wide(const wchar_t *path, const wchar_t *mode) { + // there is no standard function to open wide paths, so our best bet is to try + // utf8 path + char *path_utf8 = convert_path_heap(path); + if (!path_utf8) + return 0; + + // convert mode to ASCII (we mirror _wfopen interface) + char mode_ascii[4] = {0}; + for (size_t i = 0; mode[i]; ++i) + mode_ascii[i] = static_cast(mode[i]); + + // try to open the utf8 path + FILE *result = fopen(path_utf8, mode_ascii); + + // free dummy buffer + xml_memory::deallocate(path_utf8); + + return result; +} +#endif + +PUGI__FN bool save_file_impl(const xml_document &doc, FILE *file, + const char_t *indent, unsigned int flags, + xml_encoding encoding) { + if (!file) + return false; + + xml_writer_file writer(file); + doc.save(writer, indent, flags, encoding); + + return ferror(file) == 0; +} + +struct name_null_sentry { + xml_node_struct *node; + char_t *name; + + name_null_sentry(xml_node_struct *node_) : node(node_), name(node_->name) { + node->name = 0; + } + + ~name_null_sentry() { node->name = name; } +}; +PUGI__NS_END + +namespace pugi { +PUGI__FN xml_writer_file::xml_writer_file(void *file_) : file(file_) {} + +PUGI__FN void xml_writer_file::write(const void *data, size_t size) { + size_t result = fwrite(data, 1, size, static_cast(file)); + (void)!result; // unfortunately we can't do proper error handling here +} + +#ifndef PUGIXML_NO_STL +PUGI__FN xml_writer_stream::xml_writer_stream( + std::basic_ostream> &stream) + : narrow_stream(&stream), wide_stream(0) {} + +PUGI__FN xml_writer_stream::xml_writer_stream( + std::basic_ostream> &stream) + : narrow_stream(0), wide_stream(&stream) {} + +PUGI__FN void xml_writer_stream::write(const void *data, size_t size) { + if (narrow_stream) { + assert(!wide_stream); + narrow_stream->write(reinterpret_cast(data), + static_cast(size)); + } else { + assert(wide_stream); + assert(size % sizeof(wchar_t) == 0); + + wide_stream->write(reinterpret_cast(data), + static_cast(size / sizeof(wchar_t))); + } +} +#endif + +PUGI__FN xml_tree_walker::xml_tree_walker() : _depth(0) {} + +PUGI__FN xml_tree_walker::~xml_tree_walker() {} + +PUGI__FN int xml_tree_walker::depth() const { return _depth; } + +PUGI__FN bool xml_tree_walker::begin(xml_node &) { return true; } + +PUGI__FN bool xml_tree_walker::end(xml_node &) { return true; } + +PUGI__FN xml_attribute::xml_attribute() : _attr(0) {} + +PUGI__FN xml_attribute::xml_attribute(xml_attribute_struct *attr) + : _attr(attr) {} + +PUGI__FN static void unspecified_bool_xml_attribute(xml_attribute ***) {} + +PUGI__FN xml_attribute::operator xml_attribute::unspecified_bool_type() const { + return _attr ? unspecified_bool_xml_attribute : 0; +} + +PUGI__FN bool xml_attribute::operator!() const { return !_attr; } + +PUGI__FN bool xml_attribute::operator==(const xml_attribute &r) const { + return (_attr == r._attr); +} + +PUGI__FN bool xml_attribute::operator!=(const xml_attribute &r) const { + return (_attr != r._attr); +} + +PUGI__FN bool xml_attribute::operator<(const xml_attribute &r) const { + return (_attr < r._attr); +} + +PUGI__FN bool xml_attribute::operator>(const xml_attribute &r) const { + return (_attr > r._attr); +} + +PUGI__FN bool xml_attribute::operator<=(const xml_attribute &r) const { + return (_attr <= r._attr); +} + +PUGI__FN bool xml_attribute::operator>=(const xml_attribute &r) const { + return (_attr >= r._attr); +} + +PUGI__FN xml_attribute xml_attribute::next_attribute() const { + return _attr ? xml_attribute(_attr->next_attribute) : xml_attribute(); +} + +PUGI__FN xml_attribute xml_attribute::previous_attribute() const { + return _attr && _attr->prev_attribute_c->next_attribute + ? xml_attribute(_attr->prev_attribute_c) + : xml_attribute(); +} + +PUGI__FN const char_t *xml_attribute::as_string(const char_t *def) const { + return (_attr && _attr->value) ? _attr->value + 0 : def; +} + +PUGI__FN int xml_attribute::as_int(int def) const { + return (_attr && _attr->value) ? impl::get_value_int(_attr->value) : def; +} + +PUGI__FN unsigned int xml_attribute::as_uint(unsigned int def) const { + return (_attr && _attr->value) ? impl::get_value_uint(_attr->value) : def; +} + +PUGI__FN double xml_attribute::as_double(double def) const { + return (_attr && _attr->value) ? impl::get_value_double(_attr->value) : def; +} + +PUGI__FN float xml_attribute::as_float(float def) const { + return (_attr && _attr->value) ? impl::get_value_float(_attr->value) : def; +} + +PUGI__FN bool xml_attribute::as_bool(bool def) const { + return (_attr && _attr->value) ? impl::get_value_bool(_attr->value) : def; +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN long long xml_attribute::as_llong(long long def) const { + return (_attr && _attr->value) ? impl::get_value_llong(_attr->value) : def; +} + +PUGI__FN unsigned long long +xml_attribute::as_ullong(unsigned long long def) const { + return (_attr && _attr->value) ? impl::get_value_ullong(_attr->value) : def; +} +#endif + +PUGI__FN bool xml_attribute::empty() const { return !_attr; } + +PUGI__FN const char_t *xml_attribute::name() const { + return (_attr && _attr->name) ? _attr->name + 0 : PUGIXML_TEXT(""); +} + +PUGI__FN const char_t *xml_attribute::value() const { + return (_attr && _attr->value) ? _attr->value + 0 : PUGIXML_TEXT(""); +} + +PUGI__FN size_t xml_attribute::hash_value() const { + return static_cast(reinterpret_cast(_attr) / + sizeof(xml_attribute_struct)); +} + +PUGI__FN xml_attribute_struct *xml_attribute::internal_object() const { + return _attr; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(const char_t *rhs) { + set_value(rhs); + return *this; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(int rhs) { + set_value(rhs); + return *this; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(unsigned int rhs) { + set_value(rhs); + return *this; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(double rhs) { + set_value(rhs); + return *this; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(float rhs) { + set_value(rhs); + return *this; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(bool rhs) { + set_value(rhs); + return *this; +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN xml_attribute &xml_attribute::operator=(long long rhs) { + set_value(rhs); + return *this; +} + +PUGI__FN xml_attribute &xml_attribute::operator=(unsigned long long rhs) { + set_value(rhs); + return *this; +} +#endif + +PUGI__FN bool xml_attribute::set_name(const char_t *rhs) { + if (!_attr) + return false; + + return impl::strcpy_insitu(_attr->name, _attr->header, + impl::xml_memory_page_name_allocated_mask, rhs, + impl::strlength(rhs)); +} + +PUGI__FN bool xml_attribute::set_value(const char_t *rhs) { + if (!_attr) + return false; + + return impl::strcpy_insitu(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, rhs, + impl::strlength(rhs)); +} + +PUGI__FN bool xml_attribute::set_value(int rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} + +PUGI__FN bool xml_attribute::set_value(unsigned int rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} + +PUGI__FN bool xml_attribute::set_value(double rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} + +PUGI__FN bool xml_attribute::set_value(float rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} + +PUGI__FN bool xml_attribute::set_value(bool rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN bool xml_attribute::set_value(long long rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} + +PUGI__FN bool xml_attribute::set_value(unsigned long long rhs) { + if (!_attr) + return false; + + return impl::set_value_convert(_attr->value, _attr->header, + impl::xml_memory_page_value_allocated_mask, + rhs); +} +#endif + +#ifdef __BORLANDC__ +PUGI__FN bool operator&&(const xml_attribute &lhs, bool rhs) { + return (bool)lhs && rhs; +} + +PUGI__FN bool operator||(const xml_attribute &lhs, bool rhs) { + return (bool)lhs || rhs; +} +#endif + +PUGI__FN xml_node::xml_node() : _root(0) {} + +PUGI__FN xml_node::xml_node(xml_node_struct *p) : _root(p) {} + +PUGI__FN static void unspecified_bool_xml_node(xml_node ***) {} + +PUGI__FN xml_node::operator xml_node::unspecified_bool_type() const { + return _root ? unspecified_bool_xml_node : 0; +} + +PUGI__FN bool xml_node::operator!() const { return !_root; } + +PUGI__FN xml_node::iterator xml_node::begin() const { + return iterator(_root ? _root->first_child + 0 : 0, _root); +} + +PUGI__FN xml_node::iterator xml_node::end() const { return iterator(0, _root); } + +PUGI__FN xml_node::attribute_iterator xml_node::attributes_begin() const { + return attribute_iterator(_root ? _root->first_attribute + 0 : 0, _root); +} + +PUGI__FN xml_node::attribute_iterator xml_node::attributes_end() const { + return attribute_iterator(0, _root); +} + +PUGI__FN xml_object_range xml_node::children() const { + return xml_object_range(begin(), end()); +} + +PUGI__FN xml_object_range +xml_node::children(const char_t *name_) const { + return xml_object_range( + xml_named_node_iterator(child(name_)._root, _root, name_), + xml_named_node_iterator(0, _root, name_)); +} + +PUGI__FN xml_object_range xml_node::attributes() const { + return xml_object_range(attributes_begin(), + attributes_end()); +} + +PUGI__FN bool xml_node::operator==(const xml_node &r) const { + return (_root == r._root); +} + +PUGI__FN bool xml_node::operator!=(const xml_node &r) const { + return (_root != r._root); +} + +PUGI__FN bool xml_node::operator<(const xml_node &r) const { + return (_root < r._root); +} + +PUGI__FN bool xml_node::operator>(const xml_node &r) const { + return (_root > r._root); +} + +PUGI__FN bool xml_node::operator<=(const xml_node &r) const { + return (_root <= r._root); +} + +PUGI__FN bool xml_node::operator>=(const xml_node &r) const { + return (_root >= r._root); +} + +PUGI__FN bool xml_node::empty() const { return !_root; } + +PUGI__FN const char_t *xml_node::name() const { + return (_root && _root->name) ? _root->name + 0 : PUGIXML_TEXT(""); +} + +PUGI__FN xml_node_type xml_node::type() const { + return _root ? PUGI__NODETYPE(_root) : node_null; +} + +PUGI__FN const char_t *xml_node::value() const { + return (_root && _root->value) ? _root->value + 0 : PUGIXML_TEXT(""); +} + +PUGI__FN xml_node xml_node::child(const char_t *name_) const { + if (!_root) + return xml_node(); + + for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) + if (i->name && impl::strequal(name_, i->name)) + return xml_node(i); + + return xml_node(); +} + +PUGI__FN xml_attribute xml_node::attribute(const char_t *name_) const { + if (!_root) + return xml_attribute(); + + for (xml_attribute_struct *i = _root->first_attribute; i; + i = i->next_attribute) + if (i->name && impl::strequal(name_, i->name)) + return xml_attribute(i); + + return xml_attribute(); +} + +PUGI__FN xml_node xml_node::next_sibling(const char_t *name_) const { + if (!_root) + return xml_node(); + + for (xml_node_struct *i = _root->next_sibling; i; i = i->next_sibling) + if (i->name && impl::strequal(name_, i->name)) + return xml_node(i); + + return xml_node(); +} + +PUGI__FN xml_node xml_node::next_sibling() const { + return _root ? xml_node(_root->next_sibling) : xml_node(); +} + +PUGI__FN xml_node xml_node::previous_sibling(const char_t *name_) const { + if (!_root) + return xml_node(); + + for (xml_node_struct *i = _root->prev_sibling_c; i->next_sibling; + i = i->prev_sibling_c) + if (i->name && impl::strequal(name_, i->name)) + return xml_node(i); + + return xml_node(); +} + +PUGI__FN xml_attribute xml_node::attribute(const char_t *name_, + xml_attribute &hint_) const { + xml_attribute_struct *hint = hint_._attr; + + // if hint is not an attribute of node, behavior is not defined + assert(!hint || (_root && impl::is_attribute_of(hint, _root))); + + if (!_root) + return xml_attribute(); + + // optimistically search from hint up until the end + for (xml_attribute_struct *i = hint; i; i = i->next_attribute) + if (i->name && impl::strequal(name_, i->name)) { + // update hint to maximize efficiency of searching for consecutive + // attributes + hint_._attr = i->next_attribute; + + return xml_attribute(i); + } + + // wrap around and search from the first attribute until the hint + // 'j' null pointer check is technically redundant, but it prevents a crash in + // case the assertion above fails + for (xml_attribute_struct *j = _root->first_attribute; j && j != hint; + j = j->next_attribute) + if (j->name && impl::strequal(name_, j->name)) { + // update hint to maximize efficiency of searching for consecutive + // attributes + hint_._attr = j->next_attribute; + + return xml_attribute(j); + } + + return xml_attribute(); +} + +PUGI__FN xml_node xml_node::previous_sibling() const { + if (!_root) + return xml_node(); + + if (_root->prev_sibling_c->next_sibling) + return xml_node(_root->prev_sibling_c); + else + return xml_node(); +} + +PUGI__FN xml_node xml_node::parent() const { + return _root ? xml_node(_root->parent) : xml_node(); +} + +PUGI__FN xml_node xml_node::root() const { + return _root ? xml_node(&impl::get_document(_root)) : xml_node(); +} + +PUGI__FN xml_text xml_node::text() const { return xml_text(_root); } + +PUGI__FN const char_t *xml_node::child_value() const { + if (!_root) + return PUGIXML_TEXT(""); + + for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) + if (impl::is_text_node(i) && i->value) + return i->value; + + return PUGIXML_TEXT(""); +} + +PUGI__FN const char_t *xml_node::child_value(const char_t *name_) const { + return child(name_).child_value(); +} + +PUGI__FN xml_attribute xml_node::first_attribute() const { + return _root ? xml_attribute(_root->first_attribute) : xml_attribute(); +} + +PUGI__FN xml_attribute xml_node::last_attribute() const { + return _root && _root->first_attribute + ? xml_attribute(_root->first_attribute->prev_attribute_c) + : xml_attribute(); +} + +PUGI__FN xml_node xml_node::first_child() const { + return _root ? xml_node(_root->first_child) : xml_node(); +} + +PUGI__FN xml_node xml_node::last_child() const { + return _root && _root->first_child + ? xml_node(_root->first_child->prev_sibling_c) + : xml_node(); +} + +PUGI__FN bool xml_node::set_name(const char_t *rhs) { + xml_node_type type_ = _root ? PUGI__NODETYPE(_root) : node_null; + + if (type_ != node_element && type_ != node_pi && type_ != node_declaration) + return false; + + return impl::strcpy_insitu(_root->name, _root->header, + impl::xml_memory_page_name_allocated_mask, rhs, + impl::strlength(rhs)); +} + +PUGI__FN bool xml_node::set_value(const char_t *rhs) { + xml_node_type type_ = _root ? PUGI__NODETYPE(_root) : node_null; + + if (type_ != node_pcdata && type_ != node_cdata && type_ != node_comment && + type_ != node_pi && type_ != node_doctype) + return false; + + return impl::strcpy_insitu(_root->value, _root->header, + impl::xml_memory_page_value_allocated_mask, rhs, + impl::strlength(rhs)); +} + +PUGI__FN xml_attribute xml_node::append_attribute(const char_t *name_) { + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::append_attribute(a._attr, _root); + + a.set_name(name_); + + return a; +} + +PUGI__FN xml_attribute xml_node::prepend_attribute(const char_t *name_) { + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::prepend_attribute(a._attr, _root); + + a.set_name(name_); + + return a; +} + +PUGI__FN xml_attribute xml_node::insert_attribute_after( + const char_t *name_, const xml_attribute &attr) { + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + if (!attr || !impl::is_attribute_of(attr._attr, _root)) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::insert_attribute_after(a._attr, attr._attr, _root); + + a.set_name(name_); + + return a; +} + +PUGI__FN xml_attribute xml_node::insert_attribute_before( + const char_t *name_, const xml_attribute &attr) { + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + if (!attr || !impl::is_attribute_of(attr._attr, _root)) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::insert_attribute_before(a._attr, attr._attr, _root); + + a.set_name(name_); + + return a; +} + +PUGI__FN xml_attribute xml_node::append_copy(const xml_attribute &proto) { + if (!proto) + return xml_attribute(); + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::append_attribute(a._attr, _root); + impl::node_copy_attribute(a._attr, proto._attr); + + return a; +} + +PUGI__FN xml_attribute xml_node::prepend_copy(const xml_attribute &proto) { + if (!proto) + return xml_attribute(); + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::prepend_attribute(a._attr, _root); + impl::node_copy_attribute(a._attr, proto._attr); + + return a; +} + +PUGI__FN xml_attribute xml_node::insert_copy_after(const xml_attribute &proto, + const xml_attribute &attr) { + if (!proto) + return xml_attribute(); + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + if (!attr || !impl::is_attribute_of(attr._attr, _root)) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::insert_attribute_after(a._attr, attr._attr, _root); + impl::node_copy_attribute(a._attr, proto._attr); + + return a; +} + +PUGI__FN xml_attribute xml_node::insert_copy_before(const xml_attribute &proto, + const xml_attribute &attr) { + if (!proto) + return xml_attribute(); + if (!impl::allow_insert_attribute(type())) + return xml_attribute(); + if (!attr || !impl::is_attribute_of(attr._attr, _root)) + return xml_attribute(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_attribute(); + + xml_attribute a(impl::allocate_attribute(alloc)); + if (!a) + return xml_attribute(); + + impl::insert_attribute_before(a._attr, attr._attr, _root); + impl::node_copy_attribute(a._attr, proto._attr); + + return a; +} + +PUGI__FN xml_node xml_node::append_child(xml_node_type type_) { + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::append_node(n._root, _root); + + if (type_ == node_declaration) + n.set_name(PUGIXML_TEXT("xml")); + + return n; +} + +PUGI__FN xml_node xml_node::prepend_child(xml_node_type type_) { + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::prepend_node(n._root, _root); + + if (type_ == node_declaration) + n.set_name(PUGIXML_TEXT("xml")); + + return n; +} + +PUGI__FN xml_node xml_node::insert_child_before(xml_node_type type_, + const xml_node &node) { + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + if (!node._root || node._root->parent != _root) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::insert_node_before(n._root, node._root); + + if (type_ == node_declaration) + n.set_name(PUGIXML_TEXT("xml")); + + return n; +} + +PUGI__FN xml_node xml_node::insert_child_after(xml_node_type type_, + const xml_node &node) { + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + if (!node._root || node._root->parent != _root) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::insert_node_after(n._root, node._root); + + if (type_ == node_declaration) + n.set_name(PUGIXML_TEXT("xml")); + + return n; +} + +PUGI__FN xml_node xml_node::append_child(const char_t *name_) { + xml_node result = append_child(node_element); + + result.set_name(name_); + + return result; +} + +PUGI__FN xml_node xml_node::prepend_child(const char_t *name_) { + xml_node result = prepend_child(node_element); + + result.set_name(name_); + + return result; +} + +PUGI__FN xml_node xml_node::insert_child_after(const char_t *name_, + const xml_node &node) { + xml_node result = insert_child_after(node_element, node); + + result.set_name(name_); + + return result; +} + +PUGI__FN xml_node xml_node::insert_child_before(const char_t *name_, + const xml_node &node) { + xml_node result = insert_child_before(node_element, node); + + result.set_name(name_); + + return result; +} + +PUGI__FN xml_node xml_node::append_copy(const xml_node &proto) { + xml_node_type type_ = proto.type(); + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::append_node(n._root, _root); + impl::node_copy_tree(n._root, proto._root); + + return n; +} + +PUGI__FN xml_node xml_node::prepend_copy(const xml_node &proto) { + xml_node_type type_ = proto.type(); + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::prepend_node(n._root, _root); + impl::node_copy_tree(n._root, proto._root); + + return n; +} + +PUGI__FN xml_node xml_node::insert_copy_after(const xml_node &proto, + const xml_node &node) { + xml_node_type type_ = proto.type(); + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + if (!node._root || node._root->parent != _root) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::insert_node_after(n._root, node._root); + impl::node_copy_tree(n._root, proto._root); + + return n; +} + +PUGI__FN xml_node xml_node::insert_copy_before(const xml_node &proto, + const xml_node &node) { + xml_node_type type_ = proto.type(); + if (!impl::allow_insert_child(type(), type_)) + return xml_node(); + if (!node._root || node._root->parent != _root) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + xml_node n(impl::allocate_node(alloc, type_)); + if (!n) + return xml_node(); + + impl::insert_node_before(n._root, node._root); + impl::node_copy_tree(n._root, proto._root); + + return n; +} + +PUGI__FN xml_node xml_node::append_move(const xml_node &moved) { + if (!impl::allow_move(*this, moved)) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + // disable document_buffer_order optimization since moving nodes around + // changes document order without changing buffer pointers + impl::get_document(_root).header |= + impl::xml_memory_page_contents_shared_mask; + + impl::remove_node(moved._root); + impl::append_node(moved._root, _root); + + return moved; +} + +PUGI__FN xml_node xml_node::prepend_move(const xml_node &moved) { + if (!impl::allow_move(*this, moved)) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + // disable document_buffer_order optimization since moving nodes around + // changes document order without changing buffer pointers + impl::get_document(_root).header |= + impl::xml_memory_page_contents_shared_mask; + + impl::remove_node(moved._root); + impl::prepend_node(moved._root, _root); + + return moved; +} + +PUGI__FN xml_node xml_node::insert_move_after(const xml_node &moved, + const xml_node &node) { + if (!impl::allow_move(*this, moved)) + return xml_node(); + if (!node._root || node._root->parent != _root) + return xml_node(); + if (moved._root == node._root) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + // disable document_buffer_order optimization since moving nodes around + // changes document order without changing buffer pointers + impl::get_document(_root).header |= + impl::xml_memory_page_contents_shared_mask; + + impl::remove_node(moved._root); + impl::insert_node_after(moved._root, node._root); + + return moved; +} + +PUGI__FN xml_node xml_node::insert_move_before(const xml_node &moved, + const xml_node &node) { + if (!impl::allow_move(*this, moved)) + return xml_node(); + if (!node._root || node._root->parent != _root) + return xml_node(); + if (moved._root == node._root) + return xml_node(); + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return xml_node(); + + // disable document_buffer_order optimization since moving nodes around + // changes document order without changing buffer pointers + impl::get_document(_root).header |= + impl::xml_memory_page_contents_shared_mask; + + impl::remove_node(moved._root); + impl::insert_node_before(moved._root, node._root); + + return moved; +} + +PUGI__FN bool xml_node::remove_attribute(const char_t *name_) { + return remove_attribute(attribute(name_)); +} + +PUGI__FN bool xml_node::remove_attribute(const xml_attribute &a) { + if (!_root || !a._attr) + return false; + if (!impl::is_attribute_of(a._attr, _root)) + return false; + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return false; + + impl::remove_attribute(a._attr, _root); + impl::destroy_attribute(a._attr, alloc); + + return true; +} + +PUGI__FN bool xml_node::remove_child(const char_t *name_) { + return remove_child(child(name_)); +} + +PUGI__FN bool xml_node::remove_child(const xml_node &n) { + if (!_root || !n._root || n._root->parent != _root) + return false; + + impl::xml_allocator &alloc = impl::get_allocator(_root); + if (!alloc.reserve()) + return false; + + impl::remove_node(n._root); + impl::destroy_node(n._root, alloc); + + return true; +} + +PUGI__FN xml_parse_result xml_node::append_buffer(const void *contents, + size_t size, + unsigned int options, + xml_encoding encoding) { + // append_buffer is only valid for elements/documents + if (!impl::allow_insert_child(type(), node_element)) + return impl::make_parse_result(status_append_invalid_root); + + // get document node + impl::xml_document_struct *doc = &impl::get_document(_root); + + // disable document_buffer_order optimization since in a document with + // multiple buffers comparing buffer pointers does not make sense + doc->header |= impl::xml_memory_page_contents_shared_mask; + + // get extra buffer element (we'll store the document fragment buffer there so + // that we can deallocate it later) + impl::xml_memory_page *page = 0; + impl::xml_extra_buffer *extra = static_cast( + doc->allocate_memory(sizeof(impl::xml_extra_buffer), page)); + (void)page; + + if (!extra) + return impl::make_parse_result(status_out_of_memory); + + // add extra buffer to the list + extra->buffer = 0; + extra->next = doc->extra_buffers; + doc->extra_buffers = extra; + + // name of the root has to be NULL before parsing - otherwise closing node + // mismatches will not be detected at the top level + impl::name_null_sentry sentry(_root); + + return impl::load_buffer_impl(doc, _root, const_cast(contents), size, + options, encoding, false, false, + &extra->buffer); +} + +PUGI__FN xml_node +xml_node::find_child_by_attribute(const char_t *name_, const char_t *attr_name, + const char_t *attr_value) const { + if (!_root) + return xml_node(); + + for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) + if (i->name && impl::strequal(name_, i->name)) { + for (xml_attribute_struct *a = i->first_attribute; a; + a = a->next_attribute) + if (a->name && impl::strequal(attr_name, a->name) && + impl::strequal(attr_value, + a->value ? a->value + 0 : PUGIXML_TEXT(""))) + return xml_node(i); + } + + return xml_node(); +} + +PUGI__FN xml_node xml_node::find_child_by_attribute( + const char_t *attr_name, const char_t *attr_value) const { + if (!_root) + return xml_node(); + + for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) + for (xml_attribute_struct *a = i->first_attribute; a; a = a->next_attribute) + if (a->name && impl::strequal(attr_name, a->name) && + impl::strequal(attr_value, + a->value ? a->value + 0 : PUGIXML_TEXT(""))) + return xml_node(i); + + return xml_node(); +} + +#ifndef PUGIXML_NO_STL +PUGI__FN string_t xml_node::path(char_t delimiter) const { + if (!_root) + return string_t(); + + size_t offset = 0; + + for (xml_node_struct *i = _root; i; i = i->parent) { + offset += (i != _root); + offset += i->name ? impl::strlength(i->name) : 0; + } + + string_t result; + result.resize(offset); + + for (xml_node_struct *j = _root; j; j = j->parent) { + if (j != _root) + result[--offset] = delimiter; + + if (j->name && *j->name) { + size_t length = impl::strlength(j->name); + + offset -= length; + memcpy(&result[offset], j->name, length * sizeof(char_t)); + } + } + + assert(offset == 0); + + return result; +} +#endif + +PUGI__FN xml_node xml_node::first_element_by_path(const char_t *path_, + char_t delimiter) const { + xml_node found = *this; // Current search context. + + if (!_root || !path_ || !path_[0]) + return found; + + if (path_[0] == delimiter) { + // Absolute path; e.g. '/foo/bar' + found = found.root(); + ++path_; + } + + const char_t *path_segment = path_; + + while (*path_segment == delimiter) + ++path_segment; + + const char_t *path_segment_end = path_segment; + + while (*path_segment_end && *path_segment_end != delimiter) + ++path_segment_end; + + if (path_segment == path_segment_end) + return found; + + const char_t *next_segment = path_segment_end; + + while (*next_segment == delimiter) + ++next_segment; + + if (*path_segment == '.' && path_segment + 1 == path_segment_end) + return found.first_element_by_path(next_segment, delimiter); + else if (*path_segment == '.' && *(path_segment + 1) == '.' && + path_segment + 2 == path_segment_end) + return found.parent().first_element_by_path(next_segment, delimiter); + else { + for (xml_node_struct *j = found._root->first_child; j; + j = j->next_sibling) { + if (j->name && impl::strequalrange(j->name, path_segment, + static_cast(path_segment_end - + path_segment))) { + xml_node subsearch = + xml_node(j).first_element_by_path(next_segment, delimiter); + + if (subsearch) + return subsearch; + } + } + + return xml_node(); + } +} + +PUGI__FN bool xml_node::traverse(xml_tree_walker &walker) { + walker._depth = -1; + + xml_node arg_begin = *this; + if (!walker.begin(arg_begin)) + return false; + + xml_node cur = first_child(); + + if (cur) { + ++walker._depth; + + do { + xml_node arg_for_each = cur; + if (!walker.for_each(arg_for_each)) + return false; + + if (cur.first_child()) { + ++walker._depth; + cur = cur.first_child(); + } else if (cur.next_sibling()) + cur = cur.next_sibling(); + else { + // Borland C++ workaround + while (!cur.next_sibling() && cur != *this && !cur.parent().empty()) { + --walker._depth; + cur = cur.parent(); + } + + if (cur != *this) + cur = cur.next_sibling(); + } + } while (cur && cur != *this); + } + + assert(walker._depth == -1); + + xml_node arg_end = *this; + return walker.end(arg_end); +} + +PUGI__FN size_t xml_node::hash_value() const { + return static_cast(reinterpret_cast(_root) / + sizeof(xml_node_struct)); +} + +PUGI__FN xml_node_struct *xml_node::internal_object() const { return _root; } + +PUGI__FN void xml_node::print(xml_writer &writer, const char_t *indent, + unsigned int flags, xml_encoding encoding, + unsigned int depth) const { + if (!_root) + return; + + impl::xml_buffered_writer buffered_writer(writer, encoding); + + impl::node_output(buffered_writer, _root, indent, flags, depth); + + buffered_writer.flush(); +} + +#ifndef PUGIXML_NO_STL +PUGI__FN void +xml_node::print(std::basic_ostream> &stream, + const char_t *indent, unsigned int flags, xml_encoding encoding, + unsigned int depth) const { + xml_writer_stream writer(stream); + + print(writer, indent, flags, encoding, depth); +} + +PUGI__FN void +xml_node::print(std::basic_ostream> &stream, + const char_t *indent, unsigned int flags, + unsigned int depth) const { + xml_writer_stream writer(stream); + + print(writer, indent, flags, encoding_wchar, depth); +} +#endif + +PUGI__FN ptrdiff_t xml_node::offset_debug() const { + if (!_root) + return -1; + + impl::xml_document_struct &doc = impl::get_document(_root); + + // we can determine the offset reliably only if there is exactly once parse + // buffer + if (!doc.buffer || doc.extra_buffers) + return -1; + + switch (type()) { + case node_document: + return 0; + + case node_element: + case node_declaration: + case node_pi: + return _root->name && + (_root->header & + impl::xml_memory_page_name_allocated_or_shared_mask) == 0 + ? _root->name - doc.buffer + : -1; + + case node_pcdata: + case node_cdata: + case node_comment: + case node_doctype: + return _root->value && + (_root->header & + impl::xml_memory_page_value_allocated_or_shared_mask) == 0 + ? _root->value - doc.buffer + : -1; + + default: + return -1; + } +} + +#ifdef __BORLANDC__ +PUGI__FN bool operator&&(const xml_node &lhs, bool rhs) { + return (bool)lhs && rhs; +} + +PUGI__FN bool operator||(const xml_node &lhs, bool rhs) { + return (bool)lhs || rhs; +} +#endif + +PUGI__FN xml_text::xml_text(xml_node_struct *root) : _root(root) {} + +PUGI__FN xml_node_struct *xml_text::_data() const { + if (!_root || impl::is_text_node(_root)) + return _root; + + for (xml_node_struct *node = _root->first_child; node; + node = node->next_sibling) + if (impl::is_text_node(node)) + return node; + + return 0; +} + +PUGI__FN xml_node_struct *xml_text::_data_new() { + xml_node_struct *d = _data(); + if (d) + return d; + + return xml_node(_root).append_child(node_pcdata).internal_object(); +} + +PUGI__FN xml_text::xml_text() : _root(0) {} + +PUGI__FN static void unspecified_bool_xml_text(xml_text ***) {} + +PUGI__FN xml_text::operator xml_text::unspecified_bool_type() const { + return _data() ? unspecified_bool_xml_text : 0; +} + +PUGI__FN bool xml_text::operator!() const { return !_data(); } + +PUGI__FN bool xml_text::empty() const { return _data() == 0; } + +PUGI__FN const char_t *xml_text::get() const { + xml_node_struct *d = _data(); + + return (d && d->value) ? d->value + 0 : PUGIXML_TEXT(""); +} + +PUGI__FN const char_t *xml_text::as_string(const char_t *def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? d->value + 0 : def; +} + +PUGI__FN int xml_text::as_int(int def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_int(d->value) : def; +} + +PUGI__FN unsigned int xml_text::as_uint(unsigned int def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_uint(d->value) : def; +} + +PUGI__FN double xml_text::as_double(double def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_double(d->value) : def; +} + +PUGI__FN float xml_text::as_float(float def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_float(d->value) : def; +} + +PUGI__FN bool xml_text::as_bool(bool def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_bool(d->value) : def; +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN long long xml_text::as_llong(long long def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_llong(d->value) : def; +} + +PUGI__FN unsigned long long xml_text::as_ullong(unsigned long long def) const { + xml_node_struct *d = _data(); + + return (d && d->value) ? impl::get_value_ullong(d->value) : def; +} +#endif + +PUGI__FN bool xml_text::set(const char_t *rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::strcpy_insitu(dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, + rhs, impl::strlength(rhs)) + : false; +} + +PUGI__FN bool xml_text::set(int rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} + +PUGI__FN bool xml_text::set(unsigned int rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} + +PUGI__FN bool xml_text::set(float rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} + +PUGI__FN bool xml_text::set(double rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} + +PUGI__FN bool xml_text::set(bool rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN bool xml_text::set(long long rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} + +PUGI__FN bool xml_text::set(unsigned long long rhs) { + xml_node_struct *dn = _data_new(); + + return dn ? impl::set_value_convert( + dn->value, dn->header, + impl::xml_memory_page_value_allocated_mask, rhs) + : false; +} +#endif + +PUGI__FN xml_text &xml_text::operator=(const char_t *rhs) { + set(rhs); + return *this; +} + +PUGI__FN xml_text &xml_text::operator=(int rhs) { + set(rhs); + return *this; +} + +PUGI__FN xml_text &xml_text::operator=(unsigned int rhs) { + set(rhs); + return *this; +} + +PUGI__FN xml_text &xml_text::operator=(double rhs) { + set(rhs); + return *this; +} + +PUGI__FN xml_text &xml_text::operator=(float rhs) { + set(rhs); + return *this; +} + +PUGI__FN xml_text &xml_text::operator=(bool rhs) { + set(rhs); + return *this; +} + +#ifdef PUGIXML_HAS_LONG_LONG +PUGI__FN xml_text &xml_text::operator=(long long rhs) { + set(rhs); + return *this; +} + +PUGI__FN xml_text &xml_text::operator=(unsigned long long rhs) { + set(rhs); + return *this; +} +#endif + +PUGI__FN xml_node xml_text::data() const { return xml_node(_data()); } + +#ifdef __BORLANDC__ +PUGI__FN bool operator&&(const xml_text &lhs, bool rhs) { + return (bool)lhs && rhs; +} + +PUGI__FN bool operator||(const xml_text &lhs, bool rhs) { + return (bool)lhs || rhs; +} +#endif + +PUGI__FN xml_node_iterator::xml_node_iterator() {} + +PUGI__FN xml_node_iterator::xml_node_iterator(const xml_node &node) + : _wrap(node), _parent(node.parent()) {} + +PUGI__FN xml_node_iterator::xml_node_iterator(xml_node_struct *ref, + xml_node_struct *parent) + : _wrap(ref), _parent(parent) {} + +PUGI__FN bool +xml_node_iterator::operator==(const xml_node_iterator &rhs) const { + return _wrap._root == rhs._wrap._root && _parent._root == rhs._parent._root; +} + +PUGI__FN bool +xml_node_iterator::operator!=(const xml_node_iterator &rhs) const { + return _wrap._root != rhs._wrap._root || _parent._root != rhs._parent._root; +} + +PUGI__FN xml_node &xml_node_iterator::operator*() const { + assert(_wrap._root); + return _wrap; +} + +PUGI__FN xml_node *xml_node_iterator::operator->() const { + assert(_wrap._root); + return const_cast(&_wrap); // BCC32 workaround +} + +PUGI__FN const xml_node_iterator &xml_node_iterator::operator++() { + assert(_wrap._root); + _wrap._root = _wrap._root->next_sibling; + return *this; +} + +PUGI__FN xml_node_iterator xml_node_iterator::operator++(int) { + xml_node_iterator temp = *this; + ++*this; + return temp; +} + +PUGI__FN const xml_node_iterator &xml_node_iterator::operator--() { + _wrap = _wrap._root ? _wrap.previous_sibling() : _parent.last_child(); + return *this; +} + +PUGI__FN xml_node_iterator xml_node_iterator::operator--(int) { + xml_node_iterator temp = *this; + --*this; + return temp; +} + +PUGI__FN xml_attribute_iterator::xml_attribute_iterator() {} + +PUGI__FN +xml_attribute_iterator::xml_attribute_iterator(const xml_attribute &attr, + const xml_node &parent) + : _wrap(attr), _parent(parent) {} + +PUGI__FN +xml_attribute_iterator::xml_attribute_iterator(xml_attribute_struct *ref, + xml_node_struct *parent) + : _wrap(ref), _parent(parent) {} + +PUGI__FN bool +xml_attribute_iterator::operator==(const xml_attribute_iterator &rhs) const { + return _wrap._attr == rhs._wrap._attr && _parent._root == rhs._parent._root; +} + +PUGI__FN bool +xml_attribute_iterator::operator!=(const xml_attribute_iterator &rhs) const { + return _wrap._attr != rhs._wrap._attr || _parent._root != rhs._parent._root; +} + +PUGI__FN xml_attribute &xml_attribute_iterator::operator*() const { + assert(_wrap._attr); + return _wrap; +} + +PUGI__FN xml_attribute *xml_attribute_iterator::operator->() const { + assert(_wrap._attr); + return const_cast(&_wrap); // BCC32 workaround +} + +PUGI__FN const xml_attribute_iterator &xml_attribute_iterator::operator++() { + assert(_wrap._attr); + _wrap._attr = _wrap._attr->next_attribute; + return *this; +} + +PUGI__FN xml_attribute_iterator xml_attribute_iterator::operator++(int) { + xml_attribute_iterator temp = *this; + ++*this; + return temp; +} + +PUGI__FN const xml_attribute_iterator &xml_attribute_iterator::operator--() { + _wrap = _wrap._attr ? _wrap.previous_attribute() : _parent.last_attribute(); + return *this; +} + +PUGI__FN xml_attribute_iterator xml_attribute_iterator::operator--(int) { + xml_attribute_iterator temp = *this; + --*this; + return temp; +} + +PUGI__FN xml_named_node_iterator::xml_named_node_iterator() : _name(0) {} + +PUGI__FN xml_named_node_iterator::xml_named_node_iterator(const xml_node &node, + const char_t *name) + : _wrap(node), _parent(node.parent()), _name(name) {} + +PUGI__FN xml_named_node_iterator::xml_named_node_iterator( + xml_node_struct *ref, xml_node_struct *parent, const char_t *name) + : _wrap(ref), _parent(parent), _name(name) {} + +PUGI__FN bool +xml_named_node_iterator::operator==(const xml_named_node_iterator &rhs) const { + return _wrap._root == rhs._wrap._root && _parent._root == rhs._parent._root; +} + +PUGI__FN bool +xml_named_node_iterator::operator!=(const xml_named_node_iterator &rhs) const { + return _wrap._root != rhs._wrap._root || _parent._root != rhs._parent._root; +} + +PUGI__FN xml_node &xml_named_node_iterator::operator*() const { + assert(_wrap._root); + return _wrap; +} + +PUGI__FN xml_node *xml_named_node_iterator::operator->() const { + assert(_wrap._root); + return const_cast(&_wrap); // BCC32 workaround +} + +PUGI__FN const xml_named_node_iterator &xml_named_node_iterator::operator++() { + assert(_wrap._root); + _wrap = _wrap.next_sibling(_name); + return *this; +} + +PUGI__FN xml_named_node_iterator xml_named_node_iterator::operator++(int) { + xml_named_node_iterator temp = *this; + ++*this; + return temp; +} + +PUGI__FN const xml_named_node_iterator &xml_named_node_iterator::operator--() { + if (_wrap._root) + _wrap = _wrap.previous_sibling(_name); + else { + _wrap = _parent.last_child(); + + if (!impl::strequal(_wrap.name(), _name)) + _wrap = _wrap.previous_sibling(_name); + } + + return *this; +} + +PUGI__FN xml_named_node_iterator xml_named_node_iterator::operator--(int) { + xml_named_node_iterator temp = *this; + --*this; + return temp; +} + +PUGI__FN xml_parse_result::xml_parse_result() + : status(status_internal_error), offset(0), encoding(encoding_auto) {} + +PUGI__FN xml_parse_result::operator bool() const { return status == status_ok; } + +PUGI__FN const char *xml_parse_result::description() const { + switch (status) { + case status_ok: + return "No error"; + + case status_file_not_found: + return "File was not found"; + case status_io_error: + return "Error reading from file/stream"; + case status_out_of_memory: + return "Could not allocate memory"; + case status_internal_error: + return "Internal error occurred"; + + case status_unrecognized_tag: + return "Could not determine tag type"; + + case status_bad_pi: + return "Error parsing document declaration/processing instruction"; + case status_bad_comment: + return "Error parsing comment"; + case status_bad_cdata: + return "Error parsing CDATA section"; + case status_bad_doctype: + return "Error parsing document type declaration"; + case status_bad_pcdata: + return "Error parsing PCDATA section"; + case status_bad_start_element: + return "Error parsing start element tag"; + case status_bad_attribute: + return "Error parsing element attribute"; + case status_bad_end_element: + return "Error parsing end element tag"; + case status_end_element_mismatch: + return "Start-end tags mismatch"; + + case status_append_invalid_root: + return "Unable to append nodes: root is not an element or document"; + + case status_no_document_element: + return "No document element found"; + + default: + return "Unknown error"; + } +} + +PUGI__FN xml_document::xml_document() : _buffer(0) { create(); } + +PUGI__FN xml_document::~xml_document() { destroy(); } + +PUGI__FN void xml_document::reset() { + destroy(); + create(); +} + +PUGI__FN void xml_document::reset(const xml_document &proto) { + reset(); + + for (xml_node cur = proto.first_child(); cur; cur = cur.next_sibling()) + append_copy(cur); +} + +PUGI__FN void xml_document::create() { + assert(!_root); + +#ifdef PUGIXML_COMPACT + const size_t page_offset = sizeof(uint32_t); +#else + const size_t page_offset = 0; +#endif + + // initialize sentinel page + PUGI__STATIC_ASSERT( + sizeof(impl::xml_memory_page) + sizeof(impl::xml_document_struct) + + impl::xml_memory_page_alignment - sizeof(void *) + page_offset <= + sizeof(_memory)); + + // align upwards to page boundary + void *page_memory = + reinterpret_cast((reinterpret_cast(_memory) + + (impl::xml_memory_page_alignment - 1)) & + ~(impl::xml_memory_page_alignment - 1)); + + // prepare page structure + impl::xml_memory_page *page = impl::xml_memory_page::construct(page_memory); + assert(page); + + page->busy_size = impl::xml_memory_page_size; + + // setup first page marker +#ifdef PUGIXML_COMPACT + // round-trip through void* to avoid 'cast increases required alignment of + // target type' warning + page->compact_page_marker = reinterpret_cast(static_cast( + reinterpret_cast(page) + sizeof(impl::xml_memory_page))); + *page->compact_page_marker = sizeof(impl::xml_memory_page); +#endif + + // allocate new root + _root = new (reinterpret_cast(page) + sizeof(impl::xml_memory_page) + + page_offset) impl::xml_document_struct(page); + _root->prev_sibling_c = _root; + + // setup sentinel page + page->allocator = static_cast(_root); + + // verify the document allocation + assert(reinterpret_cast(_root) + sizeof(impl::xml_document_struct) <= + _memory + sizeof(_memory)); +} + +PUGI__FN void xml_document::destroy() { + assert(_root); + + // destroy static storage + if (_buffer) { + impl::xml_memory::deallocate(_buffer); + _buffer = 0; + } + + // destroy extra buffers (note: no need to destroy linked list nodes, they're + // allocated using document allocator) + for (impl::xml_extra_buffer *extra = + static_cast(_root)->extra_buffers; + extra; extra = extra->next) { + if (extra->buffer) + impl::xml_memory::deallocate(extra->buffer); + } + + // destroy dynamic storage, leave sentinel page (it's in static memory) + impl::xml_memory_page *root_page = PUGI__GETPAGE(_root); + assert(root_page && !root_page->prev); + assert(reinterpret_cast(root_page) >= _memory && + reinterpret_cast(root_page) < _memory + sizeof(_memory)); + + for (impl::xml_memory_page *page = root_page->next; page;) { + impl::xml_memory_page *next = page->next; + + impl::xml_allocator::deallocate_page(page); + + page = next; + } + +#ifdef PUGIXML_COMPACT + // destroy hash table + static_cast(_root)->hash.clear(); +#endif + + _root = 0; +} + +#ifndef PUGIXML_NO_STL +PUGI__FN xml_parse_result +xml_document::load(std::basic_istream> &stream, + unsigned int options, xml_encoding encoding) { + reset(); + + return impl::load_stream_impl(static_cast(_root), + stream, options, encoding, &_buffer); +} + +PUGI__FN xml_parse_result xml_document::load( + std::basic_istream> &stream, + unsigned int options) { + reset(); + + return impl::load_stream_impl(static_cast(_root), + stream, options, encoding_wchar, &_buffer); +} +#endif + +PUGI__FN xml_parse_result xml_document::load_string(const char_t *contents, + unsigned int options) { + // Force native encoding (skip autodetection) +#ifdef PUGIXML_WCHAR_MODE + xml_encoding encoding = encoding_wchar; +#else + xml_encoding encoding = encoding_utf8; +#endif + + return load_buffer(contents, impl::strlength(contents) * sizeof(char_t), + options, encoding); +} + +PUGI__FN xml_parse_result xml_document::load(const char_t *contents, + unsigned int options) { + return load_string(contents, options); +} + +PUGI__FN xml_parse_result xml_document::load_file(const char *path_, + unsigned int options, + xml_encoding encoding) { + reset(); + + using impl::auto_deleter; // MSVC7 workaround + auto_deleter file(fopen(path_, "rb"), fclose); + + return impl::load_file_impl(static_cast(_root), + file.data, options, encoding, &_buffer); +} + +PUGI__FN xml_parse_result xml_document::load_file(const wchar_t *path_, + unsigned int options, + xml_encoding encoding) { + reset(); + + using impl::auto_deleter; // MSVC7 workaround + auto_deleter file(impl::open_file_wide(path_, L"rb"), + fclose); + + return impl::load_file_impl(static_cast(_root), + file.data, options, encoding, &_buffer); +} + +PUGI__FN xml_parse_result xml_document::load_buffer(const void *contents, + size_t size, + unsigned int options, + xml_encoding encoding) { + reset(); + + return impl::load_buffer_impl(static_cast(_root), + _root, const_cast(contents), size, + options, encoding, false, false, &_buffer); +} + +PUGI__FN xml_parse_result xml_document::load_buffer_inplace( + void *contents, size_t size, unsigned int options, xml_encoding encoding) { + reset(); + + return impl::load_buffer_impl(static_cast(_root), + _root, contents, size, options, encoding, true, + false, &_buffer); +} + +PUGI__FN xml_parse_result xml_document::load_buffer_inplace_own( + void *contents, size_t size, unsigned int options, xml_encoding encoding) { + reset(); + + return impl::load_buffer_impl(static_cast(_root), + _root, contents, size, options, encoding, true, + true, &_buffer); +} + +PUGI__FN void xml_document::save(xml_writer &writer, const char_t *indent, + unsigned int flags, + xml_encoding encoding) const { + impl::xml_buffered_writer buffered_writer(writer, encoding); + + if ((flags & format_write_bom) && encoding != encoding_latin1) { + // BOM always represents the codepoint U+FEFF, so just write it in native + // encoding +#ifdef PUGIXML_WCHAR_MODE + unsigned int bom = 0xfeff; + buffered_writer.write(static_cast(bom)); +#else + buffered_writer.write('\xef', '\xbb', '\xbf'); +#endif + } + + if (!(flags & format_no_declaration) && !impl::has_declaration(_root)) { + buffered_writer.write_string(PUGIXML_TEXT("'); + if (!(flags & format_raw)) + buffered_writer.write('\n'); + } + + impl::node_output(buffered_writer, _root, indent, flags, 0); + + buffered_writer.flush(); +} + +#ifndef PUGIXML_NO_STL +PUGI__FN void +xml_document::save(std::basic_ostream> &stream, + const char_t *indent, unsigned int flags, + xml_encoding encoding) const { + xml_writer_stream writer(stream); + + save(writer, indent, flags, encoding); +} + +PUGI__FN void xml_document::save( + std::basic_ostream> &stream, + const char_t *indent, unsigned int flags) const { + xml_writer_stream writer(stream); + + save(writer, indent, flags, encoding_wchar); +} +#endif + +PUGI__FN bool xml_document::save_file(const char *path_, const char_t *indent, + unsigned int flags, + xml_encoding encoding) const { + using impl::auto_deleter; // MSVC7 workaround + auto_deleter file( + fopen(path_, (flags & format_save_file_text) ? "w" : "wb"), fclose); + + return impl::save_file_impl(*this, file.data, indent, flags, encoding); +} + +PUGI__FN bool xml_document::save_file(const wchar_t *path_, + const char_t *indent, unsigned int flags, + xml_encoding encoding) const { + using impl::auto_deleter; // MSVC7 workaround + auto_deleter file( + impl::open_file_wide(path_, + (flags & format_save_file_text) ? L"w" : L"wb"), + fclose); + + return impl::save_file_impl(*this, file.data, indent, flags, encoding); +} + +PUGI__FN xml_node xml_document::document_element() const { + assert(_root); + + for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) + if (PUGI__NODETYPE(i) == node_element) + return xml_node(i); + + return xml_node(); +} + +#ifndef PUGIXML_NO_STL +PUGI__FN std::string PUGIXML_FUNCTION as_utf8(const wchar_t *str) { + assert(str); + + return impl::as_utf8_impl(str, impl::strlength_wide(str)); +} + +PUGI__FN std::string PUGIXML_FUNCTION +as_utf8(const std::basic_string &str) { + return impl::as_utf8_impl(str.c_str(), str.size()); +} + +PUGI__FN std::basic_string PUGIXML_FUNCTION as_wide(const char *str) { + assert(str); + + return impl::as_wide_impl(str, strlen(str)); +} + +PUGI__FN std::basic_string + PUGIXML_FUNCTION as_wide(const std::string &str) { + return impl::as_wide_impl(str.c_str(), str.size()); +} +#endif + +PUGI__FN void PUGIXML_FUNCTION set_memory_management_functions( + allocation_function allocate, deallocation_function deallocate) { + impl::xml_memory::allocate = allocate; + impl::xml_memory::deallocate = deallocate; +} + +PUGI__FN allocation_function PUGIXML_FUNCTION get_memory_allocation_function() { + return impl::xml_memory::allocate; +} + +PUGI__FN deallocation_function PUGIXML_FUNCTION +get_memory_deallocation_function() { + return impl::xml_memory::deallocate; +} +} // namespace pugi + +#if !defined(PUGIXML_NO_STL) && (defined(_MSC_VER) || defined(__ICC)) +namespace std { +// Workarounds for (non-standard) iterator category detection for older versions +// (MSVC7/IC8 and earlier) +PUGI__FN std::bidirectional_iterator_tag +_Iter_cat(const pugi::xml_node_iterator &) { + return std::bidirectional_iterator_tag(); +} + +PUGI__FN std::bidirectional_iterator_tag +_Iter_cat(const pugi::xml_attribute_iterator &) { + return std::bidirectional_iterator_tag(); +} + +PUGI__FN std::bidirectional_iterator_tag +_Iter_cat(const pugi::xml_named_node_iterator &) { + return std::bidirectional_iterator_tag(); +} +} // namespace std +#endif + +#if !defined(PUGIXML_NO_STL) && defined(__SUNPRO_CC) +namespace std { +// Workarounds for (non-standard) iterator category detection +PUGI__FN std::bidirectional_iterator_tag +__iterator_category(const pugi::xml_node_iterator &) { + return std::bidirectional_iterator_tag(); +} + +PUGI__FN std::bidirectional_iterator_tag +__iterator_category(const pugi::xml_attribute_iterator &) { + return std::bidirectional_iterator_tag(); +} + +PUGI__FN std::bidirectional_iterator_tag +__iterator_category(const pugi::xml_named_node_iterator &) { + return std::bidirectional_iterator_tag(); +} +} // namespace std +#endif + +#ifndef PUGIXML_NO_XPATH +// STL replacements +PUGI__NS_BEGIN +struct equal_to { + template bool operator()(const T &lhs, const T &rhs) const { + return lhs == rhs; + } +}; + +struct not_equal_to { + template bool operator()(const T &lhs, const T &rhs) const { + return lhs != rhs; + } +}; + +struct less { + template bool operator()(const T &lhs, const T &rhs) const { + return lhs < rhs; + } +}; + +struct less_equal { + template bool operator()(const T &lhs, const T &rhs) const { + return lhs <= rhs; + } +}; + +template void swap(T &lhs, T &rhs) { + T temp = lhs; + lhs = rhs; + rhs = temp; +} + +template +I min_element(I begin, I end, const Pred &pred) { + I result = begin; + + for (I it = begin + 1; it != end; ++it) + if (pred(*it, *result)) + result = it; + + return result; +} + +template void reverse(I begin, I end) { + while (end - begin > 1) + swap(*begin++, *--end); +} + +template I unique(I begin, I end) { + // fast skip head + while (end - begin > 1 && *begin != *(begin + 1)) + begin++; + + if (begin == end) + return begin; + + // last written element + I write = begin++; + + // merge unique elements + while (begin != end) { + if (*begin != *write) + *++write = *begin++; + else + begin++; + } + + // past-the-end (write points to live element) + return write + 1; +} + +template void copy_backwards(I begin, I end, I target) { + while (begin != end) + *--target = *--end; +} + +template +void insertion_sort(I begin, I end, const Pred &pred, T *) { + assert(begin != end); + + for (I it = begin + 1; it != end; ++it) { + T val = *it; + + if (pred(val, *begin)) { + // move to front + copy_backwards(begin, it, it + 1); + *begin = val; + } else { + I hole = it; + + // move hole backwards + while (pred(val, *(hole - 1))) { + *hole = *(hole - 1); + hole--; + } + + // fill hole with element + *hole = val; + } + } +} + +// std variant for elements with == +template +void partition(I begin, I middle, I end, const Pred &pred, I *out_eqbeg, + I *out_eqend) { + I eqbeg = middle, eqend = middle + 1; + + // expand equal range + while (eqbeg != begin && *(eqbeg - 1) == *eqbeg) + --eqbeg; + while (eqend != end && *eqend == *eqbeg) + ++eqend; + + // process outer elements + I ltend = eqbeg, gtbeg = eqend; + + for (;;) { + // find the element from the right side that belongs to the left one + for (; gtbeg != end; ++gtbeg) + if (!pred(*eqbeg, *gtbeg)) { + if (*gtbeg == *eqbeg) + swap(*gtbeg, *eqend++); + else + break; + } + + // find the element from the left side that belongs to the right one + for (; ltend != begin; --ltend) + if (!pred(*(ltend - 1), *eqbeg)) { + if (*eqbeg == *(ltend - 1)) + swap(*(ltend - 1), *--eqbeg); + else + break; + } + + // scanned all elements + if (gtbeg == end && ltend == begin) { + *out_eqbeg = eqbeg; + *out_eqend = eqend; + return; + } + + // make room for elements by moving equal area + if (gtbeg == end) { + if (--ltend != --eqbeg) + swap(*ltend, *eqbeg); + swap(*eqbeg, *--eqend); + } else if (ltend == begin) { + if (eqend != gtbeg) + swap(*eqbeg, *eqend); + ++eqend; + swap(*gtbeg++, *eqbeg++); + } else + swap(*gtbeg++, *--ltend); + } +} + +template +void median3(I first, I middle, I last, const Pred &pred) { + if (pred(*middle, *first)) + swap(*middle, *first); + if (pred(*last, *middle)) + swap(*last, *middle); + if (pred(*middle, *first)) + swap(*middle, *first); +} + +template +void median(I first, I middle, I last, const Pred &pred) { + if (last - first <= 40) { + // median of three for small chunks + median3(first, middle, last, pred); + } else { + // median of nine + size_t step = (last - first + 1) / 8; + + median3(first, first + step, first + 2 * step, pred); + median3(middle - step, middle, middle + step, pred); + median3(last - 2 * step, last - step, last, pred); + median3(first + step, middle, last - step, pred); + } +} + +template +void sort(I begin, I end, const Pred &pred) { + // sort large chunks + while (end - begin > 32) { + // find median element + I middle = begin + (end - begin) / 2; + median(begin, middle, end - 1, pred); + + // partition in three chunks (< = >) + I eqbeg, eqend; + partition(begin, middle, end, pred, &eqbeg, &eqend); + + // loop on larger half + if (eqbeg - begin > end - eqend) { + sort(eqend, end, pred); + end = eqbeg; + } else { + sort(begin, eqbeg, pred); + begin = eqend; + } + } + + // insertion sort small chunk + if (begin != end) + insertion_sort(begin, end, pred, &*begin); +} +PUGI__NS_END + +// Allocator used for AST and evaluation stacks +PUGI__NS_BEGIN +static const size_t xpath_memory_page_size = +#ifdef PUGIXML_MEMORY_XPATH_PAGE_SIZE + PUGIXML_MEMORY_XPATH_PAGE_SIZE +#else + 4096 +#endif + ; + +static const uintptr_t xpath_memory_block_alignment = sizeof(double) > + sizeof(void *) + ? sizeof(double) + : sizeof(void *); + +struct xpath_memory_block { + xpath_memory_block *next; + size_t capacity; + + union { + char data[xpath_memory_page_size]; + double alignment; + }; +}; + +class xpath_allocator { + xpath_memory_block *_root; + size_t _root_size; + +public: +#ifdef PUGIXML_NO_EXCEPTIONS + jmp_buf *error_handler; +#endif + + xpath_allocator(xpath_memory_block *root, size_t root_size = 0) + : _root(root), _root_size(root_size) { +#ifdef PUGIXML_NO_EXCEPTIONS + error_handler = 0; +#endif + } + + void *allocate_nothrow(size_t size) { + // round size up to block alignment boundary + size = (size + xpath_memory_block_alignment - 1) & + ~(xpath_memory_block_alignment - 1); + + if (_root_size + size <= _root->capacity) { + void *buf = &_root->data[0] + _root_size; + _root_size += size; + return buf; + } else { + // make sure we have at least 1/4th of the page free after allocation to + // satisfy subsequent allocation requests + size_t block_capacity_base = sizeof(_root->data); + size_t block_capacity_req = size + block_capacity_base / 4; + size_t block_capacity = (block_capacity_base > block_capacity_req) + ? block_capacity_base + : block_capacity_req; + + size_t block_size = block_capacity + offsetof(xpath_memory_block, data); + + xpath_memory_block *block = + static_cast(xml_memory::allocate(block_size)); + if (!block) + return 0; + + block->next = _root; + block->capacity = block_capacity; + + _root = block; + _root_size = size; + + return block->data; + } + } + + void *allocate(size_t size) { + void *result = allocate_nothrow(size); + + if (!result) { +#ifdef PUGIXML_NO_EXCEPTIONS + assert(error_handler); + longjmp(*error_handler, 1); +#else + throw std::bad_alloc(); +#endif + } + + return result; + } + + void *reallocate(void *ptr, size_t old_size, size_t new_size) { + // round size up to block alignment boundary + old_size = (old_size + xpath_memory_block_alignment - 1) & + ~(xpath_memory_block_alignment - 1); + new_size = (new_size + xpath_memory_block_alignment - 1) & + ~(xpath_memory_block_alignment - 1); + + // we can only reallocate the last object + assert(ptr == 0 || + static_cast(ptr) + old_size == &_root->data[0] + _root_size); + + // adjust root size so that we have not allocated the object at all + bool only_object = (_root_size == old_size); + + if (ptr) + _root_size -= old_size; + + // allocate a new version (this will obviously reuse the memory if possible) + void *result = allocate(new_size); + assert(result); + + // we have a new block + if (result != ptr && ptr) { + // copy old data + assert(new_size >= old_size); + memcpy(result, ptr, old_size); + + // free the previous page if it had no other objects + if (only_object) { + assert(_root->data == result); + assert(_root->next); + + xpath_memory_block *next = _root->next->next; + + if (next) { + // deallocate the whole page, unless it was the first one + xml_memory::deallocate(_root->next); + _root->next = next; + } + } + } + + return result; + } + + void revert(const xpath_allocator &state) { + // free all new pages + xpath_memory_block *cur = _root; + + while (cur != state._root) { + xpath_memory_block *next = cur->next; + + xml_memory::deallocate(cur); + + cur = next; + } + + // restore state + _root = state._root; + _root_size = state._root_size; + } + + void release() { + xpath_memory_block *cur = _root; + assert(cur); + + while (cur->next) { + xpath_memory_block *next = cur->next; + + xml_memory::deallocate(cur); + + cur = next; + } + } +}; + +struct xpath_allocator_capture { + xpath_allocator_capture(xpath_allocator *alloc) + : _target(alloc), _state(*alloc) {} + + ~xpath_allocator_capture() { _target->revert(_state); } + + xpath_allocator *_target; + xpath_allocator _state; +}; + +struct xpath_stack { + xpath_allocator *result; + xpath_allocator *temp; +}; + +struct xpath_stack_data { + xpath_memory_block blocks[2]; + xpath_allocator result; + xpath_allocator temp; + xpath_stack stack; + +#ifdef PUGIXML_NO_EXCEPTIONS + jmp_buf error_handler; +#endif + + xpath_stack_data() : result(blocks + 0), temp(blocks + 1) { + blocks[0].next = blocks[1].next = 0; + blocks[0].capacity = blocks[1].capacity = sizeof(blocks[0].data); + + stack.result = &result; + stack.temp = &temp; + +#ifdef PUGIXML_NO_EXCEPTIONS + result.error_handler = temp.error_handler = &error_handler; +#endif + } + + ~xpath_stack_data() { + result.release(); + temp.release(); + } +}; +PUGI__NS_END + +// String class +PUGI__NS_BEGIN +class xpath_string { + const char_t *_buffer; + bool _uses_heap; + size_t _length_heap; + + static char_t *duplicate_string(const char_t *string, size_t length, + xpath_allocator *alloc) { + char_t *result = + static_cast(alloc->allocate((length + 1) * sizeof(char_t))); + assert(result); + + memcpy(result, string, length * sizeof(char_t)); + result[length] = 0; + + return result; + } + + xpath_string(const char_t *buffer, bool uses_heap_, size_t length_heap) + : _buffer(buffer), _uses_heap(uses_heap_), _length_heap(length_heap) {} + +public: + static xpath_string from_const(const char_t *str) { + return xpath_string(str, false, 0); + } + + static xpath_string from_heap_preallocated(const char_t *begin, + const char_t *end) { + assert(begin <= end && *end == 0); + + return xpath_string(begin, true, static_cast(end - begin)); + } + + static xpath_string from_heap(const char_t *begin, const char_t *end, + xpath_allocator *alloc) { + assert(begin <= end); + + size_t length = static_cast(end - begin); + + return length == 0 ? xpath_string() + : xpath_string(duplicate_string(begin, length, alloc), + true, length); + } + + xpath_string() + : _buffer(PUGIXML_TEXT("")), _uses_heap(false), _length_heap(0) {} + + void append(const xpath_string &o, xpath_allocator *alloc) { + // skip empty sources + if (!*o._buffer) + return; + + // fast append for constant empty target and constant source + if (!*_buffer && !_uses_heap && !o._uses_heap) { + _buffer = o._buffer; + } else { + // need to make heap copy + size_t target_length = length(); + size_t source_length = o.length(); + size_t result_length = target_length + source_length; + + // allocate new buffer + char_t *result = static_cast( + alloc->reallocate(_uses_heap ? const_cast(_buffer) : 0, + (target_length + 1) * sizeof(char_t), + (result_length + 1) * sizeof(char_t))); + assert(result); + + // append first string to the new buffer in case there was no reallocation + if (!_uses_heap) + memcpy(result, _buffer, target_length * sizeof(char_t)); + + // append second string to the new buffer + memcpy(result + target_length, o._buffer, source_length * sizeof(char_t)); + result[result_length] = 0; + + // finalize + _buffer = result; + _uses_heap = true; + _length_heap = result_length; + } + } + + const char_t *c_str() const { return _buffer; } + + size_t length() const { + return _uses_heap ? _length_heap : strlength(_buffer); + } + + char_t *data(xpath_allocator *alloc) { + // make private heap copy + if (!_uses_heap) { + size_t length_ = strlength(_buffer); + + _buffer = duplicate_string(_buffer, length_, alloc); + _uses_heap = true; + _length_heap = length_; + } + + return const_cast(_buffer); + } + + bool empty() const { return *_buffer == 0; } + + bool operator==(const xpath_string &o) const { + return strequal(_buffer, o._buffer); + } + + bool operator!=(const xpath_string &o) const { + return !strequal(_buffer, o._buffer); + } + + bool uses_heap() const { return _uses_heap; } +}; +PUGI__NS_END + +PUGI__NS_BEGIN +PUGI__FN bool starts_with(const char_t *string, const char_t *pattern) { + while (*pattern && *string == *pattern) { + string++; + pattern++; + } + + return *pattern == 0; +} + +PUGI__FN const char_t *find_char(const char_t *s, char_t c) { +#ifdef PUGIXML_WCHAR_MODE + return wcschr(s, c); +#else + return strchr(s, c); +#endif +} + +PUGI__FN const char_t *find_substring(const char_t *s, const char_t *p) { +#ifdef PUGIXML_WCHAR_MODE + // MSVC6 wcsstr bug workaround (if s is empty it always returns 0) + return (*p == 0) ? s : wcsstr(s, p); +#else + return strstr(s, p); +#endif +} + +// Converts symbol to lower case, if it is an ASCII one +PUGI__FN char_t tolower_ascii(char_t ch) { + return static_cast(ch - 'A') < 26 + ? static_cast(ch | ' ') + : ch; +} + +PUGI__FN xpath_string string_value(const xpath_node &na, + xpath_allocator *alloc) { + if (na.attribute()) + return xpath_string::from_const(na.attribute().value()); + else { + xml_node n = na.node(); + + switch (n.type()) { + case node_pcdata: + case node_cdata: + case node_comment: + case node_pi: + return xpath_string::from_const(n.value()); + + case node_document: + case node_element: { + xpath_string result; + + xml_node cur = n.first_child(); + + while (cur && cur != n) { + if (cur.type() == node_pcdata || cur.type() == node_cdata) + result.append(xpath_string::from_const(cur.value()), alloc); + + if (cur.first_child()) + cur = cur.first_child(); + else if (cur.next_sibling()) + cur = cur.next_sibling(); + else { + while (!cur.next_sibling() && cur != n) + cur = cur.parent(); + + if (cur != n) + cur = cur.next_sibling(); + } + } + + return result; + } + + default: + return xpath_string(); + } + } +} + +PUGI__FN bool node_is_before_sibling(xml_node_struct *ln, xml_node_struct *rn) { + assert(ln->parent == rn->parent); + + // there is no common ancestor (the shared parent is null), nodes are from + // different documents + if (!ln->parent) + return ln < rn; + + // determine sibling order + xml_node_struct *ls = ln; + xml_node_struct *rs = rn; + + while (ls && rs) { + if (ls == rn) + return true; + if (rs == ln) + return false; + + ls = ls->next_sibling; + rs = rs->next_sibling; + } + + // if rn sibling chain ended ln must be before rn + return !rs; +} + +PUGI__FN bool node_is_before(xml_node_struct *ln, xml_node_struct *rn) { + // find common ancestor at the same depth, if any + xml_node_struct *lp = ln; + xml_node_struct *rp = rn; + + while (lp && rp && lp->parent != rp->parent) { + lp = lp->parent; + rp = rp->parent; + } + + // parents are the same! + if (lp && rp) + return node_is_before_sibling(lp, rp); + + // nodes are at different depths, need to normalize heights + bool left_higher = !lp; + + while (lp) { + lp = lp->parent; + ln = ln->parent; + } + + while (rp) { + rp = rp->parent; + rn = rn->parent; + } + + // one node is the ancestor of the other + if (ln == rn) + return left_higher; + + // find common ancestor... again + while (ln->parent != rn->parent) { + ln = ln->parent; + rn = rn->parent; + } + + return node_is_before_sibling(ln, rn); +} + +PUGI__FN bool node_is_ancestor(xml_node_struct *parent, xml_node_struct *node) { + while (node && node != parent) + node = node->parent; + + return parent && node == parent; +} + +PUGI__FN const void *document_buffer_order(const xpath_node &xnode) { + xml_node_struct *node = xnode.node().internal_object(); + + if (node) { + if ((get_document(node).header & xml_memory_page_contents_shared_mask) == + 0) { + if (node->name && + (node->header & + impl::xml_memory_page_name_allocated_or_shared_mask) == 0) + return node->name; + if (node->value && + (node->header & + impl::xml_memory_page_value_allocated_or_shared_mask) == 0) + return node->value; + } + + return 0; + } + + xml_attribute_struct *attr = xnode.attribute().internal_object(); + + if (attr) { + if ((get_document(attr).header & xml_memory_page_contents_shared_mask) == + 0) { + if ((attr->header & + impl::xml_memory_page_name_allocated_or_shared_mask) == 0) + return attr->name; + if ((attr->header & + impl::xml_memory_page_value_allocated_or_shared_mask) == 0) + return attr->value; + } + + return 0; + } + + return 0; +} + +struct document_order_comparator { + bool operator()(const xpath_node &lhs, const xpath_node &rhs) const { + // optimized document order based check + const void *lo = document_buffer_order(lhs); + const void *ro = document_buffer_order(rhs); + + if (lo && ro) + return lo < ro; + + // slow comparison + xml_node ln = lhs.node(), rn = rhs.node(); + + // compare attributes + if (lhs.attribute() && rhs.attribute()) { + // shared parent + if (lhs.parent() == rhs.parent()) { + // determine sibling order + for (xml_attribute a = lhs.attribute(); a; a = a.next_attribute()) + if (a == rhs.attribute()) + return true; + + return false; + } + + // compare attribute parents + ln = lhs.parent(); + rn = rhs.parent(); + } else if (lhs.attribute()) { + // attributes go after the parent element + if (lhs.parent() == rhs.node()) + return false; + + ln = lhs.parent(); + } else if (rhs.attribute()) { + // attributes go after the parent element + if (rhs.parent() == lhs.node()) + return true; + + rn = rhs.parent(); + } + + if (ln == rn) + return false; + + if (!ln || !rn) + return ln < rn; + + return node_is_before(ln.internal_object(), rn.internal_object()); + } +}; + +struct duplicate_comparator { + bool operator()(const xpath_node &lhs, const xpath_node &rhs) const { + if (lhs.attribute()) + return rhs.attribute() ? lhs.attribute() < rhs.attribute() : true; + else + return rhs.attribute() ? false : lhs.node() < rhs.node(); + } +}; + +PUGI__FN double gen_nan() { +#if defined(__STDC_IEC_559__) || \ + ((FLT_RADIX - 0 == 2) && (FLT_MAX_EXP - 0 == 128) && \ + (FLT_MANT_DIG - 0 == 24)) + union { + float f; + uint32_t i; + } u[sizeof(float) == sizeof(uint32_t) ? 1 : -1]; + u[0].i = 0x7fc00000; + return u[0].f; +#else + // fallback + const volatile double zero = 0.0; + return zero / zero; +#endif +} + +PUGI__FN bool is_nan(double value) { +#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) + return !!_isnan(value); +#elif defined(fpclassify) && defined(FP_NAN) + return fpclassify(value) == FP_NAN; +#else + // fallback + const volatile double v = value; + return v != v; +#endif +} + +PUGI__FN const char_t *convert_number_to_string_special(double value) { +#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) + if (_finite(value)) + return (value == 0) ? PUGIXML_TEXT("0") : 0; + if (_isnan(value)) + return PUGIXML_TEXT("NaN"); + return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity"); +#elif defined(fpclassify) && defined(FP_NAN) && defined(FP_INFINITE) && \ + defined(FP_ZERO) + switch (fpclassify(value)) { + case FP_NAN: + return PUGIXML_TEXT("NaN"); + + case FP_INFINITE: + return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity"); + + case FP_ZERO: + return PUGIXML_TEXT("0"); + + default: + return 0; + } +#else + // fallback + const volatile double v = value; + + if (v == 0) + return PUGIXML_TEXT("0"); + if (v != v) + return PUGIXML_TEXT("NaN"); + if (v * 2 == v) + return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity"); + return 0; +#endif +} + +PUGI__FN bool convert_number_to_boolean(double value) { + return (value != 0 && !is_nan(value)); +} + +PUGI__FN void truncate_zeros(char *begin, char *end) { + while (begin != end && end[-1] == '0') + end--; + + *end = 0; +} + +// gets mantissa digits in the form of 0.xxxxx with 0. implied and the exponent +#if defined(PUGI__MSVC_CRT_VERSION) && PUGI__MSVC_CRT_VERSION >= 1400 && \ + !defined(_WIN32_WCE) +PUGI__FN void convert_number_to_mantissa_exponent(double value, char *buffer, + size_t buffer_size, + char **out_mantissa, + int *out_exponent) { + // get base values + int sign, exponent; + _ecvt_s(buffer, buffer_size, value, DBL_DIG + 1, &exponent, &sign); + + // truncate redundant zeros + truncate_zeros(buffer, buffer + strlen(buffer)); + + // fill results + *out_mantissa = buffer; + *out_exponent = exponent; +} +#else +PUGI__FN void convert_number_to_mantissa_exponent(double value, char *buffer, + size_t buffer_size, + char **out_mantissa, + int *out_exponent) { + // get a scientific notation value with IEEE DBL_DIG decimals + sprintf(buffer, "%.*e", DBL_DIG, value); + assert(strlen(buffer) < buffer_size); + (void)!buffer_size; + + // get the exponent (possibly negative) + char *exponent_string = strchr(buffer, 'e'); + assert(exponent_string); + + int exponent = atoi(exponent_string + 1); + + // extract mantissa string: skip sign + char *mantissa = buffer[0] == '-' ? buffer + 1 : buffer; + assert(mantissa[0] != '0' && mantissa[1] == '.'); + + // divide mantissa by 10 to eliminate integer part + mantissa[1] = mantissa[0]; + mantissa++; + exponent++; + + // remove extra mantissa digits and zero-terminate mantissa + truncate_zeros(mantissa, exponent_string); + + // fill results + *out_mantissa = mantissa; + *out_exponent = exponent; +} +#endif + +PUGI__FN xpath_string convert_number_to_string(double value, + xpath_allocator *alloc) { + // try special number conversion + const char_t *special = convert_number_to_string_special(value); + if (special) + return xpath_string::from_const(special); + + // get mantissa + exponent form + char mantissa_buffer[32]; + + char *mantissa; + int exponent; + convert_number_to_mantissa_exponent( + value, mantissa_buffer, sizeof(mantissa_buffer), &mantissa, &exponent); + + // allocate a buffer of suitable length for the number + size_t result_size = + strlen(mantissa_buffer) + (exponent > 0 ? exponent : -exponent) + 4; + char_t *result = + static_cast(alloc->allocate(sizeof(char_t) * result_size)); + assert(result); + + // make the number! + char_t *s = result; + + // sign + if (value < 0) + *s++ = '-'; + + // integer part + if (exponent <= 0) { + *s++ = '0'; + } else { + while (exponent > 0) { + assert(*mantissa == 0 || + static_cast(static_cast(*mantissa) - + '0') <= 9); + *s++ = *mantissa ? *mantissa++ : '0'; + exponent--; + } + } + + // fractional part + if (*mantissa) { + // decimal point + *s++ = '.'; + + // extra zeroes from negative exponent + while (exponent < 0) { + *s++ = '0'; + exponent++; + } + + // extra mantissa digits + while (*mantissa) { + assert(static_cast(*mantissa - '0') <= 9); + *s++ = *mantissa++; + } + } + + // zero-terminate + assert(s < result + result_size); + *s = 0; + + return xpath_string::from_heap_preallocated(result, s); +} + +PUGI__FN bool check_string_to_number_format(const char_t *string) { + // parse leading whitespace + while (PUGI__IS_CHARTYPE(*string, ct_space)) + ++string; + + // parse sign + if (*string == '-') + ++string; + + if (!*string) + return false; + + // if there is no integer part, there should be a decimal part with at least + // one digit + if (!PUGI__IS_CHARTYPEX(string[0], ctx_digit) && + (string[0] != '.' || !PUGI__IS_CHARTYPEX(string[1], ctx_digit))) + return false; + + // parse integer part + while (PUGI__IS_CHARTYPEX(*string, ctx_digit)) + ++string; + + // parse decimal part + if (*string == '.') { + ++string; + + while (PUGI__IS_CHARTYPEX(*string, ctx_digit)) + ++string; + } + + // parse trailing whitespace + while (PUGI__IS_CHARTYPE(*string, ct_space)) + ++string; + + return *string == 0; +} + +PUGI__FN double convert_string_to_number(const char_t *string) { + // check string format + if (!check_string_to_number_format(string)) + return gen_nan(); + + // parse string +#ifdef PUGIXML_WCHAR_MODE + return wcstod(string, 0); +#else + return strtod(string, 0); +#endif +} + +PUGI__FN bool convert_string_to_number_scratch(char_t (&buffer)[32], + const char_t *begin, + const char_t *end, + double *out_result) { + size_t length = static_cast(end - begin); + char_t *scratch = buffer; + + if (length >= sizeof(buffer) / sizeof(buffer[0])) { + // need to make dummy on-heap copy + scratch = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!scratch) + return false; + } + + // copy string to zero-terminated buffer and perform conversion + memcpy(scratch, begin, length * sizeof(char_t)); + scratch[length] = 0; + + *out_result = convert_string_to_number(scratch); + + // free dummy buffer + if (scratch != buffer) + xml_memory::deallocate(scratch); + + return true; +} + +PUGI__FN double round_nearest(double value) { return floor(value + 0.5); } + +PUGI__FN double round_nearest_nzero(double value) { + // same as round_nearest, but returns -0 for [-0.5, -0] + // ceil is used to differentiate between +0 and -0 (we return -0 for [-0.5, + // -0] and +0 for +0) + return (value >= -0.5 && value <= 0) ? ceil(value) : floor(value + 0.5); +} + +PUGI__FN const char_t *qualified_name(const xpath_node &node) { + return node.attribute() ? node.attribute().name() : node.node().name(); +} + +PUGI__FN const char_t *local_name(const xpath_node &node) { + const char_t *name = qualified_name(node); + const char_t *p = find_char(name, ':'); + + return p ? p + 1 : name; +} + +struct namespace_uri_predicate { + const char_t *prefix; + size_t prefix_length; + + namespace_uri_predicate(const char_t *name) { + const char_t *pos = find_char(name, ':'); + + prefix = pos ? name : 0; + prefix_length = pos ? static_cast(pos - name) : 0; + } + + bool operator()(xml_attribute a) const { + const char_t *name = a.name(); + + if (!starts_with(name, PUGIXML_TEXT("xmlns"))) + return false; + + return prefix ? name[5] == ':' && + strequalrange(name + 6, prefix, prefix_length) + : name[5] == 0; + } +}; + +PUGI__FN const char_t *namespace_uri(xml_node node) { + namespace_uri_predicate pred = node.name(); + + xml_node p = node; + + while (p) { + xml_attribute a = p.find_attribute(pred); + + if (a) + return a.value(); + + p = p.parent(); + } + + return PUGIXML_TEXT(""); +} + +PUGI__FN const char_t *namespace_uri(xml_attribute attr, xml_node parent) { + namespace_uri_predicate pred = attr.name(); + + // Default namespace does not apply to attributes + if (!pred.prefix) + return PUGIXML_TEXT(""); + + xml_node p = parent; + + while (p) { + xml_attribute a = p.find_attribute(pred); + + if (a) + return a.value(); + + p = p.parent(); + } + + return PUGIXML_TEXT(""); +} + +PUGI__FN const char_t *namespace_uri(const xpath_node &node) { + return node.attribute() ? namespace_uri(node.attribute(), node.parent()) + : namespace_uri(node.node()); +} + +PUGI__FN char_t *normalize_space(char_t *buffer) { + char_t *write = buffer; + + for (char_t *it = buffer; *it;) { + char_t ch = *it++; + + if (PUGI__IS_CHARTYPE(ch, ct_space)) { + // replace whitespace sequence with single space + while (PUGI__IS_CHARTYPE(*it, ct_space)) + it++; + + // avoid leading spaces + if (write != buffer) + *write++ = ' '; + } else + *write++ = ch; + } + + // remove trailing space + if (write != buffer && PUGI__IS_CHARTYPE(write[-1], ct_space)) + write--; + + // zero-terminate + *write = 0; + + return write; +} + +PUGI__FN char_t *translate(char_t *buffer, const char_t *from, const char_t *to, + size_t to_length) { + char_t *write = buffer; + + while (*buffer) { + PUGI__DMC_VOLATILE char_t ch = *buffer++; + + const char_t *pos = find_char(from, ch); + + if (!pos) + *write++ = ch; // do not process + else if (static_cast(pos - from) < to_length) + *write++ = to[pos - from]; // replace + } + + // zero-terminate + *write = 0; + + return write; +} + +PUGI__FN unsigned char *translate_table_generate(xpath_allocator *alloc, + const char_t *from, + const char_t *to) { + unsigned char table[128] = {0}; + + while (*from) { + unsigned int fc = static_cast(*from); + unsigned int tc = static_cast(*to); + + if (fc >= 128 || tc >= 128) + return 0; + + // code=128 means "skip character" + if (!table[fc]) + table[fc] = static_cast(tc ? tc : 128); + + from++; + if (tc) + to++; + } + + for (int i = 0; i < 128; ++i) + if (!table[i]) + table[i] = static_cast(i); + + void *result = alloc->allocate_nothrow(sizeof(table)); + + if (result) { + memcpy(result, table, sizeof(table)); + } + + return static_cast(result); +} + +PUGI__FN char_t *translate_table(char_t *buffer, const unsigned char *table) { + char_t *write = buffer; + + while (*buffer) { + char_t ch = *buffer++; + unsigned int index = static_cast(ch); + + if (index < 128) { + unsigned char code = table[index]; + + // code=128 means "skip character" (table size is 128 so 128 can be a + // special value) this code skips these characters without extra branches + *write = static_cast(code); + write += 1 - (code >> 7); + } else { + *write++ = ch; + } + } + + // zero-terminate + *write = 0; + + return write; +} + +inline bool is_xpath_attribute(const char_t *name) { + return !(starts_with(name, PUGIXML_TEXT("xmlns")) && + (name[5] == 0 || name[5] == ':')); +} + +struct xpath_variable_boolean : xpath_variable { + xpath_variable_boolean() : xpath_variable(xpath_type_boolean), value(false) {} + + bool value; + char_t name[1]; +}; + +struct xpath_variable_number : xpath_variable { + xpath_variable_number() : xpath_variable(xpath_type_number), value(0) {} + + double value; + char_t name[1]; +}; + +struct xpath_variable_string : xpath_variable { + xpath_variable_string() : xpath_variable(xpath_type_string), value(0) {} + + ~xpath_variable_string() { + if (value) + xml_memory::deallocate(value); + } + + char_t *value; + char_t name[1]; +}; + +struct xpath_variable_node_set : xpath_variable { + xpath_variable_node_set() : xpath_variable(xpath_type_node_set) {} + + xpath_node_set value; + char_t name[1]; +}; + +static const xpath_node_set dummy_node_set; + +PUGI__FN unsigned int hash_string(const char_t *str) { + // Jenkins one-at-a-time hash + // (http://en.wikipedia.org/wiki/Jenkins_hash_function#one-at-a-time) + unsigned int result = 0; + + while (*str) { + result += static_cast(*str++); + result += result << 10; + result ^= result >> 6; + } + + result += result << 3; + result ^= result >> 11; + result += result << 15; + + return result; +} + +template PUGI__FN T *new_xpath_variable(const char_t *name) { + size_t length = strlength(name); + if (length == 0) + return 0; // empty variable names are invalid + + // $$ we can't use offsetof(T, name) because T is non-POD, so we just allocate + // additional length characters + void *memory = xml_memory::allocate(sizeof(T) + length * sizeof(char_t)); + if (!memory) + return 0; + + T *result = new (memory) T(); + + memcpy(result->name, name, (length + 1) * sizeof(char_t)); + + return result; +} + +PUGI__FN xpath_variable *new_xpath_variable(xpath_value_type type, + const char_t *name) { + switch (type) { + case xpath_type_node_set: + return new_xpath_variable(name); + + case xpath_type_number: + return new_xpath_variable(name); + + case xpath_type_string: + return new_xpath_variable(name); + + case xpath_type_boolean: + return new_xpath_variable(name); + + default: + return 0; + } +} + +template PUGI__FN void delete_xpath_variable(T *var) { + var->~T(); + xml_memory::deallocate(var); +} + +PUGI__FN void delete_xpath_variable(xpath_value_type type, + xpath_variable *var) { + switch (type) { + case xpath_type_node_set: + delete_xpath_variable(static_cast(var)); + break; + + case xpath_type_number: + delete_xpath_variable(static_cast(var)); + break; + + case xpath_type_string: + delete_xpath_variable(static_cast(var)); + break; + + case xpath_type_boolean: + delete_xpath_variable(static_cast(var)); + break; + + default: + assert(!"Invalid variable type"); + } +} + +PUGI__FN bool copy_xpath_variable(xpath_variable *lhs, + const xpath_variable *rhs) { + switch (rhs->type()) { + case xpath_type_node_set: + return lhs->set(static_cast(rhs)->value); + + case xpath_type_number: + return lhs->set(static_cast(rhs)->value); + + case xpath_type_string: + return lhs->set(static_cast(rhs)->value); + + case xpath_type_boolean: + return lhs->set(static_cast(rhs)->value); + + default: + assert(!"Invalid variable type"); + return false; + } +} + +PUGI__FN bool get_variable_scratch(char_t (&buffer)[32], + xpath_variable_set *set, const char_t *begin, + const char_t *end, + xpath_variable **out_result) { + size_t length = static_cast(end - begin); + char_t *scratch = buffer; + + if (length >= sizeof(buffer) / sizeof(buffer[0])) { + // need to make dummy on-heap copy + scratch = static_cast( + xml_memory::allocate((length + 1) * sizeof(char_t))); + if (!scratch) + return false; + } + + // copy string to zero-terminated buffer and perform lookup + memcpy(scratch, begin, length * sizeof(char_t)); + scratch[length] = 0; + + *out_result = set->get(scratch); + + // free dummy buffer + if (scratch != buffer) + xml_memory::deallocate(scratch); + + return true; +} +PUGI__NS_END + +// Internal node set class +PUGI__NS_BEGIN +PUGI__FN xpath_node_set::type_t xpath_get_order(const xpath_node *begin, + const xpath_node *end) { + if (end - begin < 2) + return xpath_node_set::type_sorted; + + document_order_comparator cmp; + + bool first = cmp(begin[0], begin[1]); + + for (const xpath_node *it = begin + 1; it + 1 < end; ++it) + if (cmp(it[0], it[1]) != first) + return xpath_node_set::type_unsorted; + + return first ? xpath_node_set::type_sorted + : xpath_node_set::type_sorted_reverse; +} + +PUGI__FN xpath_node_set::type_t xpath_sort(xpath_node *begin, xpath_node *end, + xpath_node_set::type_t type, + bool rev) { + xpath_node_set::type_t order = + rev ? xpath_node_set::type_sorted_reverse : xpath_node_set::type_sorted; + + if (type == xpath_node_set::type_unsorted) { + xpath_node_set::type_t sorted = xpath_get_order(begin, end); + + if (sorted == xpath_node_set::type_unsorted) { + sort(begin, end, document_order_comparator()); + + type = xpath_node_set::type_sorted; + } else + type = sorted; + } + + if (type != order) + reverse(begin, end); + + return order; +} + +PUGI__FN xpath_node xpath_first(const xpath_node *begin, const xpath_node *end, + xpath_node_set::type_t type) { + if (begin == end) + return xpath_node(); + + switch (type) { + case xpath_node_set::type_sorted: + return *begin; + + case xpath_node_set::type_sorted_reverse: + return *(end - 1); + + case xpath_node_set::type_unsorted: + return *min_element(begin, end, document_order_comparator()); + + default: + assert(!"Invalid node set type"); + return xpath_node(); + } +} + +class xpath_node_set_raw { + xpath_node_set::type_t _type; + + xpath_node *_begin; + xpath_node *_end; + xpath_node *_eos; + +public: + xpath_node_set_raw() + : _type(xpath_node_set::type_unsorted), _begin(0), _end(0), _eos(0) {} + + xpath_node *begin() const { return _begin; } + + xpath_node *end() const { return _end; } + + bool empty() const { return _begin == _end; } + + size_t size() const { return static_cast(_end - _begin); } + + xpath_node first() const { return xpath_first(_begin, _end, _type); } + + void push_back_grow(const xpath_node &node, xpath_allocator *alloc); + + void push_back(const xpath_node &node, xpath_allocator *alloc) { + if (_end != _eos) + *_end++ = node; + else + push_back_grow(node, alloc); + } + + void append(const xpath_node *begin_, const xpath_node *end_, + xpath_allocator *alloc) { + if (begin_ == end_) + return; + + size_t size_ = static_cast(_end - _begin); + size_t capacity = static_cast(_eos - _begin); + size_t count = static_cast(end_ - begin_); + + if (size_ + count > capacity) { + // reallocate the old array or allocate a new one + xpath_node *data = static_cast( + alloc->reallocate(_begin, capacity * sizeof(xpath_node), + (size_ + count) * sizeof(xpath_node))); + assert(data); + + // finalize + _begin = data; + _end = data + size_; + _eos = data + size_ + count; + } + + memcpy(_end, begin_, count * sizeof(xpath_node)); + _end += count; + } + + void sort_do() { _type = xpath_sort(_begin, _end, _type, false); } + + void truncate(xpath_node *pos) { + assert(_begin <= pos && pos <= _end); + + _end = pos; + } + + void remove_duplicates() { + if (_type == xpath_node_set::type_unsorted) + sort(_begin, _end, duplicate_comparator()); + + _end = unique(_begin, _end); + } + + xpath_node_set::type_t type() const { return _type; } + + void set_type(xpath_node_set::type_t value) { _type = value; } +}; + +PUGI__FN_NO_INLINE void +xpath_node_set_raw::push_back_grow(const xpath_node &node, + xpath_allocator *alloc) { + size_t capacity = static_cast(_eos - _begin); + + // get new capacity (1.5x rule) + size_t new_capacity = capacity + capacity / 2 + 1; + + // reallocate the old array or allocate a new one + xpath_node *data = static_cast( + alloc->reallocate(_begin, capacity * sizeof(xpath_node), + new_capacity * sizeof(xpath_node))); + assert(data); + + // finalize + _begin = data; + _end = data + capacity; + _eos = data + new_capacity; + + // push + *_end++ = node; +} +PUGI__NS_END + +PUGI__NS_BEGIN +struct xpath_context { + xpath_node n; + size_t position, size; + + xpath_context(const xpath_node &n_, size_t position_, size_t size_) + : n(n_), position(position_), size(size_) {} +}; + +enum lexeme_t { + lex_none = 0, + lex_equal, + lex_not_equal, + lex_less, + lex_greater, + lex_less_or_equal, + lex_greater_or_equal, + lex_plus, + lex_minus, + lex_multiply, + lex_union, + lex_var_ref, + lex_open_brace, + lex_close_brace, + lex_quoted_string, + lex_number, + lex_slash, + lex_double_slash, + lex_open_square_brace, + lex_close_square_brace, + lex_string, + lex_comma, + lex_axis_attribute, + lex_dot, + lex_double_dot, + lex_double_colon, + lex_eof +}; + +struct xpath_lexer_string { + const char_t *begin; + const char_t *end; + + xpath_lexer_string() : begin(0), end(0) {} + + bool operator==(const char_t *other) const { + size_t length = static_cast(end - begin); + + return strequalrange(other, begin, length); + } +}; + +class xpath_lexer { + const char_t *_cur; + const char_t *_cur_lexeme_pos; + xpath_lexer_string _cur_lexeme_contents; + + lexeme_t _cur_lexeme; + +public: + explicit xpath_lexer(const char_t *query) : _cur(query) { next(); } + + const char_t *state() const { return _cur; } + + void next() { + const char_t *cur = _cur; + + while (PUGI__IS_CHARTYPE(*cur, ct_space)) + ++cur; + + // save lexeme position for error reporting + _cur_lexeme_pos = cur; + + switch (*cur) { + case 0: + _cur_lexeme = lex_eof; + break; + + case '>': + if (*(cur + 1) == '=') { + cur += 2; + _cur_lexeme = lex_greater_or_equal; + } else { + cur += 1; + _cur_lexeme = lex_greater; + } + break; + + case '<': + if (*(cur + 1) == '=') { + cur += 2; + _cur_lexeme = lex_less_or_equal; + } else { + cur += 1; + _cur_lexeme = lex_less; + } + break; + + case '!': + if (*(cur + 1) == '=') { + cur += 2; + _cur_lexeme = lex_not_equal; + } else { + _cur_lexeme = lex_none; + } + break; + + case '=': + cur += 1; + _cur_lexeme = lex_equal; + + break; + + case '+': + cur += 1; + _cur_lexeme = lex_plus; + + break; + + case '-': + cur += 1; + _cur_lexeme = lex_minus; + + break; + + case '*': + cur += 1; + _cur_lexeme = lex_multiply; + + break; + + case '|': + cur += 1; + _cur_lexeme = lex_union; + + break; + + case '$': + cur += 1; + + if (PUGI__IS_CHARTYPEX(*cur, ctx_start_symbol)) { + _cur_lexeme_contents.begin = cur; + + while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) + cur++; + + if (cur[0] == ':' && PUGI__IS_CHARTYPEX(cur[1], ctx_symbol)) // qname + { + cur++; // : + + while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) + cur++; + } + + _cur_lexeme_contents.end = cur; + + _cur_lexeme = lex_var_ref; + } else { + _cur_lexeme = lex_none; + } + + break; + + case '(': + cur += 1; + _cur_lexeme = lex_open_brace; + + break; + + case ')': + cur += 1; + _cur_lexeme = lex_close_brace; + + break; + + case '[': + cur += 1; + _cur_lexeme = lex_open_square_brace; + + break; + + case ']': + cur += 1; + _cur_lexeme = lex_close_square_brace; + + break; + + case ',': + cur += 1; + _cur_lexeme = lex_comma; + + break; + + case '/': + if (*(cur + 1) == '/') { + cur += 2; + _cur_lexeme = lex_double_slash; + } else { + cur += 1; + _cur_lexeme = lex_slash; + } + break; + + case '.': + if (*(cur + 1) == '.') { + cur += 2; + _cur_lexeme = lex_double_dot; + } else if (PUGI__IS_CHARTYPEX(*(cur + 1), ctx_digit)) { + _cur_lexeme_contents.begin = cur; // . + + ++cur; + + while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) + cur++; + + _cur_lexeme_contents.end = cur; + + _cur_lexeme = lex_number; + } else { + cur += 1; + _cur_lexeme = lex_dot; + } + break; + + case '@': + cur += 1; + _cur_lexeme = lex_axis_attribute; + + break; + + case '"': + case '\'': { + char_t terminator = *cur; + + ++cur; + + _cur_lexeme_contents.begin = cur; + while (*cur && *cur != terminator) + cur++; + _cur_lexeme_contents.end = cur; + + if (!*cur) + _cur_lexeme = lex_none; + else { + cur += 1; + _cur_lexeme = lex_quoted_string; + } + + break; + } + + case ':': + if (*(cur + 1) == ':') { + cur += 2; + _cur_lexeme = lex_double_colon; + } else { + _cur_lexeme = lex_none; + } + break; + + default: + if (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) { + _cur_lexeme_contents.begin = cur; + + while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) + cur++; + + if (*cur == '.') { + cur++; + + while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) + cur++; + } + + _cur_lexeme_contents.end = cur; + + _cur_lexeme = lex_number; + } else if (PUGI__IS_CHARTYPEX(*cur, ctx_start_symbol)) { + _cur_lexeme_contents.begin = cur; + + while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) + cur++; + + if (cur[0] == ':') { + if (cur[1] == '*') // namespace test ncname:* + { + cur += 2; // :* + } else if (PUGI__IS_CHARTYPEX(cur[1], + ctx_symbol)) // namespace test qname + { + cur++; // : + + while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) + cur++; + } + } + + _cur_lexeme_contents.end = cur; + + _cur_lexeme = lex_string; + } else { + _cur_lexeme = lex_none; + } + } + + _cur = cur; + } + + lexeme_t current() const { return _cur_lexeme; } + + const char_t *current_pos() const { return _cur_lexeme_pos; } + + const xpath_lexer_string &contents() const { + assert(_cur_lexeme == lex_var_ref || _cur_lexeme == lex_number || + _cur_lexeme == lex_string || _cur_lexeme == lex_quoted_string); + + return _cur_lexeme_contents; + } +}; + +enum ast_type_t { + ast_unknown, + ast_op_or, // left or right + ast_op_and, // left and right + ast_op_equal, // left = right + ast_op_not_equal, // left != right + ast_op_less, // left < right + ast_op_greater, // left > right + ast_op_less_or_equal, // left <= right + ast_op_greater_or_equal, // left >= right + ast_op_add, // left + right + ast_op_subtract, // left - right + ast_op_multiply, // left * right + ast_op_divide, // left / right + ast_op_mod, // left % right + ast_op_negate, // left - right + ast_op_union, // left | right + ast_predicate, // apply predicate to set; next points to next predicate + ast_filter, // select * from left where right + ast_string_constant, // string constant + ast_number_constant, // number constant + ast_variable, // variable + ast_func_last, // last() + ast_func_position, // position() + ast_func_count, // count(left) + ast_func_id, // id(left) + ast_func_local_name_0, // local-name() + ast_func_local_name_1, // local-name(left) + ast_func_namespace_uri_0, // namespace-uri() + ast_func_namespace_uri_1, // namespace-uri(left) + ast_func_name_0, // name() + ast_func_name_1, // name(left) + ast_func_string_0, // string() + ast_func_string_1, // string(left) + ast_func_concat, // concat(left, right, siblings) + ast_func_starts_with, // starts_with(left, right) + ast_func_contains, // contains(left, right) + ast_func_substring_before, // substring-before(left, right) + ast_func_substring_after, // substring-after(left, right) + ast_func_substring_2, // substring(left, right) + ast_func_substring_3, // substring(left, right, third) + ast_func_string_length_0, // string-length() + ast_func_string_length_1, // string-length(left) + ast_func_normalize_space_0, // normalize-space() + ast_func_normalize_space_1, // normalize-space(left) + ast_func_translate, // translate(left, right, third) + ast_func_boolean, // boolean(left) + ast_func_not, // not(left) + ast_func_true, // true() + ast_func_false, // false() + ast_func_lang, // lang(left) + ast_func_number_0, // number() + ast_func_number_1, // number(left) + ast_func_sum, // sum(left) + ast_func_floor, // floor(left) + ast_func_ceiling, // ceiling(left) + ast_func_round, // round(left) + ast_step, // process set left with step + ast_step_root, // select root node + + ast_opt_translate_table, // translate(left, right, third) where right/third + // are constants + ast_opt_compare_attribute // @name = 'string' +}; + +enum axis_t { + axis_ancestor, + axis_ancestor_or_self, + axis_attribute, + axis_child, + axis_descendant, + axis_descendant_or_self, + axis_following, + axis_following_sibling, + axis_namespace, + axis_parent, + axis_preceding, + axis_preceding_sibling, + axis_self +}; + +enum nodetest_t { + nodetest_none, + nodetest_name, + nodetest_type_node, + nodetest_type_comment, + nodetest_type_pi, + nodetest_type_text, + nodetest_pi, + nodetest_all, + nodetest_all_in_namespace +}; + +enum predicate_t { + predicate_default, + predicate_posinv, + predicate_constant, + predicate_constant_one +}; + +enum nodeset_eval_t { nodeset_eval_all, nodeset_eval_any, nodeset_eval_first }; + +template struct axis_to_type { static const axis_t axis; }; + +template const axis_t axis_to_type::axis = N; + +class xpath_ast_node { +private: + // node type + char _type; + char _rettype; + + // for ast_step + char _axis; + + // for ast_step/ast_predicate/ast_filter + char _test; + + // tree node structure + xpath_ast_node *_left; + xpath_ast_node *_right; + xpath_ast_node *_next; + + union { + // value for ast_string_constant + const char_t *string; + // value for ast_number_constant + double number; + // variable for ast_variable + xpath_variable *variable; + // node test for ast_step (node name/namespace/node type/pi target) + const char_t *nodetest; + // table for ast_opt_translate_table + const unsigned char *table; + } _data; + + xpath_ast_node(const xpath_ast_node &); + xpath_ast_node &operator=(const xpath_ast_node &); + + template + static bool compare_eq(xpath_ast_node *lhs, xpath_ast_node *rhs, + const xpath_context &c, const xpath_stack &stack, + const Comp &comp) { + xpath_value_type lt = lhs->rettype(), rt = rhs->rettype(); + + if (lt != xpath_type_node_set && rt != xpath_type_node_set) { + if (lt == xpath_type_boolean || rt == xpath_type_boolean) + return comp(lhs->eval_boolean(c, stack), rhs->eval_boolean(c, stack)); + else if (lt == xpath_type_number || rt == xpath_type_number) + return comp(lhs->eval_number(c, stack), rhs->eval_number(c, stack)); + else if (lt == xpath_type_string || rt == xpath_type_string) { + xpath_allocator_capture cr(stack.result); + + xpath_string ls = lhs->eval_string(c, stack); + xpath_string rs = rhs->eval_string(c, stack); + + return comp(ls, rs); + } + } else if (lt == xpath_type_node_set && rt == xpath_type_node_set) { + xpath_allocator_capture cr(stack.result); + + xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all); + xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); + + for (const xpath_node *li = ls.begin(); li != ls.end(); ++li) + for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { + xpath_allocator_capture cri(stack.result); + + if (comp(string_value(*li, stack.result), + string_value(*ri, stack.result))) + return true; + } + + return false; + } else { + if (lt == xpath_type_node_set) { + swap(lhs, rhs); + swap(lt, rt); + } + + if (lt == xpath_type_boolean) + return comp(lhs->eval_boolean(c, stack), rhs->eval_boolean(c, stack)); + else if (lt == xpath_type_number) { + xpath_allocator_capture cr(stack.result); + + double l = lhs->eval_number(c, stack); + xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); + + for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { + xpath_allocator_capture cri(stack.result); + + if (comp(l, convert_string_to_number( + string_value(*ri, stack.result).c_str()))) + return true; + } + + return false; + } else if (lt == xpath_type_string) { + xpath_allocator_capture cr(stack.result); + + xpath_string l = lhs->eval_string(c, stack); + xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); + + for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { + xpath_allocator_capture cri(stack.result); + + if (comp(l, string_value(*ri, stack.result))) + return true; + } + + return false; + } + } + + assert(!"Wrong types"); + return false; + } + + static bool eval_once(xpath_node_set::type_t type, nodeset_eval_t eval) { + return type == xpath_node_set::type_sorted ? eval != nodeset_eval_all + : eval == nodeset_eval_any; + } + + template + static bool compare_rel(xpath_ast_node *lhs, xpath_ast_node *rhs, + const xpath_context &c, const xpath_stack &stack, + const Comp &comp) { + xpath_value_type lt = lhs->rettype(), rt = rhs->rettype(); + + if (lt != xpath_type_node_set && rt != xpath_type_node_set) + return comp(lhs->eval_number(c, stack), rhs->eval_number(c, stack)); + else if (lt == xpath_type_node_set && rt == xpath_type_node_set) { + xpath_allocator_capture cr(stack.result); + + xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all); + xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); + + for (const xpath_node *li = ls.begin(); li != ls.end(); ++li) { + xpath_allocator_capture cri(stack.result); + + double l = + convert_string_to_number(string_value(*li, stack.result).c_str()); + + for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { + xpath_allocator_capture crii(stack.result); + + if (comp(l, convert_string_to_number( + string_value(*ri, stack.result).c_str()))) + return true; + } + } + + return false; + } else if (lt != xpath_type_node_set && rt == xpath_type_node_set) { + xpath_allocator_capture cr(stack.result); + + double l = lhs->eval_number(c, stack); + xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); + + for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { + xpath_allocator_capture cri(stack.result); + + if (comp(l, convert_string_to_number( + string_value(*ri, stack.result).c_str()))) + return true; + } + + return false; + } else if (lt == xpath_type_node_set && rt != xpath_type_node_set) { + xpath_allocator_capture cr(stack.result); + + xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all); + double r = rhs->eval_number(c, stack); + + for (const xpath_node *li = ls.begin(); li != ls.end(); ++li) { + xpath_allocator_capture cri(stack.result); + + if (comp(convert_string_to_number( + string_value(*li, stack.result).c_str()), + r)) + return true; + } + + return false; + } else { + assert(!"Wrong types"); + return false; + } + } + + static void apply_predicate_boolean(xpath_node_set_raw &ns, size_t first, + xpath_ast_node *expr, + const xpath_stack &stack, bool once) { + assert(ns.size() >= first); + assert(expr->rettype() != xpath_type_number); + + size_t i = 1; + size_t size = ns.size() - first; + + xpath_node *last = ns.begin() + first; + + // remove_if... or well, sort of + for (xpath_node *it = last; it != ns.end(); ++it, ++i) { + xpath_context c(*it, i, size); + + if (expr->eval_boolean(c, stack)) { + *last++ = *it; + + if (once) + break; + } + } + + ns.truncate(last); + } + + static void apply_predicate_number(xpath_node_set_raw &ns, size_t first, + xpath_ast_node *expr, + const xpath_stack &stack, bool once) { + assert(ns.size() >= first); + assert(expr->rettype() == xpath_type_number); + + size_t i = 1; + size_t size = ns.size() - first; + + xpath_node *last = ns.begin() + first; + + // remove_if... or well, sort of + for (xpath_node *it = last; it != ns.end(); ++it, ++i) { + xpath_context c(*it, i, size); + + if (expr->eval_number(c, stack) == i) { + *last++ = *it; + + if (once) + break; + } + } + + ns.truncate(last); + } + + static void apply_predicate_number_const(xpath_node_set_raw &ns, size_t first, + xpath_ast_node *expr, + const xpath_stack &stack) { + assert(ns.size() >= first); + assert(expr->rettype() == xpath_type_number); + + size_t size = ns.size() - first; + + xpath_node *last = ns.begin() + first; + + xpath_context c(xpath_node(), 1, size); + + double er = expr->eval_number(c, stack); + + if (er >= 1.0 && er <= size) { + size_t eri = static_cast(er); + + if (er == eri) { + xpath_node r = last[eri - 1]; + + *last++ = r; + } + } + + ns.truncate(last); + } + + void apply_predicate(xpath_node_set_raw &ns, size_t first, + const xpath_stack &stack, bool once) { + if (ns.size() == first) + return; + + assert(_type == ast_filter || _type == ast_predicate); + + if (_test == predicate_constant || _test == predicate_constant_one) + apply_predicate_number_const(ns, first, _right, stack); + else if (_right->rettype() == xpath_type_number) + apply_predicate_number(ns, first, _right, stack, once); + else + apply_predicate_boolean(ns, first, _right, stack, once); + } + + void apply_predicates(xpath_node_set_raw &ns, size_t first, + const xpath_stack &stack, nodeset_eval_t eval) { + if (ns.size() == first) + return; + + bool last_once = eval_once(ns.type(), eval); + + for (xpath_ast_node *pred = _right; pred; pred = pred->_next) + pred->apply_predicate(ns, first, stack, !pred->_next && last_once); + } + + bool step_push(xpath_node_set_raw &ns, xml_attribute_struct *a, + xml_node_struct *parent, xpath_allocator *alloc) { + assert(a); + + const char_t *name = a->name ? a->name + 0 : PUGIXML_TEXT(""); + + switch (_test) { + case nodetest_name: + if (strequal(name, _data.nodetest) && is_xpath_attribute(name)) { + ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc); + return true; + } + break; + + case nodetest_type_node: + case nodetest_all: + if (is_xpath_attribute(name)) { + ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc); + return true; + } + break; + + case nodetest_all_in_namespace: + if (starts_with(name, _data.nodetest) && is_xpath_attribute(name)) { + ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc); + return true; + } + break; + + default:; + } + + return false; + } + + bool step_push(xpath_node_set_raw &ns, xml_node_struct *n, + xpath_allocator *alloc) { + assert(n); + + xml_node_type type = PUGI__NODETYPE(n); + + switch (_test) { + case nodetest_name: + if (type == node_element && n->name && + strequal(n->name, _data.nodetest)) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + case nodetest_type_node: + ns.push_back(xml_node(n), alloc); + return true; + + case nodetest_type_comment: + if (type == node_comment) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + case nodetest_type_text: + if (type == node_pcdata || type == node_cdata) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + case nodetest_type_pi: + if (type == node_pi) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + case nodetest_pi: + if (type == node_pi && n->name && strequal(n->name, _data.nodetest)) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + case nodetest_all: + if (type == node_element) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + case nodetest_all_in_namespace: + if (type == node_element && n->name && + starts_with(n->name, _data.nodetest)) { + ns.push_back(xml_node(n), alloc); + return true; + } + break; + + default: + assert(!"Unknown axis"); + } + + return false; + } + + template + void step_fill(xpath_node_set_raw &ns, xml_node_struct *n, + xpath_allocator *alloc, bool once, T) { + const axis_t axis = T::axis; + + switch (axis) { + case axis_attribute: { + for (xml_attribute_struct *a = n->first_attribute; a; + a = a->next_attribute) + if (step_push(ns, a, n, alloc) & once) + return; + + break; + } + + case axis_child: { + for (xml_node_struct *c = n->first_child; c; c = c->next_sibling) + if (step_push(ns, c, alloc) & once) + return; + + break; + } + + case axis_descendant: + case axis_descendant_or_self: { + if (axis == axis_descendant_or_self) + if (step_push(ns, n, alloc) & once) + return; + + xml_node_struct *cur = n->first_child; + + while (cur) { + if (step_push(ns, cur, alloc) & once) + return; + + if (cur->first_child) + cur = cur->first_child; + else { + while (!cur->next_sibling) { + cur = cur->parent; + + if (cur == n) + return; + } + + cur = cur->next_sibling; + } + } + + break; + } + + case axis_following_sibling: { + for (xml_node_struct *c = n->next_sibling; c; c = c->next_sibling) + if (step_push(ns, c, alloc) & once) + return; + + break; + } + + case axis_preceding_sibling: { + for (xml_node_struct *c = n->prev_sibling_c; c->next_sibling; + c = c->prev_sibling_c) + if (step_push(ns, c, alloc) & once) + return; + + break; + } + + case axis_following: { + xml_node_struct *cur = n; + + // exit from this node so that we don't include descendants + while (!cur->next_sibling) { + cur = cur->parent; + + if (!cur) + return; + } + + cur = cur->next_sibling; + + while (cur) { + if (step_push(ns, cur, alloc) & once) + return; + + if (cur->first_child) + cur = cur->first_child; + else { + while (!cur->next_sibling) { + cur = cur->parent; + + if (!cur) + return; + } + + cur = cur->next_sibling; + } + } + + break; + } + + case axis_preceding: { + xml_node_struct *cur = n; + + // exit from this node so that we don't include descendants + while (!cur->prev_sibling_c->next_sibling) { + cur = cur->parent; + + if (!cur) + return; + } + + cur = cur->prev_sibling_c; + + while (cur) { + if (cur->first_child) + cur = cur->first_child->prev_sibling_c; + else { + // leaf node, can't be ancestor + if (step_push(ns, cur, alloc) & once) + return; + + while (!cur->prev_sibling_c->next_sibling) { + cur = cur->parent; + + if (!cur) + return; + + if (!node_is_ancestor(cur, n)) + if (step_push(ns, cur, alloc) & once) + return; + } + + cur = cur->prev_sibling_c; + } + } + + break; + } + + case axis_ancestor: + case axis_ancestor_or_self: { + if (axis == axis_ancestor_or_self) + if (step_push(ns, n, alloc) & once) + return; + + xml_node_struct *cur = n->parent; + + while (cur) { + if (step_push(ns, cur, alloc) & once) + return; + + cur = cur->parent; + } + + break; + } + + case axis_self: { + step_push(ns, n, alloc); + + break; + } + + case axis_parent: { + if (n->parent) + step_push(ns, n->parent, alloc); + + break; + } + + default: + assert(!"Unimplemented axis"); + } + } + + template + void step_fill(xpath_node_set_raw &ns, xml_attribute_struct *a, + xml_node_struct *p, xpath_allocator *alloc, bool once, T v) { + const axis_t axis = T::axis; + + switch (axis) { + case axis_ancestor: + case axis_ancestor_or_self: { + if (axis == axis_ancestor_or_self && + _test == nodetest_type_node) // reject attributes based on principal + // node type test + if (step_push(ns, a, p, alloc) & once) + return; + + xml_node_struct *cur = p; + + while (cur) { + if (step_push(ns, cur, alloc) & once) + return; + + cur = cur->parent; + } + + break; + } + + case axis_descendant_or_self: + case axis_self: { + if (_test == nodetest_type_node) // reject attributes based on principal + // node type test + step_push(ns, a, p, alloc); + + break; + } + + case axis_following: { + xml_node_struct *cur = p; + + while (cur) { + if (cur->first_child) + cur = cur->first_child; + else { + while (!cur->next_sibling) { + cur = cur->parent; + + if (!cur) + return; + } + + cur = cur->next_sibling; + } + + if (step_push(ns, cur, alloc) & once) + return; + } + + break; + } + + case axis_parent: { + step_push(ns, p, alloc); + + break; + } + + case axis_preceding: { + // preceding:: axis does not include attribute nodes and attribute + // ancestors (they are the same as parent's ancestors), so we can reuse + // node preceding + step_fill(ns, p, alloc, once, v); + break; + } + + default: + assert(!"Unimplemented axis"); + } + } + + template + void step_fill(xpath_node_set_raw &ns, const xpath_node &xn, + xpath_allocator *alloc, bool once, T v) { + const axis_t axis = T::axis; + const bool axis_has_attributes = + (axis == axis_ancestor || axis == axis_ancestor_or_self || + axis == axis_descendant_or_self || axis == axis_following || + axis == axis_parent || axis == axis_preceding || axis == axis_self); + + if (xn.node()) + step_fill(ns, xn.node().internal_object(), alloc, once, v); + else if (axis_has_attributes && xn.attribute() && xn.parent()) + step_fill(ns, xn.attribute().internal_object(), + xn.parent().internal_object(), alloc, once, v); + } + + template + xpath_node_set_raw step_do(const xpath_context &c, const xpath_stack &stack, + nodeset_eval_t eval, T v) { + const axis_t axis = T::axis; + const bool axis_reverse = + (axis == axis_ancestor || axis == axis_ancestor_or_self || + axis == axis_preceding || axis == axis_preceding_sibling); + const xpath_node_set::type_t axis_type = + axis_reverse ? xpath_node_set::type_sorted_reverse + : xpath_node_set::type_sorted; + + bool once = + (axis == axis_attribute && _test == nodetest_name) || + (!_right && eval_once(axis_type, eval)) || + (_right && !_right->_next && _right->_test == predicate_constant_one); + + xpath_node_set_raw ns; + ns.set_type(axis_type); + + if (_left) { + xpath_node_set_raw s = _left->eval_node_set(c, stack, nodeset_eval_all); + + // self axis preserves the original order + if (axis == axis_self) + ns.set_type(s.type()); + + for (const xpath_node *it = s.begin(); it != s.end(); ++it) { + size_t size = ns.size(); + + // in general, all axes generate elements in a particular order, but + // there is no order guarantee if axis is applied to two nodes + if (axis != axis_self && size != 0) + ns.set_type(xpath_node_set::type_unsorted); + + step_fill(ns, *it, stack.result, once, v); + if (_right) + apply_predicates(ns, size, stack, eval); + } + } else { + step_fill(ns, c.n, stack.result, once, v); + if (_right) + apply_predicates(ns, 0, stack, eval); + } + + // child, attribute and self axes always generate unique set of nodes + // for other axis, if the set stayed sorted, it stayed unique because the + // traversal algorithms do not visit the same node twice + if (axis != axis_child && axis != axis_attribute && axis != axis_self && + ns.type() == xpath_node_set::type_unsorted) + ns.remove_duplicates(); + + return ns; + } + +public: + xpath_ast_node(ast_type_t type, xpath_value_type rettype_, + const char_t *value) + : _type(static_cast(type)), _rettype(static_cast(rettype_)), + _axis(0), _test(0), _left(0), _right(0), _next(0) { + assert(type == ast_string_constant); + _data.string = value; + } + + xpath_ast_node(ast_type_t type, xpath_value_type rettype_, double value) + : _type(static_cast(type)), _rettype(static_cast(rettype_)), + _axis(0), _test(0), _left(0), _right(0), _next(0) { + assert(type == ast_number_constant); + _data.number = value; + } + + xpath_ast_node(ast_type_t type, xpath_value_type rettype_, + xpath_variable *value) + : _type(static_cast(type)), _rettype(static_cast(rettype_)), + _axis(0), _test(0), _left(0), _right(0), _next(0) { + assert(type == ast_variable); + _data.variable = value; + } + + xpath_ast_node(ast_type_t type, xpath_value_type rettype_, + xpath_ast_node *left = 0, xpath_ast_node *right = 0) + : _type(static_cast(type)), _rettype(static_cast(rettype_)), + _axis(0), _test(0), _left(left), _right(right), _next(0) {} + + xpath_ast_node(ast_type_t type, xpath_ast_node *left, axis_t axis, + nodetest_t test, const char_t *contents) + : _type(static_cast(type)), _rettype(xpath_type_node_set), + _axis(static_cast(axis)), _test(static_cast(test)), + _left(left), _right(0), _next(0) { + assert(type == ast_step); + _data.nodetest = contents; + } + + xpath_ast_node(ast_type_t type, xpath_ast_node *left, xpath_ast_node *right, + predicate_t test) + : _type(static_cast(type)), _rettype(xpath_type_node_set), _axis(0), + _test(static_cast(test)), _left(left), _right(right), _next(0) { + assert(type == ast_filter || type == ast_predicate); + } + + void set_next(xpath_ast_node *value) { _next = value; } + + void set_right(xpath_ast_node *value) { _right = value; } + + bool eval_boolean(const xpath_context &c, const xpath_stack &stack) { + switch (_type) { + case ast_op_or: + return _left->eval_boolean(c, stack) || _right->eval_boolean(c, stack); + + case ast_op_and: + return _left->eval_boolean(c, stack) && _right->eval_boolean(c, stack); + + case ast_op_equal: + return compare_eq(_left, _right, c, stack, equal_to()); + + case ast_op_not_equal: + return compare_eq(_left, _right, c, stack, not_equal_to()); + + case ast_op_less: + return compare_rel(_left, _right, c, stack, less()); + + case ast_op_greater: + return compare_rel(_right, _left, c, stack, less()); + + case ast_op_less_or_equal: + return compare_rel(_left, _right, c, stack, less_equal()); + + case ast_op_greater_or_equal: + return compare_rel(_right, _left, c, stack, less_equal()); + + case ast_func_starts_with: { + xpath_allocator_capture cr(stack.result); + + xpath_string lr = _left->eval_string(c, stack); + xpath_string rr = _right->eval_string(c, stack); + + return starts_with(lr.c_str(), rr.c_str()); + } + + case ast_func_contains: { + xpath_allocator_capture cr(stack.result); + + xpath_string lr = _left->eval_string(c, stack); + xpath_string rr = _right->eval_string(c, stack); + + return find_substring(lr.c_str(), rr.c_str()) != 0; + } + + case ast_func_boolean: + return _left->eval_boolean(c, stack); + + case ast_func_not: + return !_left->eval_boolean(c, stack); + + case ast_func_true: + return true; + + case ast_func_false: + return false; + + case ast_func_lang: { + if (c.n.attribute()) + return false; + + xpath_allocator_capture cr(stack.result); + + xpath_string lang = _left->eval_string(c, stack); + + for (xml_node n = c.n.node(); n; n = n.parent()) { + xml_attribute a = n.attribute(PUGIXML_TEXT("xml:lang")); + + if (a) { + const char_t *value = a.value(); + + // strnicmp / strncasecmp is not portable + for (const char_t *lit = lang.c_str(); *lit; ++lit) { + if (tolower_ascii(*lit) != tolower_ascii(*value)) + return false; + ++value; + } + + return *value == 0 || *value == '-'; + } + } + + return false; + } + + case ast_opt_compare_attribute: { + const char_t *value = (_right->_type == ast_string_constant) + ? _right->_data.string + : _right->_data.variable->get_string(); + + xml_attribute attr = c.n.node().attribute(_left->_data.nodetest); + + return attr && strequal(attr.value(), value) && + is_xpath_attribute(attr.name()); + } + + case ast_variable: { + assert(_rettype == _data.variable->type()); + + if (_rettype == xpath_type_boolean) + return _data.variable->get_boolean(); + + // fallthrough to type conversion + } + + default: { + switch (_rettype) { + case xpath_type_number: + return convert_number_to_boolean(eval_number(c, stack)); + + case xpath_type_string: { + xpath_allocator_capture cr(stack.result); + + return !eval_string(c, stack).empty(); + } + + case xpath_type_node_set: { + xpath_allocator_capture cr(stack.result); + + return !eval_node_set(c, stack, nodeset_eval_any).empty(); + } + + default: + assert(!"Wrong expression for return type boolean"); + return false; + } + } + } + } + + double eval_number(const xpath_context &c, const xpath_stack &stack) { + switch (_type) { + case ast_op_add: + return _left->eval_number(c, stack) + _right->eval_number(c, stack); + + case ast_op_subtract: + return _left->eval_number(c, stack) - _right->eval_number(c, stack); + + case ast_op_multiply: + return _left->eval_number(c, stack) * _right->eval_number(c, stack); + + case ast_op_divide: + return _left->eval_number(c, stack) / _right->eval_number(c, stack); + + case ast_op_mod: + return fmod(_left->eval_number(c, stack), _right->eval_number(c, stack)); + + case ast_op_negate: + return -_left->eval_number(c, stack); + + case ast_number_constant: + return _data.number; + + case ast_func_last: + return static_cast(c.size); + + case ast_func_position: + return static_cast(c.position); + + case ast_func_count: { + xpath_allocator_capture cr(stack.result); + + return static_cast( + _left->eval_node_set(c, stack, nodeset_eval_all).size()); + } + + case ast_func_string_length_0: { + xpath_allocator_capture cr(stack.result); + + return static_cast(string_value(c.n, stack.result).length()); + } + + case ast_func_string_length_1: { + xpath_allocator_capture cr(stack.result); + + return static_cast(_left->eval_string(c, stack).length()); + } + + case ast_func_number_0: { + xpath_allocator_capture cr(stack.result); + + return convert_string_to_number(string_value(c.n, stack.result).c_str()); + } + + case ast_func_number_1: + return _left->eval_number(c, stack); + + case ast_func_sum: { + xpath_allocator_capture cr(stack.result); + + double r = 0; + + xpath_node_set_raw ns = _left->eval_node_set(c, stack, nodeset_eval_all); + + for (const xpath_node *it = ns.begin(); it != ns.end(); ++it) { + xpath_allocator_capture cri(stack.result); + + r += convert_string_to_number(string_value(*it, stack.result).c_str()); + } + + return r; + } + + case ast_func_floor: { + double r = _left->eval_number(c, stack); + + return r == r ? floor(r) : r; + } + + case ast_func_ceiling: { + double r = _left->eval_number(c, stack); + + return r == r ? ceil(r) : r; + } + + case ast_func_round: + return round_nearest_nzero(_left->eval_number(c, stack)); + + case ast_variable: { + assert(_rettype == _data.variable->type()); + + if (_rettype == xpath_type_number) + return _data.variable->get_number(); + + // fallthrough to type conversion + } + + default: { + switch (_rettype) { + case xpath_type_boolean: + return eval_boolean(c, stack) ? 1 : 0; + + case xpath_type_string: { + xpath_allocator_capture cr(stack.result); + + return convert_string_to_number(eval_string(c, stack).c_str()); + } + + case xpath_type_node_set: { + xpath_allocator_capture cr(stack.result); + + return convert_string_to_number(eval_string(c, stack).c_str()); + } + + default: + assert(!"Wrong expression for return type number"); + return 0; + } + } + } + } + + xpath_string eval_string_concat(const xpath_context &c, + const xpath_stack &stack) { + assert(_type == ast_func_concat); + + xpath_allocator_capture ct(stack.temp); + + // count the string number + size_t count = 1; + for (xpath_ast_node *nc = _right; nc; nc = nc->_next) + count++; + + // gather all strings + xpath_string static_buffer[4]; + xpath_string *buffer = static_buffer; + + // allocate on-heap for large concats + if (count > sizeof(static_buffer) / sizeof(static_buffer[0])) { + buffer = static_cast( + stack.temp->allocate(count * sizeof(xpath_string))); + assert(buffer); + } + + // evaluate all strings to temporary stack + xpath_stack swapped_stack = {stack.temp, stack.result}; + + buffer[0] = _left->eval_string(c, swapped_stack); + + size_t pos = 1; + for (xpath_ast_node *n = _right; n; n = n->_next, ++pos) + buffer[pos] = n->eval_string(c, swapped_stack); + assert(pos == count); + + // get total length + size_t length = 0; + for (size_t i = 0; i < count; ++i) + length += buffer[i].length(); + + // create final string + char_t *result = static_cast( + stack.result->allocate((length + 1) * sizeof(char_t))); + assert(result); + + char_t *ri = result; + + for (size_t j = 0; j < count; ++j) + for (const char_t *bi = buffer[j].c_str(); *bi; ++bi) + *ri++ = *bi; + + *ri = 0; + + return xpath_string::from_heap_preallocated(result, ri); + } + + xpath_string eval_string(const xpath_context &c, const xpath_stack &stack) { + switch (_type) { + case ast_string_constant: + return xpath_string::from_const(_data.string); + + case ast_func_local_name_0: { + xpath_node na = c.n; + + return xpath_string::from_const(local_name(na)); + } + + case ast_func_local_name_1: { + xpath_allocator_capture cr(stack.result); + + xpath_node_set_raw ns = + _left->eval_node_set(c, stack, nodeset_eval_first); + xpath_node na = ns.first(); + + return xpath_string::from_const(local_name(na)); + } + + case ast_func_name_0: { + xpath_node na = c.n; + + return xpath_string::from_const(qualified_name(na)); + } + + case ast_func_name_1: { + xpath_allocator_capture cr(stack.result); + + xpath_node_set_raw ns = + _left->eval_node_set(c, stack, nodeset_eval_first); + xpath_node na = ns.first(); + + return xpath_string::from_const(qualified_name(na)); + } + + case ast_func_namespace_uri_0: { + xpath_node na = c.n; + + return xpath_string::from_const(namespace_uri(na)); + } + + case ast_func_namespace_uri_1: { + xpath_allocator_capture cr(stack.result); + + xpath_node_set_raw ns = + _left->eval_node_set(c, stack, nodeset_eval_first); + xpath_node na = ns.first(); + + return xpath_string::from_const(namespace_uri(na)); + } + + case ast_func_string_0: + return string_value(c.n, stack.result); + + case ast_func_string_1: + return _left->eval_string(c, stack); + + case ast_func_concat: + return eval_string_concat(c, stack); + + case ast_func_substring_before: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_string s = _left->eval_string(c, swapped_stack); + xpath_string p = _right->eval_string(c, swapped_stack); + + const char_t *pos = find_substring(s.c_str(), p.c_str()); + + return pos ? xpath_string::from_heap(s.c_str(), pos, stack.result) + : xpath_string(); + } + + case ast_func_substring_after: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_string s = _left->eval_string(c, swapped_stack); + xpath_string p = _right->eval_string(c, swapped_stack); + + const char_t *pos = find_substring(s.c_str(), p.c_str()); + if (!pos) + return xpath_string(); + + const char_t *rbegin = pos + p.length(); + const char_t *rend = s.c_str() + s.length(); + + return s.uses_heap() ? xpath_string::from_heap(rbegin, rend, stack.result) + : xpath_string::from_const(rbegin); + } + + case ast_func_substring_2: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_string s = _left->eval_string(c, swapped_stack); + size_t s_length = s.length(); + + double first = round_nearest(_right->eval_number(c, stack)); + + if (is_nan(first)) + return xpath_string(); // NaN + else if (first >= s_length + 1) + return xpath_string(); + + size_t pos = first < 1 ? 1 : static_cast(first); + assert(1 <= pos && pos <= s_length + 1); + + const char_t *rbegin = s.c_str() + (pos - 1); + const char_t *rend = s.c_str() + s.length(); + + return s.uses_heap() ? xpath_string::from_heap(rbegin, rend, stack.result) + : xpath_string::from_const(rbegin); + } + + case ast_func_substring_3: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_string s = _left->eval_string(c, swapped_stack); + size_t s_length = s.length(); + + double first = round_nearest(_right->eval_number(c, stack)); + double last = first + round_nearest(_right->_next->eval_number(c, stack)); + + if (is_nan(first) || is_nan(last)) + return xpath_string(); + else if (first >= s_length + 1) + return xpath_string(); + else if (first >= last) + return xpath_string(); + else if (last < 1) + return xpath_string(); + + size_t pos = first < 1 ? 1 : static_cast(first); + size_t end = + last >= s_length + 1 ? s_length + 1 : static_cast(last); + + assert(1 <= pos && pos <= end && end <= s_length + 1); + const char_t *rbegin = s.c_str() + (pos - 1); + const char_t *rend = s.c_str() + (end - 1); + + return (end == s_length + 1 && !s.uses_heap()) + ? xpath_string::from_const(rbegin) + : xpath_string::from_heap(rbegin, rend, stack.result); + } + + case ast_func_normalize_space_0: { + xpath_string s = string_value(c.n, stack.result); + + char_t *begin = s.data(stack.result); + char_t *end = normalize_space(begin); + + return xpath_string::from_heap_preallocated(begin, end); + } + + case ast_func_normalize_space_1: { + xpath_string s = _left->eval_string(c, stack); + + char_t *begin = s.data(stack.result); + char_t *end = normalize_space(begin); + + return xpath_string::from_heap_preallocated(begin, end); + } + + case ast_func_translate: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_string s = _left->eval_string(c, stack); + xpath_string from = _right->eval_string(c, swapped_stack); + xpath_string to = _right->_next->eval_string(c, swapped_stack); + + char_t *begin = s.data(stack.result); + char_t *end = translate(begin, from.c_str(), to.c_str(), to.length()); + + return xpath_string::from_heap_preallocated(begin, end); + } + + case ast_opt_translate_table: { + xpath_string s = _left->eval_string(c, stack); + + char_t *begin = s.data(stack.result); + char_t *end = translate_table(begin, _data.table); + + return xpath_string::from_heap_preallocated(begin, end); + } + + case ast_variable: { + assert(_rettype == _data.variable->type()); + + if (_rettype == xpath_type_string) + return xpath_string::from_const(_data.variable->get_string()); + + // fallthrough to type conversion + } + + default: { + switch (_rettype) { + case xpath_type_boolean: + return xpath_string::from_const(eval_boolean(c, stack) + ? PUGIXML_TEXT("true") + : PUGIXML_TEXT("false")); + + case xpath_type_number: + return convert_number_to_string(eval_number(c, stack), stack.result); + + case xpath_type_node_set: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_node_set_raw ns = + eval_node_set(c, swapped_stack, nodeset_eval_first); + return ns.empty() ? xpath_string() + : string_value(ns.first(), stack.result); + } + + default: + assert(!"Wrong expression for return type string"); + return xpath_string(); + } + } + } + } + + xpath_node_set_raw eval_node_set(const xpath_context &c, + const xpath_stack &stack, + nodeset_eval_t eval) { + switch (_type) { + case ast_op_union: { + xpath_allocator_capture cr(stack.temp); + + xpath_stack swapped_stack = {stack.temp, stack.result}; + + xpath_node_set_raw ls = _left->eval_node_set(c, swapped_stack, eval); + xpath_node_set_raw rs = _right->eval_node_set(c, stack, eval); + + // we can optimize merging two sorted sets, but this is a very rare + // operation, so don't bother + rs.set_type(xpath_node_set::type_unsorted); + + rs.append(ls.begin(), ls.end(), stack.result); + rs.remove_duplicates(); + + return rs; + } + + case ast_filter: { + xpath_node_set_raw set = _left->eval_node_set( + c, stack, + _test == predicate_constant_one ? nodeset_eval_first + : nodeset_eval_all); + + // either expression is a number or it contains position() call; sort by + // document order + if (_test != predicate_posinv) + set.sort_do(); + + bool once = eval_once(set.type(), eval); + + apply_predicate(set, 0, stack, once); + + return set; + } + + case ast_func_id: + return xpath_node_set_raw(); + + case ast_step: { + switch (_axis) { + case axis_ancestor: + return step_do(c, stack, eval, axis_to_type()); + + case axis_ancestor_or_self: + return step_do(c, stack, eval, axis_to_type()); + + case axis_attribute: + return step_do(c, stack, eval, axis_to_type()); + + case axis_child: + return step_do(c, stack, eval, axis_to_type()); + + case axis_descendant: + return step_do(c, stack, eval, axis_to_type()); + + case axis_descendant_or_self: + return step_do(c, stack, eval, axis_to_type()); + + case axis_following: + return step_do(c, stack, eval, axis_to_type()); + + case axis_following_sibling: + return step_do(c, stack, eval, axis_to_type()); + + case axis_namespace: + // namespaced axis is not supported + return xpath_node_set_raw(); + + case axis_parent: + return step_do(c, stack, eval, axis_to_type()); + + case axis_preceding: + return step_do(c, stack, eval, axis_to_type()); + + case axis_preceding_sibling: + return step_do(c, stack, eval, axis_to_type()); + + case axis_self: + return step_do(c, stack, eval, axis_to_type()); + + default: + assert(!"Unknown axis"); + return xpath_node_set_raw(); + } + } + + case ast_step_root: { + assert(!_right); // root step can't have any predicates + + xpath_node_set_raw ns; + + ns.set_type(xpath_node_set::type_sorted); + + if (c.n.node()) + ns.push_back(c.n.node().root(), stack.result); + else if (c.n.attribute()) + ns.push_back(c.n.parent().root(), stack.result); + + return ns; + } + + case ast_variable: { + assert(_rettype == _data.variable->type()); + + if (_rettype == xpath_type_node_set) { + const xpath_node_set &s = _data.variable->get_node_set(); + + xpath_node_set_raw ns; + + ns.set_type(s.type()); + ns.append(s.begin(), s.end(), stack.result); + + return ns; + } + + // fallthrough to type conversion + } + + default: + assert(!"Wrong expression for return type node set"); + return xpath_node_set_raw(); + } + } + + void optimize(xpath_allocator *alloc) { + if (_left) + _left->optimize(alloc); + if (_right) + _right->optimize(alloc); + if (_next) + _next->optimize(alloc); + + optimize_self(alloc); + } + + void optimize_self(xpath_allocator *alloc) { + // Rewrite [position()=expr] with [expr] + // Note that this step has to go before classification to recognize + // [position()=1] + if ((_type == ast_filter || _type == ast_predicate) && + _right->_type == ast_op_equal && + _right->_left->_type == ast_func_position && + _right->_right->_rettype == xpath_type_number) { + _right = _right->_right; + } + + // Classify filter/predicate ops to perform various optimizations during + // evaluation + if (_type == ast_filter || _type == ast_predicate) { + assert(_test == predicate_default); + + if (_right->_type == ast_number_constant && _right->_data.number == 1.0) + _test = predicate_constant_one; + else if (_right->_rettype == xpath_type_number && + (_right->_type == ast_number_constant || + _right->_type == ast_variable || + _right->_type == ast_func_last)) + _test = predicate_constant; + else if (_right->_rettype != xpath_type_number && + _right->is_posinv_expr()) + _test = predicate_posinv; + } + + // Rewrite descendant-or-self::node()/child::foo with descendant::foo + // The former is a full form of //foo, the latter is much faster since it + // executes the node test immediately Do a similar kind of rewrite for + // self/descendant/descendant-or-self axes Note that we only rewrite + // positionally invariant steps (//foo[1] != /descendant::foo[1]) + if (_type == ast_step && + (_axis == axis_child || _axis == axis_self || + _axis == axis_descendant || _axis == axis_descendant_or_self) && + _left && _left->_type == ast_step && + _left->_axis == axis_descendant_or_self && + _left->_test == nodetest_type_node && !_left->_right && + is_posinv_step()) { + if (_axis == axis_child || _axis == axis_descendant) + _axis = axis_descendant; + else + _axis = axis_descendant_or_self; + + _left = _left->_left; + } + + // Use optimized lookup table implementation for translate() with constant + // arguments + if (_type == ast_func_translate && _right->_type == ast_string_constant && + _right->_next->_type == ast_string_constant) { + unsigned char *table = translate_table_generate( + alloc, _right->_data.string, _right->_next->_data.string); + + if (table) { + _type = ast_opt_translate_table; + _data.table = table; + } + } + + // Use optimized path for @attr = 'value' or @attr = $value + if (_type == ast_op_equal && _left->_type == ast_step && + _left->_axis == axis_attribute && _left->_test == nodetest_name && + !_left->_left && !_left->_right && + (_right->_type == ast_string_constant || + (_right->_type == ast_variable && + _right->_rettype == xpath_type_string))) { + _type = ast_opt_compare_attribute; + } + } + + bool is_posinv_expr() const { + switch (_type) { + case ast_func_position: + case ast_func_last: + return false; + + case ast_string_constant: + case ast_number_constant: + case ast_variable: + return true; + + case ast_step: + case ast_step_root: + return true; + + case ast_predicate: + case ast_filter: + return true; + + default: + if (_left && !_left->is_posinv_expr()) + return false; + + for (xpath_ast_node *n = _right; n; n = n->_next) + if (!n->is_posinv_expr()) + return false; + + return true; + } + } + + bool is_posinv_step() const { + assert(_type == ast_step); + + for (xpath_ast_node *n = _right; n; n = n->_next) { + assert(n->_type == ast_predicate); + + if (n->_test != predicate_posinv) + return false; + } + + return true; + } + + xpath_value_type rettype() const { + return static_cast(_rettype); + } +}; + +struct xpath_parser { + xpath_allocator *_alloc; + xpath_lexer _lexer; + + const char_t *_query; + xpath_variable_set *_variables; + + xpath_parse_result *_result; + + char_t _scratch[32]; + +#ifdef PUGIXML_NO_EXCEPTIONS + jmp_buf _error_handler; +#endif + + void throw_error(const char *message) { + _result->error = message; + _result->offset = _lexer.current_pos() - _query; + +#ifdef PUGIXML_NO_EXCEPTIONS + longjmp(_error_handler, 1); +#else + throw xpath_exception(*_result); +#endif + } + + void throw_error_oom() { +#ifdef PUGIXML_NO_EXCEPTIONS + throw_error("Out of memory"); +#else + throw std::bad_alloc(); +#endif + } + + void *alloc_node() { + void *result = _alloc->allocate_nothrow(sizeof(xpath_ast_node)); + + if (!result) + throw_error_oom(); + + return result; + } + + const char_t *alloc_string(const xpath_lexer_string &value) { + if (value.begin) { + size_t length = static_cast(value.end - value.begin); + + char_t *c = static_cast( + _alloc->allocate_nothrow((length + 1) * sizeof(char_t))); + if (!c) + throw_error_oom(); + assert(c); // workaround for clang static analysis + + memcpy(c, value.begin, length * sizeof(char_t)); + c[length] = 0; + + return c; + } else + return 0; + } + + xpath_ast_node *parse_function_helper(ast_type_t type0, ast_type_t type1, + size_t argc, xpath_ast_node *args[2]) { + assert(argc <= 1); + + if (argc == 1 && args[0]->rettype() != xpath_type_node_set) + throw_error("Function has to be applied to node set"); + + return new (alloc_node()) + xpath_ast_node(argc == 0 ? type0 : type1, xpath_type_string, args[0]); + } + + xpath_ast_node *parse_function(const xpath_lexer_string &name, size_t argc, + xpath_ast_node *args[2]) { + switch (name.begin[0]) { + case 'b': + if (name == PUGIXML_TEXT("boolean") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_boolean, xpath_type_boolean, args[0]); + + break; + + case 'c': + if (name == PUGIXML_TEXT("count") && argc == 1) { + if (args[0]->rettype() != xpath_type_node_set) + throw_error("Function has to be applied to node set"); + return new (alloc_node()) + xpath_ast_node(ast_func_count, xpath_type_number, args[0]); + } else if (name == PUGIXML_TEXT("contains") && argc == 2) + return new (alloc_node()) xpath_ast_node( + ast_func_contains, xpath_type_boolean, args[0], args[1]); + else if (name == PUGIXML_TEXT("concat") && argc >= 2) + return new (alloc_node()) xpath_ast_node( + ast_func_concat, xpath_type_string, args[0], args[1]); + else if (name == PUGIXML_TEXT("ceiling") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_ceiling, xpath_type_number, args[0]); + + break; + + case 'f': + if (name == PUGIXML_TEXT("false") && argc == 0) + return new (alloc_node()) + xpath_ast_node(ast_func_false, xpath_type_boolean); + else if (name == PUGIXML_TEXT("floor") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_floor, xpath_type_number, args[0]); + + break; + + case 'i': + if (name == PUGIXML_TEXT("id") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_id, xpath_type_node_set, args[0]); + + break; + + case 'l': + if (name == PUGIXML_TEXT("last") && argc == 0) + return new (alloc_node()) + xpath_ast_node(ast_func_last, xpath_type_number); + else if (name == PUGIXML_TEXT("lang") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_lang, xpath_type_boolean, args[0]); + else if (name == PUGIXML_TEXT("local-name") && argc <= 1) + return parse_function_helper(ast_func_local_name_0, + ast_func_local_name_1, argc, args); + + break; + + case 'n': + if (name == PUGIXML_TEXT("name") && argc <= 1) + return parse_function_helper(ast_func_name_0, ast_func_name_1, argc, + args); + else if (name == PUGIXML_TEXT("namespace-uri") && argc <= 1) + return parse_function_helper(ast_func_namespace_uri_0, + ast_func_namespace_uri_1, argc, args); + else if (name == PUGIXML_TEXT("normalize-space") && argc <= 1) + return new (alloc_node()) xpath_ast_node( + argc == 0 ? ast_func_normalize_space_0 : ast_func_normalize_space_1, + xpath_type_string, args[0], args[1]); + else if (name == PUGIXML_TEXT("not") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_not, xpath_type_boolean, args[0]); + else if (name == PUGIXML_TEXT("number") && argc <= 1) + return new (alloc_node()) + xpath_ast_node(argc == 0 ? ast_func_number_0 : ast_func_number_1, + xpath_type_number, args[0]); + + break; + + case 'p': + if (name == PUGIXML_TEXT("position") && argc == 0) + return new (alloc_node()) + xpath_ast_node(ast_func_position, xpath_type_number); + + break; + + case 'r': + if (name == PUGIXML_TEXT("round") && argc == 1) + return new (alloc_node()) + xpath_ast_node(ast_func_round, xpath_type_number, args[0]); + + break; + + case 's': + if (name == PUGIXML_TEXT("string") && argc <= 1) + return new (alloc_node()) + xpath_ast_node(argc == 0 ? ast_func_string_0 : ast_func_string_1, + xpath_type_string, args[0]); + else if (name == PUGIXML_TEXT("string-length") && argc <= 1) + return new (alloc_node()) xpath_ast_node( + argc == 0 ? ast_func_string_length_0 : ast_func_string_length_1, + xpath_type_number, args[0]); + else if (name == PUGIXML_TEXT("starts-with") && argc == 2) + return new (alloc_node()) xpath_ast_node( + ast_func_starts_with, xpath_type_boolean, args[0], args[1]); + else if (name == PUGIXML_TEXT("substring-before") && argc == 2) + return new (alloc_node()) xpath_ast_node( + ast_func_substring_before, xpath_type_string, args[0], args[1]); + else if (name == PUGIXML_TEXT("substring-after") && argc == 2) + return new (alloc_node()) xpath_ast_node( + ast_func_substring_after, xpath_type_string, args[0], args[1]); + else if (name == PUGIXML_TEXT("substring") && (argc == 2 || argc == 3)) + return new (alloc_node()) xpath_ast_node( + argc == 2 ? ast_func_substring_2 : ast_func_substring_3, + xpath_type_string, args[0], args[1]); + else if (name == PUGIXML_TEXT("sum") && argc == 1) { + if (args[0]->rettype() != xpath_type_node_set) + throw_error("Function has to be applied to node set"); + return new (alloc_node()) + xpath_ast_node(ast_func_sum, xpath_type_number, args[0]); + } + + break; + + case 't': + if (name == PUGIXML_TEXT("translate") && argc == 3) + return new (alloc_node()) xpath_ast_node( + ast_func_translate, xpath_type_string, args[0], args[1]); + else if (name == PUGIXML_TEXT("true") && argc == 0) + return new (alloc_node()) + xpath_ast_node(ast_func_true, xpath_type_boolean); + + break; + + default: + break; + } + + throw_error("Unrecognized function or wrong parameter count"); + + return 0; + } + + axis_t parse_axis_name(const xpath_lexer_string &name, bool &specified) { + specified = true; + + switch (name.begin[0]) { + case 'a': + if (name == PUGIXML_TEXT("ancestor")) + return axis_ancestor; + else if (name == PUGIXML_TEXT("ancestor-or-self")) + return axis_ancestor_or_self; + else if (name == PUGIXML_TEXT("attribute")) + return axis_attribute; + + break; + + case 'c': + if (name == PUGIXML_TEXT("child")) + return axis_child; + + break; + + case 'd': + if (name == PUGIXML_TEXT("descendant")) + return axis_descendant; + else if (name == PUGIXML_TEXT("descendant-or-self")) + return axis_descendant_or_self; + + break; + + case 'f': + if (name == PUGIXML_TEXT("following")) + return axis_following; + else if (name == PUGIXML_TEXT("following-sibling")) + return axis_following_sibling; + + break; + + case 'n': + if (name == PUGIXML_TEXT("namespace")) + return axis_namespace; + + break; + + case 'p': + if (name == PUGIXML_TEXT("parent")) + return axis_parent; + else if (name == PUGIXML_TEXT("preceding")) + return axis_preceding; + else if (name == PUGIXML_TEXT("preceding-sibling")) + return axis_preceding_sibling; + + break; + + case 's': + if (name == PUGIXML_TEXT("self")) + return axis_self; + + break; + + default: + break; + } + + specified = false; + return axis_child; + } + + nodetest_t parse_node_test_type(const xpath_lexer_string &name) { + switch (name.begin[0]) { + case 'c': + if (name == PUGIXML_TEXT("comment")) + return nodetest_type_comment; + + break; + + case 'n': + if (name == PUGIXML_TEXT("node")) + return nodetest_type_node; + + break; + + case 'p': + if (name == PUGIXML_TEXT("processing-instruction")) + return nodetest_type_pi; + + break; + + case 't': + if (name == PUGIXML_TEXT("text")) + return nodetest_type_text; + + break; + + default: + break; + } + + return nodetest_none; + } + + // PrimaryExpr ::= VariableReference | '(' Expr ')' | Literal | Number | + // FunctionCall + xpath_ast_node *parse_primary_expression() { + switch (_lexer.current()) { + case lex_var_ref: { + xpath_lexer_string name = _lexer.contents(); + + if (!_variables) + throw_error("Unknown variable: variable set is not provided"); + + xpath_variable *var = 0; + if (!get_variable_scratch(_scratch, _variables, name.begin, name.end, + &var)) + throw_error_oom(); + + if (!var) + throw_error( + "Unknown variable: variable set does not contain the given name"); + + _lexer.next(); + + return new (alloc_node()) xpath_ast_node(ast_variable, var->type(), var); + } + + case lex_open_brace: { + _lexer.next(); + + xpath_ast_node *n = parse_expression(); + + if (_lexer.current() != lex_close_brace) + throw_error("Unmatched braces"); + + _lexer.next(); + + return n; + } + + case lex_quoted_string: { + const char_t *value = alloc_string(_lexer.contents()); + + xpath_ast_node *n = new (alloc_node()) + xpath_ast_node(ast_string_constant, xpath_type_string, value); + _lexer.next(); + + return n; + } + + case lex_number: { + double value = 0; + + if (!convert_string_to_number_scratch(_scratch, _lexer.contents().begin, + _lexer.contents().end, &value)) + throw_error_oom(); + + xpath_ast_node *n = new (alloc_node()) + xpath_ast_node(ast_number_constant, xpath_type_number, value); + _lexer.next(); + + return n; + } + + case lex_string: { + xpath_ast_node *args[2] = {0}; + size_t argc = 0; + + xpath_lexer_string function = _lexer.contents(); + _lexer.next(); + + xpath_ast_node *last_arg = 0; + + if (_lexer.current() != lex_open_brace) + throw_error("Unrecognized function call"); + _lexer.next(); + + if (_lexer.current() != lex_close_brace) + args[argc++] = parse_expression(); + + while (_lexer.current() != lex_close_brace) { + if (_lexer.current() != lex_comma) + throw_error("No comma between function arguments"); + _lexer.next(); + + xpath_ast_node *n = parse_expression(); + + if (argc < 2) + args[argc] = n; + else + last_arg->set_next(n); + + argc++; + last_arg = n; + } + + _lexer.next(); + + return parse_function(function, argc, args); + } + + default: + throw_error("Unrecognizable primary expression"); + + return 0; + } + } + + // FilterExpr ::= PrimaryExpr | FilterExpr Predicate + // Predicate ::= '[' PredicateExpr ']' + // PredicateExpr ::= Expr + xpath_ast_node *parse_filter_expression() { + xpath_ast_node *n = parse_primary_expression(); + + while (_lexer.current() == lex_open_square_brace) { + _lexer.next(); + + xpath_ast_node *expr = parse_expression(); + + if (n->rettype() != xpath_type_node_set) + throw_error("Predicate has to be applied to node set"); + + n = new (alloc_node()) + xpath_ast_node(ast_filter, n, expr, predicate_default); + + if (_lexer.current() != lex_close_square_brace) + throw_error("Unmatched square brace"); + + _lexer.next(); + } + + return n; + } + + // Step ::= AxisSpecifier NodeTest Predicate* | AbbreviatedStep + // AxisSpecifier ::= AxisName '::' | '@'? + // NodeTest ::= NameTest | NodeType '(' ')' | 'processing-instruction' '(' + // Literal ')' NameTest ::= '*' | NCName ':' '*' | QName AbbreviatedStep ::= + // '.' | '..' + xpath_ast_node *parse_step(xpath_ast_node *set) { + if (set && set->rettype() != xpath_type_node_set) + throw_error("Step has to be applied to node set"); + + bool axis_specified = false; + axis_t axis = axis_child; // implied child axis + + if (_lexer.current() == lex_axis_attribute) { + axis = axis_attribute; + axis_specified = true; + + _lexer.next(); + } else if (_lexer.current() == lex_dot) { + _lexer.next(); + + return new (alloc_node()) + xpath_ast_node(ast_step, set, axis_self, nodetest_type_node, 0); + } else if (_lexer.current() == lex_double_dot) { + _lexer.next(); + + return new (alloc_node()) + xpath_ast_node(ast_step, set, axis_parent, nodetest_type_node, 0); + } + + nodetest_t nt_type = nodetest_none; + xpath_lexer_string nt_name; + + if (_lexer.current() == lex_string) { + // node name test + nt_name = _lexer.contents(); + _lexer.next(); + + // was it an axis name? + if (_lexer.current() == lex_double_colon) { + // parse axis name + if (axis_specified) + throw_error("Two axis specifiers in one step"); + + axis = parse_axis_name(nt_name, axis_specified); + + if (!axis_specified) + throw_error("Unknown axis"); + + // read actual node test + _lexer.next(); + + if (_lexer.current() == lex_multiply) { + nt_type = nodetest_all; + nt_name = xpath_lexer_string(); + _lexer.next(); + } else if (_lexer.current() == lex_string) { + nt_name = _lexer.contents(); + _lexer.next(); + } else + throw_error("Unrecognized node test"); + } + + if (nt_type == nodetest_none) { + // node type test or processing-instruction + if (_lexer.current() == lex_open_brace) { + _lexer.next(); + + if (_lexer.current() == lex_close_brace) { + _lexer.next(); + + nt_type = parse_node_test_type(nt_name); + + if (nt_type == nodetest_none) + throw_error("Unrecognized node type"); + + nt_name = xpath_lexer_string(); + } else if (nt_name == PUGIXML_TEXT("processing-instruction")) { + if (_lexer.current() != lex_quoted_string) + throw_error("Only literals are allowed as arguments to " + "processing-instruction()"); + + nt_type = nodetest_pi; + nt_name = _lexer.contents(); + _lexer.next(); + + if (_lexer.current() != lex_close_brace) + throw_error("Unmatched brace near processing-instruction()"); + _lexer.next(); + } else + throw_error("Unmatched brace near node type test"); + + } + // QName or NCName:* + else { + if (nt_name.end - nt_name.begin > 2 && nt_name.end[-2] == ':' && + nt_name.end[-1] == '*') // NCName:* + { + nt_name.end--; // erase * + + nt_type = nodetest_all_in_namespace; + } else + nt_type = nodetest_name; + } + } + } else if (_lexer.current() == lex_multiply) { + nt_type = nodetest_all; + _lexer.next(); + } else + throw_error("Unrecognized node test"); + + xpath_ast_node *n = new (alloc_node()) + xpath_ast_node(ast_step, set, axis, nt_type, alloc_string(nt_name)); + + xpath_ast_node *last = 0; + + while (_lexer.current() == lex_open_square_brace) { + _lexer.next(); + + xpath_ast_node *expr = parse_expression(); + + xpath_ast_node *pred = new (alloc_node()) + xpath_ast_node(ast_predicate, 0, expr, predicate_default); + + if (_lexer.current() != lex_close_square_brace) + throw_error("Unmatched square brace"); + _lexer.next(); + + if (last) + last->set_next(pred); + else + n->set_right(pred); + + last = pred; + } + + return n; + } + + // RelativeLocationPath ::= Step | RelativeLocationPath '/' Step | + // RelativeLocationPath '//' Step + xpath_ast_node *parse_relative_location_path(xpath_ast_node *set) { + xpath_ast_node *n = parse_step(set); + + while (_lexer.current() == lex_slash || + _lexer.current() == lex_double_slash) { + lexeme_t l = _lexer.current(); + _lexer.next(); + + if (l == lex_double_slash) + n = new (alloc_node()) xpath_ast_node( + ast_step, n, axis_descendant_or_self, nodetest_type_node, 0); + + n = parse_step(n); + } + + return n; + } + + // LocationPath ::= RelativeLocationPath | AbsoluteLocationPath + // AbsoluteLocationPath ::= '/' RelativeLocationPath? | '//' + // RelativeLocationPath + xpath_ast_node *parse_location_path() { + if (_lexer.current() == lex_slash) { + _lexer.next(); + + xpath_ast_node *n = + new (alloc_node()) xpath_ast_node(ast_step_root, xpath_type_node_set); + + // relative location path can start from axis_attribute, dot, double_dot, + // multiply and string lexemes; any other lexeme means standalone root + // path + lexeme_t l = _lexer.current(); + + if (l == lex_string || l == lex_axis_attribute || l == lex_dot || + l == lex_double_dot || l == lex_multiply) + return parse_relative_location_path(n); + else + return n; + } else if (_lexer.current() == lex_double_slash) { + _lexer.next(); + + xpath_ast_node *n = + new (alloc_node()) xpath_ast_node(ast_step_root, xpath_type_node_set); + n = new (alloc_node()) xpath_ast_node( + ast_step, n, axis_descendant_or_self, nodetest_type_node, 0); + + return parse_relative_location_path(n); + } + + // else clause moved outside of if because of bogus warning 'control may + // reach end of non-void function being inlined' in gcc 4.0.1 + return parse_relative_location_path(0); + } + + // PathExpr ::= LocationPath + // | FilterExpr + // | FilterExpr '/' RelativeLocationPath + // | FilterExpr '//' RelativeLocationPath + // UnionExpr ::= PathExpr | UnionExpr '|' PathExpr + // UnaryExpr ::= UnionExpr | '-' UnaryExpr + xpath_ast_node *parse_path_or_unary_expression() { + // Clarification. + // PathExpr begins with either LocationPath or FilterExpr. + // FilterExpr begins with PrimaryExpr + // PrimaryExpr begins with '$' in case of it being a variable reference, + // '(' in case of it being an expression, string literal, number constant or + // function call. + + if (_lexer.current() == lex_var_ref || _lexer.current() == lex_open_brace || + _lexer.current() == lex_quoted_string || + _lexer.current() == lex_number || _lexer.current() == lex_string) { + if (_lexer.current() == lex_string) { + // This is either a function call, or not - if not, we shall proceed + // with location path + const char_t *state = _lexer.state(); + + while (PUGI__IS_CHARTYPE(*state, ct_space)) + ++state; + + if (*state != '(') + return parse_location_path(); + + // This looks like a function call; however this still can be a + // node-test. Check it. + if (parse_node_test_type(_lexer.contents()) != nodetest_none) + return parse_location_path(); + } + + xpath_ast_node *n = parse_filter_expression(); + + if (_lexer.current() == lex_slash || + _lexer.current() == lex_double_slash) { + lexeme_t l = _lexer.current(); + _lexer.next(); + + if (l == lex_double_slash) { + if (n->rettype() != xpath_type_node_set) + throw_error("Step has to be applied to node set"); + + n = new (alloc_node()) xpath_ast_node( + ast_step, n, axis_descendant_or_self, nodetest_type_node, 0); + } + + // select from location path + return parse_relative_location_path(n); + } + + return n; + } else if (_lexer.current() == lex_minus) { + _lexer.next(); + + // precedence 7+ - only parses union expressions + xpath_ast_node *expr = + parse_expression_rec(parse_path_or_unary_expression(), 7); + + return new (alloc_node()) + xpath_ast_node(ast_op_negate, xpath_type_number, expr); + } else + return parse_location_path(); + } + + struct binary_op_t { + ast_type_t asttype; + xpath_value_type rettype; + int precedence; + + binary_op_t() + : asttype(ast_unknown), rettype(xpath_type_none), precedence(0) {} + + binary_op_t(ast_type_t asttype_, xpath_value_type rettype_, int precedence_) + : asttype(asttype_), rettype(rettype_), precedence(precedence_) {} + + static binary_op_t parse(xpath_lexer &lexer) { + switch (lexer.current()) { + case lex_string: + if (lexer.contents() == PUGIXML_TEXT("or")) + return binary_op_t(ast_op_or, xpath_type_boolean, 1); + else if (lexer.contents() == PUGIXML_TEXT("and")) + return binary_op_t(ast_op_and, xpath_type_boolean, 2); + else if (lexer.contents() == PUGIXML_TEXT("div")) + return binary_op_t(ast_op_divide, xpath_type_number, 6); + else if (lexer.contents() == PUGIXML_TEXT("mod")) + return binary_op_t(ast_op_mod, xpath_type_number, 6); + else + return binary_op_t(); + + case lex_equal: + return binary_op_t(ast_op_equal, xpath_type_boolean, 3); + + case lex_not_equal: + return binary_op_t(ast_op_not_equal, xpath_type_boolean, 3); + + case lex_less: + return binary_op_t(ast_op_less, xpath_type_boolean, 4); + + case lex_greater: + return binary_op_t(ast_op_greater, xpath_type_boolean, 4); + + case lex_less_or_equal: + return binary_op_t(ast_op_less_or_equal, xpath_type_boolean, 4); + + case lex_greater_or_equal: + return binary_op_t(ast_op_greater_or_equal, xpath_type_boolean, 4); + + case lex_plus: + return binary_op_t(ast_op_add, xpath_type_number, 5); + + case lex_minus: + return binary_op_t(ast_op_subtract, xpath_type_number, 5); + + case lex_multiply: + return binary_op_t(ast_op_multiply, xpath_type_number, 6); + + case lex_union: + return binary_op_t(ast_op_union, xpath_type_node_set, 7); + + default: + return binary_op_t(); + } + } + }; + + xpath_ast_node *parse_expression_rec(xpath_ast_node *lhs, int limit) { + binary_op_t op = binary_op_t::parse(_lexer); + + while (op.asttype != ast_unknown && op.precedence >= limit) { + _lexer.next(); + + xpath_ast_node *rhs = parse_path_or_unary_expression(); + + binary_op_t nextop = binary_op_t::parse(_lexer); + + while (nextop.asttype != ast_unknown && + nextop.precedence > op.precedence) { + rhs = parse_expression_rec(rhs, nextop.precedence); + + nextop = binary_op_t::parse(_lexer); + } + + if (op.asttype == ast_op_union && + (lhs->rettype() != xpath_type_node_set || + rhs->rettype() != xpath_type_node_set)) + throw_error("Union operator has to be applied to node sets"); + + lhs = new (alloc_node()) xpath_ast_node(op.asttype, op.rettype, lhs, rhs); + + op = binary_op_t::parse(_lexer); + } + + return lhs; + } + + // Expr ::= OrExpr + // OrExpr ::= AndExpr | OrExpr 'or' AndExpr + // AndExpr ::= EqualityExpr | AndExpr 'and' EqualityExpr + // EqualityExpr ::= RelationalExpr + // | EqualityExpr '=' RelationalExpr + // | EqualityExpr '!=' RelationalExpr + // RelationalExpr ::= AdditiveExpr + // | RelationalExpr '<' AdditiveExpr + // | RelationalExpr '>' AdditiveExpr + // | RelationalExpr '<=' AdditiveExpr + // | RelationalExpr '>=' AdditiveExpr + // AdditiveExpr ::= MultiplicativeExpr + // | AdditiveExpr '+' MultiplicativeExpr + // | AdditiveExpr '-' MultiplicativeExpr + // MultiplicativeExpr ::= UnaryExpr + // | MultiplicativeExpr '*' + // UnaryExpr | MultiplicativeExpr 'div' + // UnaryExpr | MultiplicativeExpr 'mod' UnaryExpr + xpath_ast_node *parse_expression() { + return parse_expression_rec(parse_path_or_unary_expression(), 0); + } + + xpath_parser(const char_t *query, xpath_variable_set *variables, + xpath_allocator *alloc, xpath_parse_result *result) + : _alloc(alloc), _lexer(query), _query(query), _variables(variables), + _result(result) {} + + xpath_ast_node *parse() { + xpath_ast_node *result = parse_expression(); + + if (_lexer.current() != lex_eof) { + // there are still unparsed tokens left, error + throw_error("Incorrect query"); + } + + return result; + } + + static xpath_ast_node *parse(const char_t *query, + xpath_variable_set *variables, + xpath_allocator *alloc, + xpath_parse_result *result) { + xpath_parser parser(query, variables, alloc, result); + +#ifdef PUGIXML_NO_EXCEPTIONS + int error = setjmp(parser._error_handler); + + return (error == 0) ? parser.parse() : 0; +#else + return parser.parse(); +#endif + } +}; + +struct xpath_query_impl { + static xpath_query_impl *create() { + void *memory = xml_memory::allocate(sizeof(xpath_query_impl)); + if (!memory) + return 0; + + return new (memory) xpath_query_impl(); + } + + static void destroy(xpath_query_impl *impl) { + // free all allocated pages + impl->alloc.release(); + + // free allocator memory (with the first page) + xml_memory::deallocate(impl); + } + + xpath_query_impl() : root(0), alloc(&block) { + block.next = 0; + block.capacity = sizeof(block.data); + } + + xpath_ast_node *root; + xpath_allocator alloc; + xpath_memory_block block; +}; + +PUGI__FN xpath_string evaluate_string_impl(xpath_query_impl *impl, + const xpath_node &n, + xpath_stack_data &sd) { + if (!impl) + return xpath_string(); + +#ifdef PUGIXML_NO_EXCEPTIONS + if (setjmp(sd.error_handler)) + return xpath_string(); +#endif + + xpath_context c(n, 1, 1); + + return impl->root->eval_string(c, sd.stack); +} + +PUGI__FN impl::xpath_ast_node * +evaluate_node_set_prepare(xpath_query_impl *impl) { + if (!impl) + return 0; + + if (impl->root->rettype() != xpath_type_node_set) { +#ifdef PUGIXML_NO_EXCEPTIONS + return 0; +#else + xpath_parse_result res; + res.error = "Expression does not evaluate to node set"; + + throw xpath_exception(res); +#endif + } + + return impl->root; +} +PUGI__NS_END + +namespace pugi { +#ifndef PUGIXML_NO_EXCEPTIONS +PUGI__FN xpath_exception::xpath_exception(const xpath_parse_result &result_) + : _result(result_) { + assert(_result.error); +} + +PUGI__FN const char *xpath_exception::what() const throw() { + return _result.error; +} + +PUGI__FN const xpath_parse_result &xpath_exception::result() const { + return _result; +} +#endif + +PUGI__FN xpath_node::xpath_node() {} + +PUGI__FN xpath_node::xpath_node(const xml_node &node_) : _node(node_) {} + +PUGI__FN xpath_node::xpath_node(const xml_attribute &attribute_, + const xml_node &parent_) + : _node(attribute_ ? parent_ : xml_node()), _attribute(attribute_) {} + +PUGI__FN xml_node xpath_node::node() const { + return _attribute ? xml_node() : _node; +} + +PUGI__FN xml_attribute xpath_node::attribute() const { return _attribute; } + +PUGI__FN xml_node xpath_node::parent() const { + return _attribute ? _node : _node.parent(); +} + +PUGI__FN static void unspecified_bool_xpath_node(xpath_node ***) {} + +PUGI__FN xpath_node::operator xpath_node::unspecified_bool_type() const { + return (_node || _attribute) ? unspecified_bool_xpath_node : 0; +} + +PUGI__FN bool xpath_node::operator!() const { return !(_node || _attribute); } + +PUGI__FN bool xpath_node::operator==(const xpath_node &n) const { + return _node == n._node && _attribute == n._attribute; +} + +PUGI__FN bool xpath_node::operator!=(const xpath_node &n) const { + return _node != n._node || _attribute != n._attribute; +} + +#ifdef __BORLANDC__ +PUGI__FN bool operator&&(const xpath_node &lhs, bool rhs) { + return (bool)lhs && rhs; +} + +PUGI__FN bool operator||(const xpath_node &lhs, bool rhs) { + return (bool)lhs || rhs; +} +#endif + +PUGI__FN void xpath_node_set::_assign(const_iterator begin_, + const_iterator end_, type_t type_) { + assert(begin_ <= end_); + + size_t size_ = static_cast(end_ - begin_); + + if (size_ <= 1) { + // deallocate old buffer + if (_begin != &_storage) + impl::xml_memory::deallocate(_begin); + + // use internal buffer + if (begin_ != end_) + _storage = *begin_; + + _begin = &_storage; + _end = &_storage + size_; + _type = type_; + } else { + // make heap copy + xpath_node *storage = static_cast( + impl::xml_memory::allocate(size_ * sizeof(xpath_node))); + + if (!storage) { +#ifdef PUGIXML_NO_EXCEPTIONS + return; +#else + throw std::bad_alloc(); +#endif + } + + memcpy(storage, begin_, size_ * sizeof(xpath_node)); + + // deallocate old buffer + if (_begin != &_storage) + impl::xml_memory::deallocate(_begin); + + // finalize + _begin = storage; + _end = storage + size_; + _type = type_; + } +} + +#if __cplusplus >= 201103 +PUGI__FN void xpath_node_set::_move(xpath_node_set &rhs) { + _type = rhs._type; + _storage = rhs._storage; + _begin = (rhs._begin == &rhs._storage) ? &_storage : rhs._begin; + _end = _begin + (rhs._end - rhs._begin); + + rhs._type = type_unsorted; + rhs._begin = &rhs._storage; + rhs._end = rhs._begin; +} +#endif + +PUGI__FN xpath_node_set::xpath_node_set() + : _type(type_unsorted), _begin(&_storage), _end(&_storage) {} + +PUGI__FN xpath_node_set::xpath_node_set(const_iterator begin_, + const_iterator end_, type_t type_) + : _type(type_unsorted), _begin(&_storage), _end(&_storage) { + _assign(begin_, end_, type_); +} + +PUGI__FN xpath_node_set::~xpath_node_set() { + if (_begin != &_storage) + impl::xml_memory::deallocate(_begin); +} + +PUGI__FN xpath_node_set::xpath_node_set(const xpath_node_set &ns) + : _type(type_unsorted), _begin(&_storage), _end(&_storage) { + _assign(ns._begin, ns._end, ns._type); +} + +PUGI__FN xpath_node_set &xpath_node_set::operator=(const xpath_node_set &ns) { + if (this == &ns) + return *this; + + _assign(ns._begin, ns._end, ns._type); + + return *this; +} + +#if __cplusplus >= 201103 +PUGI__FN xpath_node_set::xpath_node_set(xpath_node_set &&rhs) + : _type(type_unsorted), _begin(&_storage), _end(&_storage) { + _move(rhs); +} + +PUGI__FN xpath_node_set &xpath_node_set::operator=(xpath_node_set &&rhs) { + if (this == &rhs) + return *this; + + if (_begin != &_storage) + impl::xml_memory::deallocate(_begin); + + _move(rhs); + + return *this; +} +#endif + +PUGI__FN xpath_node_set::type_t xpath_node_set::type() const { return _type; } + +PUGI__FN size_t xpath_node_set::size() const { return _end - _begin; } + +PUGI__FN bool xpath_node_set::empty() const { return _begin == _end; } + +PUGI__FN const xpath_node &xpath_node_set::operator[](size_t index) const { + assert(index < size()); + return _begin[index]; +} + +PUGI__FN xpath_node_set::const_iterator xpath_node_set::begin() const { + return _begin; +} + +PUGI__FN xpath_node_set::const_iterator xpath_node_set::end() const { + return _end; +} + +PUGI__FN void xpath_node_set::sort(bool reverse) { + _type = impl::xpath_sort(_begin, _end, _type, reverse); +} + +PUGI__FN xpath_node xpath_node_set::first() const { + return impl::xpath_first(_begin, _end, _type); +} + +PUGI__FN xpath_parse_result::xpath_parse_result() + : error("Internal error"), offset(0) {} + +PUGI__FN xpath_parse_result::operator bool() const { return error == 0; } + +PUGI__FN const char *xpath_parse_result::description() const { + return error ? error : "No error"; +} + +PUGI__FN xpath_variable::xpath_variable(xpath_value_type type_) + : _type(type_), _next(0) {} + +PUGI__FN const char_t *xpath_variable::name() const { + switch (_type) { + case xpath_type_node_set: + return static_cast(this)->name; + + case xpath_type_number: + return static_cast(this)->name; + + case xpath_type_string: + return static_cast(this)->name; + + case xpath_type_boolean: + return static_cast(this)->name; + + default: + assert(!"Invalid variable type"); + return 0; + } +} + +PUGI__FN xpath_value_type xpath_variable::type() const { return _type; } + +PUGI__FN bool xpath_variable::get_boolean() const { + return (_type == xpath_type_boolean) + ? static_cast(this)->value + : false; +} + +PUGI__FN double xpath_variable::get_number() const { + return (_type == xpath_type_number) + ? static_cast(this)->value + : impl::gen_nan(); +} + +PUGI__FN const char_t *xpath_variable::get_string() const { + const char_t *value = + (_type == xpath_type_string) + ? static_cast(this)->value + : 0; + return value ? value : PUGIXML_TEXT(""); +} + +PUGI__FN const xpath_node_set &xpath_variable::get_node_set() const { + return (_type == xpath_type_node_set) + ? static_cast(this)->value + : impl::dummy_node_set; +} + +PUGI__FN bool xpath_variable::set(bool value) { + if (_type != xpath_type_boolean) + return false; + + static_cast(this)->value = value; + return true; +} + +PUGI__FN bool xpath_variable::set(double value) { + if (_type != xpath_type_number) + return false; + + static_cast(this)->value = value; + return true; +} + +PUGI__FN bool xpath_variable::set(const char_t *value) { + if (_type != xpath_type_string) + return false; + + impl::xpath_variable_string *var = + static_cast(this); + + // duplicate string + size_t size = (impl::strlength(value) + 1) * sizeof(char_t); + + char_t *copy = static_cast(impl::xml_memory::allocate(size)); + if (!copy) + return false; + + memcpy(copy, value, size); + + // replace old string + if (var->value) + impl::xml_memory::deallocate(var->value); + var->value = copy; + + return true; +} + +PUGI__FN bool xpath_variable::set(const xpath_node_set &value) { + if (_type != xpath_type_node_set) + return false; + + static_cast(this)->value = value; + return true; +} + +PUGI__FN xpath_variable_set::xpath_variable_set() { + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) + _data[i] = 0; +} + +PUGI__FN xpath_variable_set::~xpath_variable_set() { + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) + _destroy(_data[i]); +} + +PUGI__FN xpath_variable_set::xpath_variable_set(const xpath_variable_set &rhs) { + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) + _data[i] = 0; + + _assign(rhs); +} + +PUGI__FN xpath_variable_set & +xpath_variable_set::operator=(const xpath_variable_set &rhs) { + if (this == &rhs) + return *this; + + _assign(rhs); + + return *this; +} + +#if __cplusplus >= 201103 +PUGI__FN xpath_variable_set::xpath_variable_set(xpath_variable_set &&rhs) { + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) { + _data[i] = rhs._data[i]; + rhs._data[i] = 0; + } +} + +PUGI__FN xpath_variable_set & +xpath_variable_set::operator=(xpath_variable_set &&rhs) { + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) { + _destroy(_data[i]); + + _data[i] = rhs._data[i]; + rhs._data[i] = 0; + } + + return *this; +} +#endif + +PUGI__FN void xpath_variable_set::_assign(const xpath_variable_set &rhs) { + xpath_variable_set temp; + + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) + if (rhs._data[i] && !_clone(rhs._data[i], &temp._data[i])) + return; + + _swap(temp); +} + +PUGI__FN void xpath_variable_set::_swap(xpath_variable_set &rhs) { + for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) { + xpath_variable *chain = _data[i]; + + _data[i] = rhs._data[i]; + rhs._data[i] = chain; + } +} + +PUGI__FN xpath_variable *xpath_variable_set::_find(const char_t *name) const { + const size_t hash_size = sizeof(_data) / sizeof(_data[0]); + size_t hash = impl::hash_string(name) % hash_size; + + // look for existing variable + for (xpath_variable *var = _data[hash]; var; var = var->_next) + if (impl::strequal(var->name(), name)) + return var; + + return 0; +} + +PUGI__FN bool xpath_variable_set::_clone(xpath_variable *var, + xpath_variable **out_result) { + xpath_variable *last = 0; + + while (var) { + // allocate storage for new variable + xpath_variable *nvar = impl::new_xpath_variable(var->_type, var->name()); + if (!nvar) + return false; + + // link the variable to the result immediately to handle failures gracefully + if (last) + last->_next = nvar; + else + *out_result = nvar; + + last = nvar; + + // copy the value; this can fail due to out-of-memory conditions + if (!impl::copy_xpath_variable(nvar, var)) + return false; + + var = var->_next; + } + + return true; +} + +PUGI__FN void xpath_variable_set::_destroy(xpath_variable *var) { + while (var) { + xpath_variable *next = var->_next; + + impl::delete_xpath_variable(var->_type, var); + + var = next; + } +} + +PUGI__FN xpath_variable *xpath_variable_set::add(const char_t *name, + xpath_value_type type) { + const size_t hash_size = sizeof(_data) / sizeof(_data[0]); + size_t hash = impl::hash_string(name) % hash_size; + + // look for existing variable + for (xpath_variable *var = _data[hash]; var; var = var->_next) + if (impl::strequal(var->name(), name)) + return var->type() == type ? var : 0; + + // add new variable + xpath_variable *result = impl::new_xpath_variable(type, name); + + if (result) { + result->_next = _data[hash]; + + _data[hash] = result; + } + + return result; +} + +PUGI__FN bool xpath_variable_set::set(const char_t *name, bool value) { + xpath_variable *var = add(name, xpath_type_boolean); + return var ? var->set(value) : false; +} + +PUGI__FN bool xpath_variable_set::set(const char_t *name, double value) { + xpath_variable *var = add(name, xpath_type_number); + return var ? var->set(value) : false; +} + +PUGI__FN bool xpath_variable_set::set(const char_t *name, const char_t *value) { + xpath_variable *var = add(name, xpath_type_string); + return var ? var->set(value) : false; +} + +PUGI__FN bool xpath_variable_set::set(const char_t *name, + const xpath_node_set &value) { + xpath_variable *var = add(name, xpath_type_node_set); + return var ? var->set(value) : false; +} + +PUGI__FN xpath_variable *xpath_variable_set::get(const char_t *name) { + return _find(name); +} + +PUGI__FN const xpath_variable * +xpath_variable_set::get(const char_t *name) const { + return _find(name); +} + +PUGI__FN xpath_query::xpath_query(const char_t *query, + xpath_variable_set *variables) + : _impl(0) { + impl::xpath_query_impl *qimpl = impl::xpath_query_impl::create(); + + if (!qimpl) { +#ifdef PUGIXML_NO_EXCEPTIONS + _result.error = "Out of memory"; +#else + throw std::bad_alloc(); +#endif + } else { + using impl::auto_deleter; // MSVC7 workaround + auto_deleter impl(qimpl, + impl::xpath_query_impl::destroy); + + qimpl->root = + impl::xpath_parser::parse(query, variables, &qimpl->alloc, &_result); + + if (qimpl->root) { + qimpl->root->optimize(&qimpl->alloc); + + _impl = impl.release(); + _result.error = 0; + } + } +} + +PUGI__FN xpath_query::xpath_query() : _impl(0) {} + +PUGI__FN xpath_query::~xpath_query() { + if (_impl) + impl::xpath_query_impl::destroy( + static_cast(_impl)); +} + +#if __cplusplus >= 201103 +PUGI__FN xpath_query::xpath_query(xpath_query &&rhs) { + _impl = rhs._impl; + _result = rhs._result; + rhs._impl = 0; + rhs._result = xpath_parse_result(); +} + +PUGI__FN xpath_query &xpath_query::operator=(xpath_query &&rhs) { + if (this == &rhs) + return *this; + + if (_impl) + impl::xpath_query_impl::destroy( + static_cast(_impl)); + + _impl = rhs._impl; + _result = rhs._result; + rhs._impl = 0; + rhs._result = xpath_parse_result(); + + return *this; +} +#endif + +PUGI__FN xpath_value_type xpath_query::return_type() const { + if (!_impl) + return xpath_type_none; + + return static_cast(_impl)->root->rettype(); +} + +PUGI__FN bool xpath_query::evaluate_boolean(const xpath_node &n) const { + if (!_impl) + return false; + + impl::xpath_context c(n, 1, 1); + impl::xpath_stack_data sd; + +#ifdef PUGIXML_NO_EXCEPTIONS + if (setjmp(sd.error_handler)) + return false; +#endif + + return static_cast(_impl)->root->eval_boolean( + c, sd.stack); +} + +PUGI__FN double xpath_query::evaluate_number(const xpath_node &n) const { + if (!_impl) + return impl::gen_nan(); + + impl::xpath_context c(n, 1, 1); + impl::xpath_stack_data sd; + +#ifdef PUGIXML_NO_EXCEPTIONS + if (setjmp(sd.error_handler)) + return impl::gen_nan(); +#endif + + return static_cast(_impl)->root->eval_number( + c, sd.stack); +} + +#ifndef PUGIXML_NO_STL +PUGI__FN string_t xpath_query::evaluate_string(const xpath_node &n) const { + impl::xpath_stack_data sd; + + impl::xpath_string r = impl::evaluate_string_impl( + static_cast(_impl), n, sd); + + return string_t(r.c_str(), r.length()); +} +#endif + +PUGI__FN size_t xpath_query::evaluate_string(char_t *buffer, size_t capacity, + const xpath_node &n) const { + impl::xpath_stack_data sd; + + impl::xpath_string r = impl::evaluate_string_impl( + static_cast(_impl), n, sd); + + size_t full_size = r.length() + 1; + + if (capacity > 0) { + size_t size = (full_size < capacity) ? full_size : capacity; + assert(size > 0); + + memcpy(buffer, r.c_str(), (size - 1) * sizeof(char_t)); + buffer[size - 1] = 0; + } + + return full_size; +} + +PUGI__FN xpath_node_set +xpath_query::evaluate_node_set(const xpath_node &n) const { + impl::xpath_ast_node *root = impl::evaluate_node_set_prepare( + static_cast(_impl)); + if (!root) + return xpath_node_set(); + + impl::xpath_context c(n, 1, 1); + impl::xpath_stack_data sd; + +#ifdef PUGIXML_NO_EXCEPTIONS + if (setjmp(sd.error_handler)) + return xpath_node_set(); +#endif + + impl::xpath_node_set_raw r = + root->eval_node_set(c, sd.stack, impl::nodeset_eval_all); + + return xpath_node_set(r.begin(), r.end(), r.type()); +} + +PUGI__FN xpath_node xpath_query::evaluate_node(const xpath_node &n) const { + impl::xpath_ast_node *root = impl::evaluate_node_set_prepare( + static_cast(_impl)); + if (!root) + return xpath_node(); + + impl::xpath_context c(n, 1, 1); + impl::xpath_stack_data sd; + +#ifdef PUGIXML_NO_EXCEPTIONS + if (setjmp(sd.error_handler)) + return xpath_node(); +#endif + + impl::xpath_node_set_raw r = + root->eval_node_set(c, sd.stack, impl::nodeset_eval_first); + + return r.first(); +} + +PUGI__FN const xpath_parse_result &xpath_query::result() const { + return _result; +} + +PUGI__FN static void unspecified_bool_xpath_query(xpath_query ***) {} + +PUGI__FN xpath_query::operator xpath_query::unspecified_bool_type() const { + return _impl ? unspecified_bool_xpath_query : 0; +} + +PUGI__FN bool xpath_query::operator!() const { return !_impl; } + +PUGI__FN xpath_node xml_node::select_node(const char_t *query, + xpath_variable_set *variables) const { + xpath_query q(query, variables); + return select_node(q); +} + +PUGI__FN xpath_node xml_node::select_node(const xpath_query &query) const { + return query.evaluate_node(*this); +} + +PUGI__FN xpath_node_set xml_node::select_nodes( + const char_t *query, xpath_variable_set *variables) const { + xpath_query q(query, variables); + return select_nodes(q); +} + +PUGI__FN xpath_node_set xml_node::select_nodes(const xpath_query &query) const { + return query.evaluate_node_set(*this); +} + +PUGI__FN xpath_node xml_node::select_single_node( + const char_t *query, xpath_variable_set *variables) const { + xpath_query q(query, variables); + return select_single_node(q); +} + +PUGI__FN xpath_node +xml_node::select_single_node(const xpath_query &query) const { + return query.evaluate_node(*this); +} +} // namespace pugi + +#endif + +#ifdef __BORLANDC__ +#pragma option pop +#endif + +// Intel C++ does not properly keep warning state for function templates, +// so popping warning state at the end of translation unit leads to warnings in +// the middle. +#if defined(_MSC_VER) && !defined(__INTEL_COMPILER) +#pragma warning(pop) +#endif + +// Undefine all local macros (makes sure we're not leaking macros in header-only +// mode) +#undef PUGI__NO_INLINE +#undef PUGI__UNLIKELY +#undef PUGI__STATIC_ASSERT +#undef PUGI__DMC_VOLATILE +#undef PUGI__MSVC_CRT_VERSION +#undef PUGI__NS_BEGIN +#undef PUGI__NS_END +#undef PUGI__FN +#undef PUGI__FN_NO_INLINE +#undef PUGI__GETPAGE_IMPL +#undef PUGI__GETPAGE +#undef PUGI__NODETYPE +#undef PUGI__IS_CHARTYPE_IMPL +#undef PUGI__IS_CHARTYPE +#undef PUGI__IS_CHARTYPEX +#undef PUGI__ENDSWITH +#undef PUGI__SKIPWS +#undef PUGI__OPTSET +#undef PUGI__PUSHNODE +#undef PUGI__POPNODE +#undef PUGI__SCANFOR +#undef PUGI__SCANWHILE +#undef PUGI__SCANWHILE_UNROLL +#undef PUGI__ENDSEG +#undef PUGI__THROW_ERROR +#undef PUGI__CHECK_ERROR + +#endif + +/** + * Copyright (c) 2006-2015 Arseny Kapoulkine + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ diff --git a/techlibs/rapidflex/src/pugixml.hpp b/techlibs/rapidflex/src/pugixml.hpp new file mode 100644 index 000000000..55707f6fa --- /dev/null +++ b/techlibs/rapidflex/src/pugixml.hpp @@ -0,0 +1,1544 @@ +/** + * pugixml parser - version 1.7 + * -------------------------------------------------------- + * Copyright (C) 2006-2015, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com) + * Report bugs and download new versions at http://pugixml.org/ + * + * This library is distributed under the MIT License. See notice at the end + * of this file. + * + * This work is based on the pugxml parser, which is: + * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net) + */ + +#ifndef PUGIXML_VERSION +// Define version macro; evaluates to major * 100 + minor so that it's safe to +// use in less-than comparisons +#define PUGIXML_VERSION 170 +#endif + +// Include user configuration file (this can define various configuration +// macros) +#include "pugiconfig.hpp" + +#ifndef HEADER_PUGIXML_HPP +#define HEADER_PUGIXML_HPP + +// Include stddef.h for size_t and ptrdiff_t +#include + +// Include exception header for XPath +#if !defined(PUGIXML_NO_XPATH) && !defined(PUGIXML_NO_EXCEPTIONS) +#include +#endif + +// Include STL headers +#ifndef PUGIXML_NO_STL +#include +#include +#include +#endif + +// Macro for deprecated features +#ifndef PUGIXML_DEPRECATED +#if defined(__GNUC__) +#define PUGIXML_DEPRECATED __attribute__((deprecated)) +#elif defined(_MSC_VER) && _MSC_VER >= 1300 +#define PUGIXML_DEPRECATED __declspec(deprecated) +#else +#define PUGIXML_DEPRECATED +#endif +#endif + +// If no API is defined, assume default +#ifndef PUGIXML_API +#define PUGIXML_API +#endif + +// If no API for classes is defined, assume default +#ifndef PUGIXML_CLASS +#define PUGIXML_CLASS PUGIXML_API +#endif + +// If no API for functions is defined, assume default +#ifndef PUGIXML_FUNCTION +#define PUGIXML_FUNCTION PUGIXML_API +#endif + +// If the platform is known to have long long support, enable long long +// functions +#ifndef PUGIXML_HAS_LONG_LONG +#if __cplusplus >= 201103 +#define PUGIXML_HAS_LONG_LONG +#elif defined(_MSC_VER) && _MSC_VER >= 1400 +#define PUGIXML_HAS_LONG_LONG +#endif +#endif + +// Character interface macros +#ifdef PUGIXML_WCHAR_MODE +#define PUGIXML_TEXT(t) L##t +#define PUGIXML_CHAR wchar_t +#else +#define PUGIXML_TEXT(t) t +#define PUGIXML_CHAR char +#endif + +namespace pugi { +// Character type used for all internal storage and operations; depends on +// PUGIXML_WCHAR_MODE +typedef PUGIXML_CHAR char_t; + +#ifndef PUGIXML_NO_STL +// String type used for operations that work with STL string; depends on +// PUGIXML_WCHAR_MODE +typedef std::basic_string, + std::allocator> + string_t; +#endif +} // namespace pugi + +// The PugiXML namespace +namespace pugi { +// Tree node types +enum xml_node_type { + node_null, // Empty (null) node handle + node_document, // A document tree's absolute root + node_element, // Element tag, i.e. '' + node_pcdata, // Plain character data, i.e. 'text' + node_cdata, // Character data, i.e. '' + node_comment, // Comment tag, i.e. '' + node_pi, // Processing instruction, i.e. '' + node_declaration, // Document declaration, i.e. '' + node_doctype // Document type declaration, i.e. '' +}; + +// Parsing options + +// Minimal parsing mode (equivalent to turning all other flags off). +// Only elements and PCDATA sections are added to the DOM tree, no text +// conversions are performed. +const unsigned int parse_minimal = 0x0000; + +// This flag determines if processing instructions (node_pi) are added to the +// DOM tree. This flag is off by default. +const unsigned int parse_pi = 0x0001; + +// This flag determines if comments (node_comment) are added to the DOM tree. +// This flag is off by default. +const unsigned int parse_comments = 0x0002; + +// This flag determines if CDATA sections (node_cdata) are added to the DOM +// tree. This flag is on by default. +const unsigned int parse_cdata = 0x0004; + +// This flag determines if plain character data (node_pcdata) that consist only +// of whitespace are added to the DOM tree. This flag is off by default; turning +// it on usually results in slower parsing and more memory consumption. +const unsigned int parse_ws_pcdata = 0x0008; + +// This flag determines if character and entity references are expanded during +// parsing. This flag is on by default. +const unsigned int parse_escapes = 0x0010; + +// This flag determines if EOL characters are normalized (converted to #xA) +// during parsing. This flag is on by default. +const unsigned int parse_eol = 0x0020; + +// This flag determines if attribute values are normalized using CDATA +// normalization rules during parsing. This flag is on by default. +const unsigned int parse_wconv_attribute = 0x0040; + +// This flag determines if attribute values are normalized using NMTOKENS +// normalization rules during parsing. This flag is off by default. +const unsigned int parse_wnorm_attribute = 0x0080; + +// This flag determines if document declaration (node_declaration) is added to +// the DOM tree. This flag is off by default. +const unsigned int parse_declaration = 0x0100; + +// This flag determines if document type declaration (node_doctype) is added to +// the DOM tree. This flag is off by default. +const unsigned int parse_doctype = 0x0200; + +// This flag determines if plain character data (node_pcdata) that is the only +// child of the parent node and that consists only of whitespace is added to the +// DOM tree. This flag is off by default; turning it on may result in slower +// parsing and more memory consumption. +const unsigned int parse_ws_pcdata_single = 0x0400; + +// This flag determines if leading and trailing whitespace is to be removed from +// plain character data. This flag is off by default. +const unsigned int parse_trim_pcdata = 0x0800; + +// This flag determines if plain character data that does not have a parent node +// is added to the DOM tree, and if an empty document is a valid document. This +// flag is off by default. +const unsigned int parse_fragment = 0x1000; + +// The default parsing mode. +// Elements, PCDATA and CDATA sections are added to the DOM tree, +// character/reference entities are expanded, End-of-Line characters are +// normalized, attribute values are normalized using CDATA normalization rules. +const unsigned int parse_default = + parse_cdata | parse_escapes | parse_wconv_attribute | parse_eol; + +// The full parsing mode. +// Nodes of all types are added to the DOM tree, character/reference entities +// are expanded, End-of-Line characters are normalized, attribute values are +// normalized using CDATA normalization rules. +const unsigned int parse_full = parse_default | parse_pi | parse_comments | + parse_declaration | parse_doctype; + +// These flags determine the encoding of input data for XML document +enum xml_encoding { + encoding_auto, // Auto-detect input encoding using BOM or < / class xml_object_range { +public: + typedef It const_iterator; + typedef It iterator; + + xml_object_range(It b, It e) : _begin(b), _end(e) {} + + It begin() const { return _begin; } + It end() const { return _end; } + +private: + It _begin, _end; +}; + +// Writer interface for node printing (see xml_node::print) +class PUGIXML_CLASS xml_writer { +public: + virtual ~xml_writer() {} + + // Write memory chunk into stream/file/whatever + virtual void write(const void *data, size_t size) = 0; +}; + +// xml_writer implementation for FILE* +class PUGIXML_CLASS xml_writer_file : public xml_writer { +public: + // Construct writer from a FILE* object; void* is used to avoid header + // dependencies on stdio + xml_writer_file(void *file); + + virtual void write(const void *data, size_t size); + +private: + void *file; +}; + +#ifndef PUGIXML_NO_STL +// xml_writer implementation for streams +class PUGIXML_CLASS xml_writer_stream : public xml_writer { +public: + // Construct writer from an output stream object + xml_writer_stream(std::basic_ostream> &stream); + xml_writer_stream( + std::basic_ostream> &stream); + + virtual void write(const void *data, size_t size); + +private: + std::basic_ostream> *narrow_stream; + std::basic_ostream> *wide_stream; +}; +#endif + +// A light-weight handle for manipulating attributes in DOM tree +class PUGIXML_CLASS xml_attribute { + friend class xml_attribute_iterator; + friend class xml_node; + +private: + xml_attribute_struct *_attr; + + typedef void (*unspecified_bool_type)(xml_attribute ***); + +public: + // Default constructor. Constructs an empty attribute. + xml_attribute(); + + // Constructs attribute from internal pointer + explicit xml_attribute(xml_attribute_struct *attr); + + // Safe bool conversion operator + operator unspecified_bool_type() const; + + // Borland C++ workaround + bool operator!() const; + + // Comparison operators (compares wrapped attribute pointers) + bool operator==(const xml_attribute &r) const; + bool operator!=(const xml_attribute &r) const; + bool operator<(const xml_attribute &r) const; + bool operator>(const xml_attribute &r) const; + bool operator<=(const xml_attribute &r) const; + bool operator>=(const xml_attribute &r) const; + + // Check if attribute is empty + bool empty() const; + + // Get attribute name/value, or "" if attribute is empty + const char_t *name() const; + const char_t *value() const; + + // Get attribute value, or the default value if attribute is empty + const char_t *as_string(const char_t *def = PUGIXML_TEXT("")) const; + + // Get attribute value as a number, or the default value if conversion did not + // succeed or attribute is empty + int as_int(int def = 0) const; + unsigned int as_uint(unsigned int def = 0) const; + double as_double(double def = 0) const; + float as_float(float def = 0) const; + +#ifdef PUGIXML_HAS_LONG_LONG + long long as_llong(long long def = 0) const; + unsigned long long as_ullong(unsigned long long def = 0) const; +#endif + + // Get attribute value as bool (returns true if first character is in '1tTyY' + // set), or the default value if attribute is empty + bool as_bool(bool def = false) const; + + // Set attribute name/value (returns false if attribute is empty or there is + // not enough memory) + bool set_name(const char_t *rhs); + bool set_value(const char_t *rhs); + + // Set attribute value with type conversion (numbers are converted to strings, + // boolean is converted to "true"/"false") + bool set_value(int rhs); + bool set_value(unsigned int rhs); + bool set_value(double rhs); + bool set_value(float rhs); + bool set_value(bool rhs); + +#ifdef PUGIXML_HAS_LONG_LONG + bool set_value(long long rhs); + bool set_value(unsigned long long rhs); +#endif + + // Set attribute value (equivalent to set_value without error checking) + xml_attribute &operator=(const char_t *rhs); + xml_attribute &operator=(int rhs); + xml_attribute &operator=(unsigned int rhs); + xml_attribute &operator=(double rhs); + xml_attribute &operator=(float rhs); + xml_attribute &operator=(bool rhs); + +#ifdef PUGIXML_HAS_LONG_LONG + xml_attribute &operator=(long long rhs); + xml_attribute &operator=(unsigned long long rhs); +#endif + + // Get next/previous attribute in the attribute list of the parent node + xml_attribute next_attribute() const; + xml_attribute previous_attribute() const; + + // Get hash value (unique for handles to the same object) + size_t hash_value() const; + + // Get internal pointer + xml_attribute_struct *internal_object() const; +}; + +#ifdef __BORLANDC__ +// Borland C++ workaround +bool PUGIXML_FUNCTION operator&&(const xml_attribute &lhs, bool rhs); +bool PUGIXML_FUNCTION operator||(const xml_attribute &lhs, bool rhs); +#endif + +// A light-weight handle for manipulating nodes in DOM tree +class PUGIXML_CLASS xml_node { + friend class xml_attribute_iterator; + friend class xml_node_iterator; + friend class xml_named_node_iterator; + +protected: + xml_node_struct *_root; + + typedef void (*unspecified_bool_type)(xml_node ***); + +public: + // Default constructor. Constructs an empty node. + xml_node(); + + // Constructs node from internal pointer + explicit xml_node(xml_node_struct *p); + + // Safe bool conversion operator + operator unspecified_bool_type() const; + + // Borland C++ workaround + bool operator!() const; + + // Comparison operators (compares wrapped node pointers) + bool operator==(const xml_node &r) const; + bool operator!=(const xml_node &r) const; + bool operator<(const xml_node &r) const; + bool operator>(const xml_node &r) const; + bool operator<=(const xml_node &r) const; + bool operator>=(const xml_node &r) const; + + // Check if node is empty. + bool empty() const; + + // Get node type + xml_node_type type() const; + + // Get node name, or "" if node is empty or it has no name + const char_t *name() const; + + // Get node value, or "" if node is empty or it has no value + // Note: For text node.value() does not return "text"! Use + // child_value() or text() methods to access text inside nodes. + const char_t *value() const; + + // Get attribute list + xml_attribute first_attribute() const; + xml_attribute last_attribute() const; + + // Get children list + xml_node first_child() const; + xml_node last_child() const; + + // Get next/previous sibling in the children list of the parent node + xml_node next_sibling() const; + xml_node previous_sibling() const; + + // Get parent node + xml_node parent() const; + + // Get root of DOM tree this node belongs to + xml_node root() const; + + // Get text object for the current node + xml_text text() const; + + // Get child, attribute or next/previous sibling with the specified name + xml_node child(const char_t *name) const; + xml_attribute attribute(const char_t *name) const; + xml_node next_sibling(const char_t *name) const; + xml_node previous_sibling(const char_t *name) const; + + // Get attribute, starting the search from a hint (and updating hint so that + // searching for a sequence of attributes is fast) + xml_attribute attribute(const char_t *name, xml_attribute &hint) const; + + // Get child value of current node; that is, value of the first child node of + // type PCDATA/CDATA + const char_t *child_value() const; + + // Get child value of child with specified name. Equivalent to + // child(name).child_value(). + const char_t *child_value(const char_t *name) const; + + // Set node name/value (returns false if node is empty, there is not enough + // memory, or node can not have name/value) + bool set_name(const char_t *rhs); + bool set_value(const char_t *rhs); + + // Add attribute with specified name. Returns added attribute, or empty + // attribute on errors. + xml_attribute append_attribute(const char_t *name); + xml_attribute prepend_attribute(const char_t *name); + xml_attribute insert_attribute_after(const char_t *name, + const xml_attribute &attr); + xml_attribute insert_attribute_before(const char_t *name, + const xml_attribute &attr); + + // Add a copy of the specified attribute. Returns added attribute, or empty + // attribute on errors. + xml_attribute append_copy(const xml_attribute &proto); + xml_attribute prepend_copy(const xml_attribute &proto); + xml_attribute insert_copy_after(const xml_attribute &proto, + const xml_attribute &attr); + xml_attribute insert_copy_before(const xml_attribute &proto, + const xml_attribute &attr); + + // Add child node with specified type. Returns added node, or empty node on + // errors. + xml_node append_child(xml_node_type type = node_element); + xml_node prepend_child(xml_node_type type = node_element); + xml_node insert_child_after(xml_node_type type, const xml_node &node); + xml_node insert_child_before(xml_node_type type, const xml_node &node); + + // Add child element with specified name. Returns added node, or empty node on + // errors. + xml_node append_child(const char_t *name); + xml_node prepend_child(const char_t *name); + xml_node insert_child_after(const char_t *name, const xml_node &node); + xml_node insert_child_before(const char_t *name, const xml_node &node); + + // Add a copy of the specified node as a child. Returns added node, or empty + // node on errors. + xml_node append_copy(const xml_node &proto); + xml_node prepend_copy(const xml_node &proto); + xml_node insert_copy_after(const xml_node &proto, const xml_node &node); + xml_node insert_copy_before(const xml_node &proto, const xml_node &node); + + // Move the specified node to become a child of this node. Returns moved node, + // or empty node on errors. + xml_node append_move(const xml_node &moved); + xml_node prepend_move(const xml_node &moved); + xml_node insert_move_after(const xml_node &moved, const xml_node &node); + xml_node insert_move_before(const xml_node &moved, const xml_node &node); + + // Remove specified attribute + bool remove_attribute(const xml_attribute &a); + bool remove_attribute(const char_t *name); + + // Remove specified child + bool remove_child(const xml_node &n); + bool remove_child(const char_t *name); + + // Parses buffer as an XML document fragment and appends all nodes as children + // of the current node. Copies/converts the buffer, so it may be deleted or + // changed after the function returns. Note: append_buffer allocates memory + // that has the lifetime of the owning document; removing the appended nodes + // does not immediately reclaim that memory. + xml_parse_result append_buffer(const void *contents, size_t size, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + + // Find attribute using predicate. Returns first attribute for which predicate + // returned true. + template + xml_attribute find_attribute(Predicate pred) const { + if (!_root) + return xml_attribute(); + + for (xml_attribute attrib = first_attribute(); attrib; + attrib = attrib.next_attribute()) + if (pred(attrib)) + return attrib; + + return xml_attribute(); + } + + // Find child node using predicate. Returns first child for which predicate + // returned true. + template xml_node find_child(Predicate pred) const { + if (!_root) + return xml_node(); + + for (xml_node node = first_child(); node; node = node.next_sibling()) + if (pred(node)) + return node; + + return xml_node(); + } + + // Find node from subtree using predicate. Returns first node from subtree + // (depth-first), for which predicate returned true. + template xml_node find_node(Predicate pred) const { + if (!_root) + return xml_node(); + + xml_node cur = first_child(); + + while (cur._root && cur._root != _root) { + if (pred(cur)) + return cur; + + if (cur.first_child()) + cur = cur.first_child(); + else if (cur.next_sibling()) + cur = cur.next_sibling(); + else { + while (!cur.next_sibling() && cur._root != _root) + cur = cur.parent(); + + if (cur._root != _root) + cur = cur.next_sibling(); + } + } + + return xml_node(); + } + + // Find child node by attribute name/value + xml_node find_child_by_attribute(const char_t *name, const char_t *attr_name, + const char_t *attr_value) const; + xml_node find_child_by_attribute(const char_t *attr_name, + const char_t *attr_value) const; + +#ifndef PUGIXML_NO_STL + // Get the absolute node path from root as a text string. + string_t path(char_t delimiter = '/') const; +#endif + + // Search for a node by path consisting of node names and . or .. elements. + xml_node first_element_by_path(const char_t *path, + char_t delimiter = '/') const; + + // Recursively traverse subtree with xml_tree_walker + bool traverse(xml_tree_walker &walker); + +#ifndef PUGIXML_NO_XPATH + // Select single node by evaluating XPath query. Returns first node from the + // resulting node set. + xpath_node select_node(const char_t *query, + xpath_variable_set *variables = 0) const; + xpath_node select_node(const xpath_query &query) const; + + // Select node set by evaluating XPath query + xpath_node_set select_nodes(const char_t *query, + xpath_variable_set *variables = 0) const; + xpath_node_set select_nodes(const xpath_query &query) const; + + // (deprecated: use select_node instead) Select single node by evaluating + // XPath query. + xpath_node select_single_node(const char_t *query, + xpath_variable_set *variables = 0) const; + xpath_node select_single_node(const xpath_query &query) const; + +#endif + + // Print subtree using a writer object + void print(xml_writer &writer, const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, + xml_encoding encoding = encoding_auto, + unsigned int depth = 0) const; + +#ifndef PUGIXML_NO_STL + // Print subtree to stream + void print(std::basic_ostream> &os, + const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, + xml_encoding encoding = encoding_auto, + unsigned int depth = 0) const; + void print(std::basic_ostream> &os, + const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, unsigned int depth = 0) const; +#endif + + // Child nodes iterators + typedef xml_node_iterator iterator; + + iterator begin() const; + iterator end() const; + + // Attribute iterators + typedef xml_attribute_iterator attribute_iterator; + + attribute_iterator attributes_begin() const; + attribute_iterator attributes_end() const; + + // Range-based for support + xml_object_range children() const; + xml_object_range children(const char_t *name) const; + xml_object_range attributes() const; + + // Get node offset in parsed file/string (in char_t units) for debugging + // purposes + ptrdiff_t offset_debug() const; + + // Get hash value (unique for handles to the same object) + size_t hash_value() const; + + // Get internal pointer + xml_node_struct *internal_object() const; +}; + +#ifdef __BORLANDC__ +// Borland C++ workaround +bool PUGIXML_FUNCTION operator&&(const xml_node &lhs, bool rhs); +bool PUGIXML_FUNCTION operator||(const xml_node &lhs, bool rhs); +#endif + +// A helper for working with text inside PCDATA nodes +class PUGIXML_CLASS xml_text { + friend class xml_node; + + xml_node_struct *_root; + + typedef void (*unspecified_bool_type)(xml_text ***); + + explicit xml_text(xml_node_struct *root); + + xml_node_struct *_data_new(); + xml_node_struct *_data() const; + +public: + // Default constructor. Constructs an empty object. + xml_text(); + + // Safe bool conversion operator + operator unspecified_bool_type() const; + + // Borland C++ workaround + bool operator!() const; + + // Check if text object is empty + bool empty() const; + + // Get text, or "" if object is empty + const char_t *get() const; + + // Get text, or the default value if object is empty + const char_t *as_string(const char_t *def = PUGIXML_TEXT("")) const; + + // Get text as a number, or the default value if conversion did not succeed or + // object is empty + int as_int(int def = 0) const; + unsigned int as_uint(unsigned int def = 0) const; + double as_double(double def = 0) const; + float as_float(float def = 0) const; + +#ifdef PUGIXML_HAS_LONG_LONG + long long as_llong(long long def = 0) const; + unsigned long long as_ullong(unsigned long long def = 0) const; +#endif + + // Get text as bool (returns true if first character is in '1tTyY' set), or + // the default value if object is empty + bool as_bool(bool def = false) const; + + // Set text (returns false if object is empty or there is not enough memory) + bool set(const char_t *rhs); + + // Set text with type conversion (numbers are converted to strings, boolean is + // converted to "true"/"false") + bool set(int rhs); + bool set(unsigned int rhs); + bool set(double rhs); + bool set(float rhs); + bool set(bool rhs); + +#ifdef PUGIXML_HAS_LONG_LONG + bool set(long long rhs); + bool set(unsigned long long rhs); +#endif + + // Set text (equivalent to set without error checking) + xml_text &operator=(const char_t *rhs); + xml_text &operator=(int rhs); + xml_text &operator=(unsigned int rhs); + xml_text &operator=(double rhs); + xml_text &operator=(float rhs); + xml_text &operator=(bool rhs); + +#ifdef PUGIXML_HAS_LONG_LONG + xml_text &operator=(long long rhs); + xml_text &operator=(unsigned long long rhs); +#endif + + // Get the data node (node_pcdata or node_cdata) for this object + xml_node data() const; +}; + +#ifdef __BORLANDC__ +// Borland C++ workaround +bool PUGIXML_FUNCTION operator&&(const xml_text &lhs, bool rhs); +bool PUGIXML_FUNCTION operator||(const xml_text &lhs, bool rhs); +#endif + +// Child node iterator (a bidirectional iterator over a collection of xml_node) +class PUGIXML_CLASS xml_node_iterator { + friend class xml_node; + +private: + mutable xml_node _wrap; + xml_node _parent; + + xml_node_iterator(xml_node_struct *ref, xml_node_struct *parent); + +public: + // Iterator traits + typedef ptrdiff_t difference_type; + typedef xml_node value_type; + typedef xml_node *pointer; + typedef xml_node &reference; + +#ifndef PUGIXML_NO_STL + typedef std::bidirectional_iterator_tag iterator_category; +#endif + + // Default constructor + xml_node_iterator(); + + // Construct an iterator which points to the specified node + xml_node_iterator(const xml_node &node); + + // Iterator operators + bool operator==(const xml_node_iterator &rhs) const; + bool operator!=(const xml_node_iterator &rhs) const; + + xml_node &operator*() const; + xml_node *operator->() const; + + const xml_node_iterator &operator++(); + xml_node_iterator operator++(int); + + const xml_node_iterator &operator--(); + xml_node_iterator operator--(int); +}; + +// Attribute iterator (a bidirectional iterator over a collection of +// xml_attribute) +class PUGIXML_CLASS xml_attribute_iterator { + friend class xml_node; + +private: + mutable xml_attribute _wrap; + xml_node _parent; + + xml_attribute_iterator(xml_attribute_struct *ref, xml_node_struct *parent); + +public: + // Iterator traits + typedef ptrdiff_t difference_type; + typedef xml_attribute value_type; + typedef xml_attribute *pointer; + typedef xml_attribute &reference; + +#ifndef PUGIXML_NO_STL + typedef std::bidirectional_iterator_tag iterator_category; +#endif + + // Default constructor + xml_attribute_iterator(); + + // Construct an iterator which points to the specified attribute + xml_attribute_iterator(const xml_attribute &attr, const xml_node &parent); + + // Iterator operators + bool operator==(const xml_attribute_iterator &rhs) const; + bool operator!=(const xml_attribute_iterator &rhs) const; + + xml_attribute &operator*() const; + xml_attribute *operator->() const; + + const xml_attribute_iterator &operator++(); + xml_attribute_iterator operator++(int); + + const xml_attribute_iterator &operator--(); + xml_attribute_iterator operator--(int); +}; + +// Named node range helper +class PUGIXML_CLASS xml_named_node_iterator { + friend class xml_node; + +public: + // Iterator traits + typedef ptrdiff_t difference_type; + typedef xml_node value_type; + typedef xml_node *pointer; + typedef xml_node &reference; + +#ifndef PUGIXML_NO_STL + typedef std::bidirectional_iterator_tag iterator_category; +#endif + + // Default constructor + xml_named_node_iterator(); + + // Construct an iterator which points to the specified node + xml_named_node_iterator(const xml_node &node, const char_t *name); + + // Iterator operators + bool operator==(const xml_named_node_iterator &rhs) const; + bool operator!=(const xml_named_node_iterator &rhs) const; + + xml_node &operator*() const; + xml_node *operator->() const; + + const xml_named_node_iterator &operator++(); + xml_named_node_iterator operator++(int); + + const xml_named_node_iterator &operator--(); + xml_named_node_iterator operator--(int); + +private: + mutable xml_node _wrap; + xml_node _parent; + const char_t *_name; + + xml_named_node_iterator(xml_node_struct *ref, xml_node_struct *parent, + const char_t *name); +}; + +// Abstract tree walker class (see xml_node::traverse) +class PUGIXML_CLASS xml_tree_walker { + friend class xml_node; + +private: + int _depth; + +protected: + // Get current traversal depth + int depth() const; + +public: + xml_tree_walker(); + virtual ~xml_tree_walker(); + + // Callback that is called when traversal begins + virtual bool begin(xml_node &node); + + // Callback that is called for each node traversed + virtual bool for_each(xml_node &node) = 0; + + // Callback that is called when traversal ends + virtual bool end(xml_node &node); +}; + +// Parsing status, returned as part of xml_parse_result object +enum xml_parse_status { + status_ok = 0, // No error + + status_file_not_found, // File was not found during load_file() + status_io_error, // Error reading from file/stream + status_out_of_memory, // Could not allocate memory + status_internal_error, // Internal error occurred + + status_unrecognized_tag, // Parser could not determine tag type + + status_bad_pi, // Parsing error occurred while parsing document + // declaration/processing instruction + status_bad_comment, // Parsing error occurred while parsing comment + status_bad_cdata, // Parsing error occurred while parsing CDATA section + status_bad_doctype, // Parsing error occurred while parsing document type + // declaration + status_bad_pcdata, // Parsing error occurred while parsing PCDATA section + status_bad_start_element, // Parsing error occurred while parsing start + // element tag + status_bad_attribute, // Parsing error occurred while parsing element + // attribute + status_bad_end_element, // Parsing error occurred while parsing end element + // tag + status_end_element_mismatch, // There was a mismatch of start-end tags + // (closing tag had incorrect name, some tag was + // not closed or there was an excessive closing + // tag) + + status_append_invalid_root, // Unable to append nodes since root type is not + // node_element or node_document (exclusive to + // xml_node::append_buffer) + + status_no_document_element // Parsing resulted in a document without element + // nodes +}; + +// Parsing result +struct PUGIXML_CLASS xml_parse_result { + // Parsing status (see xml_parse_status) + xml_parse_status status; + + // Last parsed offset (in char_t units from start of input data) + ptrdiff_t offset; + + // Source document encoding + xml_encoding encoding; + + // Default constructor, initializes object to failed state + xml_parse_result(); + + // Cast to bool operator + operator bool() const; + + // Get error description + const char *description() const; +}; + +// Document class (DOM tree root) +class PUGIXML_CLASS xml_document : public xml_node { +private: + char_t *_buffer; + + char _memory[192]; + + // Non-copyable semantics + xml_document(const xml_document &); + xml_document &operator=(const xml_document &); + + void create(); + void destroy(); + +public: + // Default constructor, makes empty document + xml_document(); + + // Destructor, invalidates all node/attribute handles to this document + ~xml_document(); + + // Removes all nodes, leaving the empty document + void reset(); + + // Removes all nodes, then copies the entire contents of the specified + // document + void reset(const xml_document &proto); + +#ifndef PUGIXML_NO_STL + // Load document from stream. + xml_parse_result + load(std::basic_istream> &stream, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + xml_parse_result + load(std::basic_istream> &stream, + unsigned int options = parse_default); +#endif + + // (deprecated: use load_string instead) Load document from zero-terminated + // string. No encoding conversions are applied. + xml_parse_result load(const char_t *contents, + unsigned int options = parse_default); + + // Load document from zero-terminated string. No encoding conversions are + // applied. + xml_parse_result load_string(const char_t *contents, + unsigned int options = parse_default); + + // Load document from file + xml_parse_result load_file(const char *path, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + xml_parse_result load_file(const wchar_t *path, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + + // Load document from buffer. Copies/converts the buffer, so it may be deleted + // or changed after the function returns. + xml_parse_result load_buffer(const void *contents, size_t size, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + + // Load document from buffer, using the buffer for in-place parsing (the + // buffer is modified and used for storage of document data). You should + // ensure that buffer data will persist throughout the document's lifetime, + // and free the buffer memory manually once document is destroyed. + xml_parse_result load_buffer_inplace(void *contents, size_t size, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + + // Load document from buffer, using the buffer for in-place parsing (the + // buffer is modified and used for storage of document data). You should + // allocate the buffer with pugixml allocation function; document will free + // the buffer when it is no longer needed (you can't use it anymore). + xml_parse_result + load_buffer_inplace_own(void *contents, size_t size, + unsigned int options = parse_default, + xml_encoding encoding = encoding_auto); + + // Save XML document to writer (semantics is slightly different from + // xml_node::print, see documentation for details). + void save(xml_writer &writer, const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, + xml_encoding encoding = encoding_auto) const; + +#ifndef PUGIXML_NO_STL + // Save XML document to stream (semantics is slightly different from + // xml_node::print, see documentation for details). + void save(std::basic_ostream> &stream, + const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, + xml_encoding encoding = encoding_auto) const; + void save(std::basic_ostream> &stream, + const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default) const; +#endif + + // Save XML to file + bool save_file(const char *path, const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, + xml_encoding encoding = encoding_auto) const; + bool save_file(const wchar_t *path, const char_t *indent = PUGIXML_TEXT("\t"), + unsigned int flags = format_default, + xml_encoding encoding = encoding_auto) const; + + // Get document element + xml_node document_element() const; +}; + +#ifndef PUGIXML_NO_XPATH +// XPath query return type +enum xpath_value_type { + xpath_type_none, // Unknown type (query failed to compile) + xpath_type_node_set, // Node set (xpath_node_set) + xpath_type_number, // Number + xpath_type_string, // String + xpath_type_boolean // Boolean +}; + +// XPath parsing result +struct PUGIXML_CLASS xpath_parse_result { + // Error message (0 if no error) + const char *error; + + // Last parsed offset (in char_t units from string start) + ptrdiff_t offset; + + // Default constructor, initializes object to failed state + xpath_parse_result(); + + // Cast to bool operator + operator bool() const; + + // Get error description + const char *description() const; +}; + +// A single XPath variable +class PUGIXML_CLASS xpath_variable { + friend class xpath_variable_set; + +protected: + xpath_value_type _type; + xpath_variable *_next; + + xpath_variable(xpath_value_type type); + + // Non-copyable semantics + xpath_variable(const xpath_variable &); + xpath_variable &operator=(const xpath_variable &); + +public: + // Get variable name + const char_t *name() const; + + // Get variable type + xpath_value_type type() const; + + // Get variable value; no type conversion is performed, default value (false, + // NaN, empty string, empty node set) is returned on type mismatch error + bool get_boolean() const; + double get_number() const; + const char_t *get_string() const; + const xpath_node_set &get_node_set() const; + + // Set variable value; no type conversion is performed, false is returned on + // type mismatch error + bool set(bool value); + bool set(double value); + bool set(const char_t *value); + bool set(const xpath_node_set &value); +}; + +// A set of XPath variables +class PUGIXML_CLASS xpath_variable_set { +private: + xpath_variable *_data[64]; + + void _assign(const xpath_variable_set &rhs); + void _swap(xpath_variable_set &rhs); + + xpath_variable *_find(const char_t *name) const; + + static bool _clone(xpath_variable *var, xpath_variable **out_result); + static void _destroy(xpath_variable *var); + +public: + // Default constructor/destructor + xpath_variable_set(); + ~xpath_variable_set(); + + // Copy constructor/assignment operator + xpath_variable_set(const xpath_variable_set &rhs); + xpath_variable_set &operator=(const xpath_variable_set &rhs); + +#if __cplusplus >= 201103 + // Move semantics support + xpath_variable_set(xpath_variable_set &&rhs); + xpath_variable_set &operator=(xpath_variable_set &&rhs); +#endif + + // Add a new variable or get the existing one, if the types match + xpath_variable *add(const char_t *name, xpath_value_type type); + + // Set value of an existing variable; no type conversion is performed, false + // is returned if there is no such variable or if types mismatch + bool set(const char_t *name, bool value); + bool set(const char_t *name, double value); + bool set(const char_t *name, const char_t *value); + bool set(const char_t *name, const xpath_node_set &value); + + // Get existing variable by name + xpath_variable *get(const char_t *name); + const xpath_variable *get(const char_t *name) const; +}; + +// A compiled XPath query object +class PUGIXML_CLASS xpath_query { +private: + void *_impl; + xpath_parse_result _result; + + typedef void (*unspecified_bool_type)(xpath_query ***); + + // Non-copyable semantics + xpath_query(const xpath_query &); + xpath_query &operator=(const xpath_query &); + +public: + // Construct a compiled object from XPath expression. + // If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on + // compilation errors. + explicit xpath_query(const char_t *query, xpath_variable_set *variables = 0); + + // Constructor + xpath_query(); + + // Destructor + ~xpath_query(); + +#if __cplusplus >= 201103 + // Move semantics support + xpath_query(xpath_query &&rhs); + xpath_query &operator=(xpath_query &&rhs); +#endif + + // Get query expression return type + xpath_value_type return_type() const; + + // Evaluate expression as boolean value in the specified context; performs + // type conversion if necessary. If PUGIXML_NO_EXCEPTIONS is not defined, + // throws std::bad_alloc on out of memory errors. + bool evaluate_boolean(const xpath_node &n) const; + + // Evaluate expression as double value in the specified context; performs type + // conversion if necessary. If PUGIXML_NO_EXCEPTIONS is not defined, throws + // std::bad_alloc on out of memory errors. + double evaluate_number(const xpath_node &n) const; + +#ifndef PUGIXML_NO_STL + // Evaluate expression as string value in the specified context; performs type + // conversion if necessary. If PUGIXML_NO_EXCEPTIONS is not defined, throws + // std::bad_alloc on out of memory errors. + string_t evaluate_string(const xpath_node &n) const; +#endif + + // Evaluate expression as string value in the specified context; performs type + // conversion if necessary. At most capacity characters are written to the + // destination buffer, full result size is returned (includes terminating + // zero). If PUGIXML_NO_EXCEPTIONS is not defined, throws std::bad_alloc on + // out of memory errors. If PUGIXML_NO_EXCEPTIONS is defined, returns empty + // set instead. + size_t evaluate_string(char_t *buffer, size_t capacity, + const xpath_node &n) const; + + // Evaluate expression as node set in the specified context. + // If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on type + // mismatch and std::bad_alloc on out of memory errors. If + // PUGIXML_NO_EXCEPTIONS is defined, returns empty node set instead. + xpath_node_set evaluate_node_set(const xpath_node &n) const; + + // Evaluate expression as node set in the specified context. + // Return first node in document order, or empty node if node set is empty. + // If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on type + // mismatch and std::bad_alloc on out of memory errors. If + // PUGIXML_NO_EXCEPTIONS is defined, returns empty node instead. + xpath_node evaluate_node(const xpath_node &n) const; + + // Get parsing result (used to get compilation errors in PUGIXML_NO_EXCEPTIONS + // mode) + const xpath_parse_result &result() const; + + // Safe bool conversion operator + operator unspecified_bool_type() const; + + // Borland C++ workaround + bool operator!() const; +}; + +#ifndef PUGIXML_NO_EXCEPTIONS +// XPath exception class +class PUGIXML_CLASS xpath_exception : public std::exception { +private: + xpath_parse_result _result; + +public: + // Construct exception from parse result + explicit xpath_exception(const xpath_parse_result &result); + + // Get error message + virtual const char *what() const throw(); + + // Get parse result + const xpath_parse_result &result() const; +}; +#endif + +// XPath node class (either xml_node or xml_attribute) +class PUGIXML_CLASS xpath_node { +private: + xml_node _node; + xml_attribute _attribute; + + typedef void (*unspecified_bool_type)(xpath_node ***); + +public: + // Default constructor; constructs empty XPath node + xpath_node(); + + // Construct XPath node from XML node/attribute + xpath_node(const xml_node &node); + xpath_node(const xml_attribute &attribute, const xml_node &parent); + + // Get node/attribute, if any + xml_node node() const; + xml_attribute attribute() const; + + // Get parent of contained node/attribute + xml_node parent() const; + + // Safe bool conversion operator + operator unspecified_bool_type() const; + + // Borland C++ workaround + bool operator!() const; + + // Comparison operators + bool operator==(const xpath_node &n) const; + bool operator!=(const xpath_node &n) const; +}; + +#ifdef __BORLANDC__ +// Borland C++ workaround +bool PUGIXML_FUNCTION operator&&(const xpath_node &lhs, bool rhs); +bool PUGIXML_FUNCTION operator||(const xpath_node &lhs, bool rhs); +#endif + +// A fixed-size collection of XPath nodes +class PUGIXML_CLASS xpath_node_set { +public: + // Collection type + enum type_t { + type_unsorted, // Not ordered + type_sorted, // Sorted by document order (ascending) + type_sorted_reverse // Sorted by document order (descending) + }; + + // Constant iterator type + typedef const xpath_node *const_iterator; + + // We define non-constant iterator to be the same as constant iterator so that + // various generic algorithms (i.e. boost foreach) work + typedef const xpath_node *iterator; + + // Default constructor. Constructs empty set. + xpath_node_set(); + + // Constructs a set from iterator range; data is not checked for duplicates + // and is not sorted according to provided type, so be careful + xpath_node_set(const_iterator begin, const_iterator end, + type_t type = type_unsorted); + + // Destructor + ~xpath_node_set(); + + // Copy constructor/assignment operator + xpath_node_set(const xpath_node_set &ns); + xpath_node_set &operator=(const xpath_node_set &ns); + +#if __cplusplus >= 201103 + // Move semantics support + xpath_node_set(xpath_node_set &&rhs); + xpath_node_set &operator=(xpath_node_set &&rhs); +#endif + + // Get collection type + type_t type() const; + + // Get collection size + size_t size() const; + + // Indexing operator + const xpath_node &operator[](size_t index) const; + + // Collection iterators + const_iterator begin() const; + const_iterator end() const; + + // Sort the collection in ascending/descending order by document order + void sort(bool reverse = false); + + // Get first node in the collection by document order + xpath_node first() const; + + // Check if collection is empty + bool empty() const; + +private: + type_t _type; + + xpath_node _storage; + + xpath_node *_begin; + xpath_node *_end; + + void _assign(const_iterator begin, const_iterator end, type_t type); + void _move(xpath_node_set &rhs); +}; +#endif + +#ifndef PUGIXML_NO_STL +// Convert wide string to UTF8 +std::basic_string, std::allocator> + PUGIXML_FUNCTION as_utf8(const wchar_t *str); +std::basic_string, std::allocator> + PUGIXML_FUNCTION + as_utf8(const std::basic_string, + std::allocator> &str); + +// Convert UTF8 to wide string +std::basic_string, std::allocator> + PUGIXML_FUNCTION as_wide(const char *str); +std::basic_string, std::allocator> + PUGIXML_FUNCTION + as_wide(const std::basic_string, + std::allocator> &str); +#endif + +// Memory allocation function interface; returns pointer to allocated memory or +// NULL on failure +typedef void *(*allocation_function)(size_t size); + +// Memory deallocation function interface +typedef void (*deallocation_function)(void *ptr); + +// Override default memory management functions. All subsequent +// allocations/deallocations will be performed via supplied functions. +void PUGIXML_FUNCTION set_memory_management_functions( + allocation_function allocate, deallocation_function deallocate); + +// Get current memory management functions +allocation_function PUGIXML_FUNCTION get_memory_allocation_function(); +deallocation_function PUGIXML_FUNCTION get_memory_deallocation_function(); +} // namespace pugi + +#if !defined(PUGIXML_NO_STL) && (defined(_MSC_VER) || defined(__ICC)) +namespace std { +// Workarounds for (non-standard) iterator category detection for older versions +// (MSVC7/IC8 and earlier) +std::bidirectional_iterator_tag PUGIXML_FUNCTION +_Iter_cat(const pugi::xml_node_iterator &); +std::bidirectional_iterator_tag PUGIXML_FUNCTION +_Iter_cat(const pugi::xml_attribute_iterator &); +std::bidirectional_iterator_tag PUGIXML_FUNCTION +_Iter_cat(const pugi::xml_named_node_iterator &); +} // namespace std +#endif + +#if !defined(PUGIXML_NO_STL) && defined(__SUNPRO_CC) +namespace std { +// Workarounds for (non-standard) iterator category detection +std::bidirectional_iterator_tag PUGIXML_FUNCTION +__iterator_category(const pugi::xml_node_iterator &); +std::bidirectional_iterator_tag PUGIXML_FUNCTION +__iterator_category(const pugi::xml_attribute_iterator &); +std::bidirectional_iterator_tag PUGIXML_FUNCTION +__iterator_category(const pugi::xml_named_node_iterator &); +} // namespace std +#endif + +#endif + +// Make sure implementation is included in header-only mode +// Use macro expansion in #include to work around QMake (QTBUG-11923) +#if defined(PUGIXML_HEADER_ONLY) && !defined(PUGIXML_SOURCE) +#define PUGIXML_SOURCE "pugixml.cpp" +#include PUGIXML_SOURCE +#endif + +/** + * Copyright (c) 2006-2015 Arseny Kapoulkine + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ diff --git a/techlibs/rapidflex/src/rf_dsp_mad.cc b/techlibs/rapidflex/src/rf_dsp_mad.cc new file mode 100644 index 000000000..1ccdf4a79 --- /dev/null +++ b/techlibs/rapidflex/src/rf_dsp_mad.cc @@ -0,0 +1,192 @@ +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "pmgen/rf_dsp_mad.h" + +static void create_rf_mad_dsp(rf_dsp_mad_pm &pm) { + auto &st = pm.st_rf_dsp_mad; + + // Reject if multiplier drives anything else than $add + if (st.mul_nusers > 2) { + return; + } + + // Get port widths + size_t a_width = GetSize(st.mul->getPort(ID(A))); + size_t b_width = GetSize(st.mul->getPort(ID(B))); + size_t c_width = GetSize(st.add->getPort(ID(A))); + if (st.add_ba == ID(B)) { + c_width = GetSize(st.add->getPort(ID(B))); + } + size_t z_width = GetSize(st.add->getPort(ID(Y))); + + size_t min_width = std::min(a_width, b_width); + size_t max_width = std::max(a_width, b_width); + + // Signed / unsigned + bool a_signed = st.mul->getParam(ID(A_SIGNED)).as_bool(); + bool b_signed = st.mul->getParam(ID(B_SIGNED)).as_bool(); + bool c_signed = st.add->getParam(ID(A_SIGNED)).as_bool(); + if (st.add_ba == ID(B)) { + c_signed = st.add->getParam(ID(B_SIGNED)).as_bool(); + } + + // Determine DSP type or discard if too narrow / wide + RTLIL::IdString type; + size_t tgt_a_width; + size_t tgt_b_width; + size_t tgt_c_width; + size_t tgt_z_width; + + string cell_base_name = "mad"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (min_width <= 2 && max_width <= 2 && z_width <= 4) { + // Too narrow + return; + } else if (min_width <= 12 && max_width <= 10 && z_width <= 22) { + cell_size_name = "12x10x22"; + tgt_a_width = 12; + tgt_b_width = 10; + tgt_c_width = 22; + tgt_z_width = 22; + } else if (min_width <= 24 && max_width <= 20 && z_width <= 44) { + cell_size_name = "24x20x44"; + tgt_a_width = 24; + tgt_b_width = 20; + tgt_c_width = 44; + tgt_z_width = 44; + } else { + // Too wide + return; + } + + cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; + + type = RTLIL::escape_id(cell_full_name); + log("Inferring MAD %zux%zu+%zu->%zu as %s from:\n", a_width, b_width, c_width, + z_width, RTLIL::unescape_id(type).c_str()); + + for (auto cell : {st.mul, st.add}) { + if (cell != nullptr) { + log(" %s (%s)\n", RTLIL::unescape_id(cell->name).c_str(), + RTLIL::unescape_id(cell->type).c_str()); + } + } + + // Build the DSP cell name + std::string name; + name += RTLIL::unescape_id(st.mul->name) + "_"; + name += RTLIL::unescape_id(st.add->name) + "_"; + + // Add the DSP cell + RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(name), type); + + // Set attributes + cell->set_bool_attribute(RTLIL::escape_id("is_inferred"), true); + + // Get input/output data signals + RTLIL::SigSpec sig_a; + RTLIL::SigSpec sig_b; + RTLIL::SigSpec sig_c; + RTLIL::SigSpec sig_z; + + if (a_width >= b_width) { + sig_a = st.mul->getPort(ID(A)); + sig_b = st.mul->getPort(ID(B)); + } else { + sig_a = st.mul->getPort(ID(B)); + sig_b = st.mul->getPort(ID(A)); + } + + sig_c = st.add->getPort(ID(A)); + if (st.add_ba == ID(B)) { + sig_c = st.add->getPort(ID(B)); + } + sig_z = st.add->getPort(ID(Y)); + + // Connect input data ports, sign extend / pad with zeros + sig_a.extend_u0(tgt_a_width, a_signed); + sig_b.extend_u0(tgt_b_width, b_signed); + sig_c.extend_u0(tgt_c_width, c_signed); + cell->setPort(RTLIL::escape_id("A0"), sig_a); + cell->setPort(RTLIL::escape_id("B0"), sig_b); + + // Connect input data port, pad if needed + if ((size_t)GetSize(sig_c) < tgt_c_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_c_width - GetSize(sig_c)); + sig_c.append(wire); + } + cell->setPort(RTLIL::escape_id("C0"), sig_c); + + // Connect output data port, pad if needed + if ((size_t)GetSize(sig_z) < tgt_z_width) { + auto *wire = pm.module->addWire(NEW_ID, tgt_z_width - GetSize(sig_z)); + sig_z.append(wire); + } + cell->setPort(RTLIL::escape_id("Y"), sig_z); + + bool subtract = (st.add->type == RTLIL::escape_id("$sub")); + if (subtract) { + cell->setPort(RTLIL::escape_id("subtract_i"), + RTLIL::SigSpec(subtract ? RTLIL::S1 : RTLIL::S0)); + } + + // Mark the cells for removal + pm.autoremove(st.mul); + pm.autoremove(st.add); +} + +struct RfDspMacc : public Pass { + // Local variables + bool show_help; + + RfDspMacc() + : Pass("rf_dsp_mad", "Extract multiply-add and multiply-subtract " + "operators and map to dedicated DSPs") {} + + void help() override { + log("\n"); + log(" rf_dsp_mad [options] [selection]\n"); + log("\n"); + log(" Extract multiply-add and multiply-subtract operators and map to " + "dedicated DSPs\n"); + log("\n"); + log(" -help: show help desk\n"); + log("\n"); + } + + void clear_flags() override { show_help = false; } + + void execute(std::vector a_Args, + RTLIL::Design *a_Design) override { + log_header(a_Design, "Executing RF_DSP_MAD pass.\n"); + + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + if (a_Args[argidx] == "-help") { + show_help = true; + continue; + } + break; + } + extra_args(a_Args, argidx, a_Design); + if (show_help) { + help(); + return; + } + + for (auto module : a_Design->selected_modules()) { + rf_dsp_mad_pm(module, module->selected_cells()) + .run_rf_dsp_mad(create_rf_mad_dsp); + } + } + +} RfDspMad; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/rapidflex/src/rf_dsp_mad.pmg b/techlibs/rapidflex/src/rf_dsp_mad.pmg new file mode 100644 index 000000000..fa3a75dd3 --- /dev/null +++ b/techlibs/rapidflex/src/rf_dsp_mad.pmg @@ -0,0 +1,26 @@ +pattern rf_dsp_mad + +state add_ba + +state mul_nusers +state add_nusers + +match mul + select mul->type.in($mul) + select nusers(port(mul, \Y)) <= 3 + set mul_nusers nusers(port(mul, \Y)) +endmatch + +match add + select add->type.in($add, $sub) + choice AB {\A, \B} + define BA (AB == \A ? \B : \A) + index port(add, AB) === port(mul, \Y) + select nusers(port(add, \Y)) <= 3 + set add_nusers nusers(port(add, \Y)) + set add_ba BA +endmatch + +code + accept; +endcode diff --git a/techlibs/rapidflex/src/rf_new_dsp.cc b/techlibs/rapidflex/src/rf_new_dsp.cc new file mode 100644 index 000000000..aa42742e2 --- /dev/null +++ b/techlibs/rapidflex/src/rf_new_dsp.cc @@ -0,0 +1,441 @@ +#include "kernel/sigtools.h" +#include "kernel/yosys.h" + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#include "pmgen/rf_new_dsp.h" + +void swapinput(RTLIL::SigSpec &sigA, RTLIL::SigSpec &sigB) { + if (GetSize(sigA) < GetSize(sigB)) { + RTLIL::SigSpec sigC = sigB; + sigB = sigA; + sigA = sigC; + } +} + +void rf_new_dsp(rf_new_dsp_pm &pm) { + auto &st = pm.st_rf_new_dsp; + + log("mul1: %s\n", log_id(st.mul1, "--")); + log("mul2: %s\n", log_id(st.mul2, "--")); + log("mul3: %s\n", log_id(st.mul3, "--")); + log("mul4: %s\n", log_id(st.mul4, "--")); + log("postAdd1: %s\n", log_id(st.postAdd1, "--")); + log("postAdd2: %s\n", log_id(st.postAdd2, "--")); + log("postAdd3: %s\n", log_id(st.postAdd3, "--")); + log("postAdd4: %s\n", log_id(st.postAdd4, "--")); + + RTLIL::SigSpec sigA, sigB, sigD, sigY; + + // mode + string mode; + if (st.level == 4) { + if (st.dinput) + mode += + "1001"; // 4-level mac with d input: d + a1*b1 + a2*b2 + a3*b3 + a4*b4 + else + mode += + "0000"; // 4-level mac without d input: a1*b1 + a2*b2 + a3*b3 + a4*b4 + } + if (st.level == 3) + mode += "1001"; // 3-level mac with d input: d + a1*b1 + a2*b2 + a3*b3 + if (st.level == 2) { + if (st.dinput) + mode += "0001"; // 2-level mac with d input: d + a1*b1 + a2*b2 + else + mode += "0010"; // 2-level mac without d input: a1*b1 + a2*b2 + } + if (st.level == 1) { + if (st.dinput) + mode += "0101"; // 1-level mac with d input: d + a1*b1 + else + return; + } + + // input size + int n_size = 0; + int m_size = 0; + int d_size = 0; + + string cell_base_name = "mad"; + string cell_size_name = ""; + string cell_cfg_name = ""; + string cell_full_name = ""; + + if (st.mul1) { + swapinput(st.sigA1, st.sigB1); + n_size = n_size > GetSize(st.sigA1) ? n_size : GetSize(st.sigA1); + m_size = m_size > GetSize(st.sigB1) ? m_size : GetSize(st.sigB1); + } + + if (st.mul2) { + swapinput(st.sigA2, st.sigB2); + n_size = n_size > GetSize(st.sigA2) ? n_size : GetSize(st.sigA2); + m_size = m_size > GetSize(st.sigB2) ? m_size : GetSize(st.sigB2); + } + + if (st.mul3) { + swapinput(st.sigA3, st.sigB3); + n_size = n_size > GetSize(st.sigA3) ? n_size : GetSize(st.sigA3); + m_size = m_size > GetSize(st.sigB3) ? m_size : GetSize(st.sigB3); + } + + if (st.mul4) { + swapinput(st.sigA4, st.sigB4); + n_size = n_size > GetSize(st.sigA4) ? n_size : GetSize(st.sigA4); + m_size = m_size > GetSize(st.sigB4) ? m_size : GetSize(st.sigB4); + } + + if (st.dinput) + d_size = GetSize(st.sigD); + + if (mode == "0100") { + n_size = (n_size + 1) / 2; + m_size = (m_size + 1) / 2; + } + + if (n_size <= 2 && m_size <= 2 && d_size <= 4) { + // Too narrow + return; + } else if (n_size <= 12 && m_size <= 10 && d_size <= 30) { + cell_size_name = "12x10x22"; + n_size = 12; + m_size = 10; + d_size = 30; + } else if (n_size <= 24 && m_size <= 20 && d_size <= 52) { + cell_size_name = "24x20x44"; + n_size = 24; + m_size = 20; + d_size = 52; + } else { + // Too wide + return; + } + + // cell + cell_full_name = cell_base_name + cell_size_name + cell_cfg_name; + + string cellname; + cellname += "newdsp_" + RTLIL::unescape_id(st.mul1->name); + RTLIL::Cell *cell = pm.module->addCell(RTLIL::escape_id(cellname), + RTLIL::escape_id(cell_full_name)); + + // D input + bool d_signed = false; + if (st.dinput) { + d_signed = st.postAdd1->getParam(ID(A_SIGNED)).as_bool(); + if (mode == "0001") + sigD.extend_u0(d_size); + sigD.append(st.sigD); + } + sigD.extend_u0(2 * d_size, d_signed); + + // output + if (st.multiout2 || st.multiout3) { + auto *wire = pm.module->addWire(NEW_ID, d_size - GetSize(st.sigY2)); + sigY.append(st.sigY2); + sigY.append(wire); + sigY.append(st.sigY); + } else if (mode == "0001" || (st.level == 4 && st.dinput)) { + auto *wire = pm.module->addWire(NEW_ID, d_size); + sigY.append(wire); + sigY.append(st.sigY); + } else + sigY.append(st.sigY); + auto *wire = pm.module->addWire(NEW_ID, 2 * d_size - GetSize(sigY)); + sigY.append(wire); + + // input + bool a_signed, b_signed; + if (mode == "0001") { + sigA.extend_u0(2 * n_size); + sigB.extend_u0(2 * m_size); + } + if (st.mul1 && mode != "0100") { + a_signed = st.mul1->getParam(ID(A_SIGNED)).as_bool(); + b_signed = st.mul1->getParam(ID(B_SIGNED)).as_bool(); + st.sigA1.extend_u0(n_size, a_signed); + st.sigB1.extend_u0(m_size, b_signed); + sigA.append(st.sigA1); + sigB.append(st.sigB1); + } + if (mode == "0100") { + a_signed = st.mul1->getParam(ID(A_SIGNED)).as_bool(); + b_signed = st.mul1->getParam(ID(B_SIGNED)).as_bool(); + st.sigA1.extend_u0(2 * n_size, a_signed); + st.sigB1.extend_u0(2 * m_size, b_signed); + sigA.append(st.sigA1); + sigB.append(st.sigB1); + } + if (!st.dinput && st.mul4) { + a_signed = st.mul4->getParam(ID(A_SIGNED)).as_bool(); + b_signed = st.mul4->getParam(ID(B_SIGNED)).as_bool(); + st.sigA4.extend_u0(n_size, a_signed); + st.sigB4.extend_u0(m_size, b_signed); + sigA.append(st.sigA4); + sigB.append(st.sigB4); + } + if (st.mul2) { + a_signed = st.mul2->getParam(ID(A_SIGNED)).as_bool(); + b_signed = st.mul2->getParam(ID(B_SIGNED)).as_bool(); + st.sigA2.extend_u0(n_size, a_signed); + st.sigB2.extend_u0(m_size, b_signed); + sigA.append(st.sigA2); + sigB.append(st.sigB2); + } + if (st.mul3) { + a_signed = st.mul3->getParam(ID(A_SIGNED)).as_bool(); + b_signed = st.mul3->getParam(ID(B_SIGNED)).as_bool(); + st.sigA3.extend_u0(n_size, a_signed); + st.sigB3.extend_u0(m_size, b_signed); + sigA.append(st.sigA3); + sigB.append(st.sigB3); + } + if (st.dinput && st.mul4) { + a_signed = st.mul4->getParam(ID(A_SIGNED)).as_bool(); + b_signed = st.mul4->getParam(ID(B_SIGNED)).as_bool(); + st.sigA4.extend_u0(n_size, a_signed); + st.sigB4.extend_u0(m_size, b_signed); + sigA.append(st.sigA4); + sigB.append(st.sigB4); + } + sigA.extend_u0(4 * n_size); + sigB.extend_u0(4 * m_size); + + // reg + mode = "00000" + mode + "0000"; + if (st.level == 1) { + if (st.ffA1 && st.ffB1 && !(st.dinput && !st.ffD)) { + mode[1] = mode[2] = '1'; + pm.autoremove(st.ffA1); + pm.autoremove(st.ffB1); + if (st.dinput) + pm.autoremove(st.ffD); + } + if (st.ffM1 && st.ffD && st.postAdd1) { + mode[11] = '1'; + pm.autoremove(st.ffM1); + pm.autoremove(st.ffD); + } + if (st.ffY1 || (!st.postAdd1 && st.ffM1)) { + mode[3] = mode[4] = '1'; + pm.autoremove(st.ffY1); + pm.autoremove(st.ffM1); + } + } + if (st.level == 2) { + if (st.ffA1 && st.ffB1 && st.ffA2 && st.ffB2 && st.dinput && + st.ffD) // in reg + { + mode[1] = mode[2] = '1'; + pm.autoremove(st.ffA1); + pm.autoremove(st.ffB1); + pm.autoremove(st.ffA2); + pm.autoremove(st.ffB2); + pm.autoremove(st.ffD); + } + if (st.ffA1 && st.ffB1 && st.ffA4 && st.ffB4 && !st.dinput) // in reg + { + mode[1] = mode[2] = '1'; + pm.autoremove(st.ffA1); + pm.autoremove(st.ffB1); + pm.autoremove(st.ffA4); + pm.autoremove(st.ffB4); + } + if (st.ffM1 && ((st.dinput && st.ffM2) || st.ffD)) // mul in reg + { + mode[11] = '1'; + pm.autoremove(st.ffM1); + pm.autoremove(st.ffD); + if (st.dinput) + pm.autoremove(st.ffM2); + } + if (st.ffY1 && st.ffY2 && st.dinput) // mul out reg + { + mode[12] = '1'; + pm.autoremove(st.ffY1); + pm.autoremove(st.ffY2); + } else if (st.ffY1 || st.ffY2) // out reg + { + mode[3] = mode[4] = '1'; + pm.autoremove(st.ffY1); + pm.autoremove(st.ffY2); + } + } + if (st.ffA1 && st.ffB1 && st.ffA2 && st.ffB2 && st.dinput && + st.ffD) // in reg low + { + mode[2] = '1'; + pm.autoremove(st.ffA1); + pm.autoremove(st.ffB1); + pm.autoremove(st.ffA2); + pm.autoremove(st.ffB2); + pm.autoremove(st.ffD); + } + if (st.ffA1 && st.ffB1 && st.ffA4 && st.ffB4 && !st.dinput) // in reg low + { + mode[2] = '1'; + pm.autoremove(st.ffA1); + pm.autoremove(st.ffB1); + pm.autoremove(st.ffA4); + pm.autoremove(st.ffB4); + } + if (st.level == 3) { + if (st.ffA3 && st.ffB3 && st.dinput) // in reg high + { + mode[1] = '1'; + pm.autoremove(st.ffA3); + pm.autoremove(st.ffB3); + } + if (st.ffA2 && st.ffB2 && !st.dinput) // in reg high + { + mode[1] = '1'; + pm.autoremove(st.ffA2); + pm.autoremove(st.ffB2); + } + if (st.ffM1 && st.ffM2 && ((st.dinput && st.ffM3) || st.ffD)) // mul in reg + { + mode[11] = '1'; + pm.autoremove(st.ffM1); + pm.autoremove(st.ffD); + pm.autoremove(st.ffM2); + if (st.dinput) + pm.autoremove(st.ffM3); + } + if (st.ffY1 && st.ffY2 && !(st.dinput && !st.ffY3)) // mul out reg + { + mode[12] = '1'; + pm.autoremove(st.ffY1); + pm.autoremove(st.ffY2); + if (st.dinput) + pm.autoremove(st.ffY3); + } else if (st.ffY2 || st.ffY3) // out reg + { + mode[3] = mode[4] = '1'; + pm.autoremove(st.ffY2); + pm.autoremove(st.ffY3); + } + } + if (st.level == 4) { + if (st.ffA3 && st.ffB3 && st.ffA4 && st.ffB4 && st.dinput) // in reg high + { + mode[1] = '1'; + pm.autoremove(st.ffA3); + pm.autoremove(st.ffB3); + pm.autoremove(st.ffA4); + pm.autoremove(st.ffB4); + } + if (st.ffA2 && st.ffB2 && st.ffA3 && st.ffB3 && !st.dinput) // in reg high + { + mode[1] = '1'; + pm.autoremove(st.ffA2); + pm.autoremove(st.ffB2); + pm.autoremove(st.ffA3); + pm.autoremove(st.ffB3); + } + if (st.ffM1 && st.ffM2 && st.ffM3 && + ((st.dinput && st.ffM4) || st.ffD)) // mul in reg + { + mode[11] = '1'; + pm.autoremove(st.ffM1); + pm.autoremove(st.ffD); + pm.autoremove(st.ffM2); + pm.autoremove(st.ffM3); + if (st.dinput) + pm.autoremove(st.ffM4); + } + if (st.ffY1 && st.ffY2 && st.ffY3 && + !(st.dinput && !st.ffY4)) // mul out reg + { + mode[12] = '1'; + pm.autoremove(st.ffY1); + pm.autoremove(st.ffY2); + pm.autoremove(st.ffY3); + if (st.dinput) + pm.autoremove(st.ffY4); + } else if (st.ffY3 || st.ffY4) // out reg high + { + if (st.multiout2 || st.multiout3) + mode[3] = '1'; + else + mode[3] = mode[4] = '1'; + pm.autoremove(st.ffY3); + pm.autoremove(st.ffY4); + } + if (st.ffMY) // out reg low + { + mode[4] = '1'; + pm.autoremove(st.ffMY); + } + } + + cell->setPort(RTLIL::escape_id("a_i"), sigA); + cell->setPort(RTLIL::escape_id("b_i"), sigB); + cell->setPort(RTLIL::escape_id("d_i"), sigD); + cell->setPort(RTLIL::escape_id("out_o"), sigY); + cell->setPort(RTLIL::escape_id("mode_i"), Const::from_string(mode)); + if (st.clock != SigBit()) + cell->setPort(RTLIL::escape_id("clk_i"), st.clock); + cell->setPort(RTLIL::escape_id("rst_acc"), RTLIL::SigSpec(0, 1)); + cell->setPort(RTLIL::escape_id("accsel"), RTLIL::SigSpec(0, 1)); + cell->setPort(RTLIL::escape_id("cas_g"), RTLIL::SigSpec(0, 1)); + + pm.autoremove(st.mul1); + pm.autoremove(st.mul2); + pm.autoremove(st.mul3); + pm.autoremove(st.mul4); + pm.autoremove(st.postAdd1); + pm.autoremove(st.postAdd2); + pm.autoremove(st.postAdd3); + pm.autoremove(st.postAdd4); +} + +struct RfNewDSP : public Pass { + bool show_help; + + RfNewDSP() + : Pass("rf_new_dsp", + "Extract multiply-add operators and map to new_dsps") {} + + void help() override { + log("\n"); + log(" rf_new_dsp [options] [selection]\n"); + log("\n"); + log(" Extract multiply-add operators and map to new_dsps\n"); + log("\n"); + log(" -help: show help desk\n"); + log("\n"); + log(" -n_size: specify input n size\n"); + log("\n"); + log(" -m_size: specify input m size\n"); + log("\n"); + } + + void clear_flags() override { show_help = false; } + + void execute(std::vector a_Args, + RTLIL::Design *a_Design) override { + log_header(a_Design, "Executing RF_NEW_DSP pass.\n"); + size_t argidx; + for (argidx = 1; argidx < a_Args.size(); argidx++) { + if (a_Args[argidx] == "-help") { + show_help = true; + continue; + } + break; + } + extra_args(a_Args, argidx, a_Design); + if (show_help) { + help(); + return; + } + + for (auto module : a_Design->selected_modules()) { + rf_new_dsp_pm pm(module, module->selected_cells()); + pm.run_rf_new_dsp(rf_new_dsp); + } + } +} RfNewDsp; + +PRIVATE_NAMESPACE_END \ No newline at end of file diff --git a/techlibs/rapidflex/src/rf_new_dsp.pmg b/techlibs/rapidflex/src/rf_new_dsp.pmg new file mode 100644 index 000000000..5f4f58337 --- /dev/null +++ b/techlibs/rapidflex/src/rf_new_dsp.pmg @@ -0,0 +1,478 @@ +pattern rf_new_dsp + +state clock +state sigA1 sigA2 sigA3 sigA4 +state sigB1 sigB2 sigB3 sigB4 +state sigD sigY sigY2 sigM + +state ffA1 ffA2 ffA3 ffA4 +state ffB1 ffB2 ffB3 ffB4 +state ffD +state ffM1 ffM2 ffM3 ffM4 +state ffY1 ffY2 ffY3 ffY4 ffMY +state postAdd1 postAdd2 postAdd3 postAdd4 +state mul2 mul3 mul4 + +state multiout2 multiout3 dinput y_signed y2_signed +state level + +// Variables used for subpatterns +state argQ argD argA argM +udata dffD dffQ addD addY +udata dffclock +udata dff postadder multiplier +state postAddAB + +// (1) match multiplier 1 +match mul1 + select mul1->type.in($mul) +endmatch + +code sigA1 sigB1 sigY multiout2 multiout3 dinput y_signed y2_signed level + sigA1 = port(mul1, \A); + sigB1 = port(mul1, \B); + sigY = port(mul1, \Y); + multiout2 = false; + multiout3 = false; + y_signed = param(mul1, \A_SIGNED).as_bool(); + dinput = false; + level = 1; +endcode + +// (2) Match A input register 1 +code argQ ffA1 sigA1 clock + argQ = sigA1; + subpattern(in_dffe); + if (dff) { + ffA1 = dff; + clock = dffclock; + sigA1 = dffD; + } +endcode + +// (3) Match B input register 1 +code argQ ffB1 sigB1 clock + argQ = sigB1; + subpattern(in_dffe); + if (dff) { + ffB1 = dff; + clock = dffclock; + sigB1 = dffD; + } +endcode + +// (4) Match mul output register 1 +code argD ffM1 sigY clock + argD = sigY; + subpattern(out_dffe); + if (dff) { + ffM1 = dff; + clock = dffclock; + sigY = dffQ; + } +endcode + +// (5) Match post adder 1 +code argA postAdd1 sigY sigD y_signed + argA = sigY; + subpattern(post_add); + if(postadder) { + postAdd1 = postadder; + sigY = addY; + sigD = addD; + y_signed = param(postAdd1, \A_SIGNED).as_bool(); + } +endcode + +// (6) Match D input register +code argQ ffD sigD clock + argQ = sigD; + subpattern(in_dffe); + if (dff) { + ffD = dff; + clock = dffclock; + sigD = dffD; + } +endcode + +// (6-1) Match multiplier 4 +code argM mul4 sigA4 sigB4 sigD level dinput + argM = sigD; + subpattern(more_mult); + if (multiplier) { + mul4 = multiplier; + sigA4 = port(mul4, \A); + sigB4 = port(mul4, \B); + level += 1; + } + else if(postAdd1) + { + dinput = true; + } +endcode + +// (7) Match mac output register 1 +code argD ffY1 sigY clock + argD = sigY; + subpattern(out_dffe); + if (dff) { + ffY1 = dff; + clock = dffclock; + sigY = dffQ; + } +endcode + +// (8) Match post adder 2 +code argA postAdd2 sigM sigY sigD y_signed + argA = sigY; + subpattern(post_add); + if(postadder) { + postAdd2 = postadder; + sigY = addY; + sigM = addD; + y_signed = param(postAdd2, \A_SIGNED).as_bool(); + } +endcode + +// (9) Match mul output register 2 +code argQ ffM2 sigM clock + argQ = sigM; + subpattern(in_dffe); + if (dff) { + ffM2 = dff; + clock = dffclock; + sigM = dffD; + } +endcode + +// (10) match multiplier 2 +code argM mul2 sigA2 sigB2 sigM level + argM = sigM; + subpattern(more_mult); + if (multiplier) { + mul2 = multiplier; + sigA2 = port(mul2, \A); + sigB2 = port(mul2, \B); + level += 1; + } + sigM.remove(0, GetSize(sigM)); +endcode + +// (11) Match A input register 2 +code argQ ffA2 sigA2 clock + argQ = sigA2; + subpattern(in_dffe); + if (dff) { + ffA2 = dff; + clock = dffclock; + sigA2 = dffD; + } +endcode + +// (12) Match B input register 2 +code argQ ffB2 sigB2 clock + argQ = sigB2; + subpattern(in_dffe); + if (dff) { + ffB2 = dff; + clock = dffclock; + sigB2 = dffD; + } +endcode + +// (13) Match mac output register 2 +code argD ffY2 sigY clock + argD = sigY; + subpattern(out_dffe); + if (dff) { + ffY2 = dff; + clock = dffclock; + sigY = dffQ; + } +endcode + +// (14) Match post adder 3 +code argA postAdd3 sigM sigY sigD y_signed + argA = sigY; + subpattern(post_add); + if(postadder) { + postAdd3 = postadder; + sigY = addY; + sigM = addD; + y_signed = param(postAdd3, \A_SIGNED).as_bool(); + } +endcode + +// (15) Match mul output register 3 +code argQ ffM3 sigM clock + argQ = sigM; + subpattern(in_dffe); + if (dff) { + ffM3 = dff; + clock = dffclock; + sigM = dffD; + } +endcode + +// (16) match multiplier 3 +code argM mul3 sigA3 sigB3 level sigM + argM = sigM; + subpattern(more_mult); + if (multiplier) { + mul3 = multiplier; + sigA3 = port(mul3, \A); + sigB3 = port(mul3, \B); + level += 1; + } + sigM.remove(0, GetSize(sigM)); +endcode + +// (17) Match A input register 3 +code argQ ffA3 sigA3 clock + argQ = sigA3; + subpattern(in_dffe); + if (dff) { + ffA3 = dff; + clock = dffclock; + sigA3 = dffD; + } +endcode + +// (18) Match B input register 3 +code argQ ffB3 sigB3 clock + argQ = sigB3; + subpattern(in_dffe); + if (dff) { + ffB3 = dff; + clock = dffclock; + sigB3 = dffD; + } +endcode + +// (19) Match mac output register 3 +code argD ffY3 sigY clock + argD = sigY; + subpattern(out_dffe); + if (dff) { + ffY3 = dff; + clock = dffclock; + sigY = dffQ; + } +endcode + +// (20) Match post adder 4 +code argA postAdd4 sigM sigY sigD y_signed + argA = sigY; + subpattern(post_add); + if(postadder) { + postAdd4 = postadder; + sigY = addY; + sigM = addD; + y_signed = param(postAdd4, \A_SIGNED).as_bool(); + } +endcode + +// (21) Match mul output register 4 +code argQ ffM4 sigM clock + argQ = sigM; + subpattern(in_dffe); + if (dff) { + ffM4 = dff; + clock = dffclock; + sigM = dffD; + } +endcode + +// (22) match multiplier 4 +code argM mul4 sigA4 sigB4 level sigM + argM = sigM; + if(!mul4) + { + subpattern(more_mult); + if (multiplier) { + mul4 = multiplier; + sigA4 = port(mul4, \A); + sigB4 = port(mul4, \B); + level += 1; + } + } + sigM.remove(0, GetSize(sigM)); +endcode + +// (23) Match A input register 4 +code argQ ffA4 sigA4 clock + argQ = sigA4; + subpattern(in_dffe); + if (dff) { + ffA4 = dff; + clock = dffclock; + sigA4 = dffD; + } +endcode + +// (24) Match B input register 4 +code argQ ffB4 sigB4 clock + argQ = sigB4; + subpattern(in_dffe); + if (dff) { + ffB4 = dff; + clock = dffclock; + sigB4 = dffD; + } +endcode + +// (25) Match mac output register 4 +code argD ffY4 sigY clock + argD = sigY; + subpattern(out_dffe); + if (dff) { + ffY4 = dff; + clock = dffclock; + sigY = dffQ; + } +endcode + +code + accept; +endcode + +// ####################### + +// Subpattern for matching against input registers + +subpattern in_dffe +arg argQ clock + +code + dff = nullptr; + if (argQ.empty()) + reject; + for (const auto &c : argQ.chunks()) + { + // Abandon matches when 'Q' is a constant + if (!c.wire) + reject; + // Abandon matches when 'Q' has the keep attribute set + if (c.wire->get_bool_attribute(\keep)) + reject; + } +endcode + +match ff + select ff->type.in($dff, $dffe, $sdff, $sdffe, $adff, $adffe) + + slice offset GetSize(port(ff, \D)) + index port(ff, \Q)[offset] === argQ[0] + + // Check that the rest of argQ is present + filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) + filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ + + filter clock == SigBit() || port(ff, \CLK) == clock +endmatch + +code argQ + SigSpec Q = port(ff, \Q); + dff = ff; + dffclock = port(ff, \CLK); + dffD = argQ; + SigSpec D = port(ff, \D); + argQ = Q; + dffD.replace(argQ, D); //to.replace(pattern, with). 'to' become 'with' according 'pattern' +endcode + +// ####################### + +// Subpattern for matching output registers + +subpattern out_dffe +arg argD argQ clock + +code + dff = nullptr; + for (auto c : argD.chunks()) + // Abandon matches when 'D' has the keep attribute set + if (c.wire->get_bool_attribute(\keep)) + reject; +endcode + +match ff + select ff->type.in($dff, $dffe, $sdff, $sdffe) + + slice offset GetSize(port(ff, \D)) + index port(ff, \D)[offset] === argD[0] + + // Check that the rest of argD is present + filter GetSize(port(ff, \D)) >= offset + GetSize(argD) + filter port(ff, \D).extract(offset, GetSize(argD)) == argD + + filter clock == SigBit() || port(ff, \CLK) == clock +endmatch + +code argQ + SigSpec D = port(ff, \D); + SigSpec Q = port(ff, \Q); + argQ = argD; + argQ.replace(D, Q); + + dff = ff; + dffQ = argQ; + dffclock = port(ff, \CLK); +endcode + +// ####################### + +// Subpattern for matching post adder + +subpattern post_add +arg argA + +code + postadder = nullptr; +endcode + +match adder + select adder->type.in($add) + choice AB {\A, \B} + select nusers(port(adder, AB)) == 2 + + index port(adder, AB)[0] === argA[0] + filter GetSize(port(adder, AB)) >= GetSize(argA) + filter port(adder, AB).extract(0, GetSize(argA)) == argA + + set postAddAB AB +endmatch + +code argA + SigSpec A = port(adder, postAddAB); + SigSpec D = port(adder, postAddAB == \A ? \B : \A); + SigSpec Y = port(adder, \Y); + + postadder = adder; + + addY = argA; + addY.replace(A, Y); + + addD = D; +endcode + +// ####################### + +// Subpattern for matching multiplier + +subpattern more_mult +arg argM + +code + multiplier = nullptr; +endcode + +match mult + select mult->type.in($mul) + filter GetSize(port(mult, \Y)) <= GetSize(argM) + filter port(mult, \Y) == argM.extract(0, GetSize(port(mult, \Y))) +endmatch + +code + multiplier = mult; +endcode \ No newline at end of file diff --git a/techlibs/rapidflex/src/synth_rf_alkaid.cc b/techlibs/rapidflex/src/synth_rf_alkaid.cc new file mode 100644 index 000000000..498e860e4 --- /dev/null +++ b/techlibs/rapidflex/src/synth_rf_alkaid.cc @@ -0,0 +1,526 @@ +/* + * Copyright 2020-2024 RapidFlex + */ +#include "kernel/celltypes.h" +#include "kernel/log.h" +#include "kernel/register.h" +#include "kernel/rtlil.h" +using namespace std; +/* Constants for device name */ +constexpr const char *ALKDC_DNAME = "alkaidC"; +constexpr const char *ALKDL_DNAME = "alkaidL"; +constexpr const char *ALKDT_DNAME = "alkaidT"; + +USING_YOSYS_NAMESPACE +PRIVATE_NAMESPACE_BEGIN + +#define XSTR(val) #val +#define STR(val) XSTR(val) + +#ifndef PASS_NAME +#define PASS_NAME synth_rf_alkaid +#endif + +struct SynthRapidFlexPass : public ScriptPass { + + SynthRapidFlexPass() + : ScriptPass(STR(PASS_NAME), "Synthesis for RapidFlex Alkaid FPGAs") {} + + void help() override { + log("\n"); + log(" %s [options]\n", STR(PASS_NAME)); + log("This command runs synthesis for RapidFlex Alkaid FPGAs\n"); + log("\n"); + log(" -top \n"); + log(" use the specified module as top module\n"); + log("\n"); + log(" -family \n"); + log(" run synthesis for the specified RapidFlex architecture\n"); + log(" generate the synthesis netlist for the specified family.\n"); + log(" supported values:\n"); + log(" - alkaidL\n"); + log(" - alkaidT\n"); + log(" - alkaidC\n"); + log("\n"); + log(" -edif \n"); + log(" write the design to the specified edif file. Writing of an " + "output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -blif \n"); + log(" write the design to the specified BLIF file. Writing of an " + "output file\n"); + log(" is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -verilog \n"); + log(" write the design to the specified verilog file. Writing of an " + "output\n"); + log(" file is omitted if this parameter is not specified.\n"); + log("\n"); + log(" -no_dsp\n"); + log(" By default use DSP blocks in output netlist.\n"); + log(" do not use DSP blocks to implement multipliers and associated " + "logic\n"); + log("\n"); + log(" -no_adder\n"); + log(" By default use adder cells in output netlist.\n"); + log(" Specifying this switch turns it off.\n"); + log("\n"); + log(" -no_bram\n"); + log(" By default use Block RAM in output netlist.\n"); + log(" Specifying this switch turns it off.\n"); + log("\n"); + log(" -insert_clock_buffer\n"); + log(" By default no insertion of clock buffer for output " + "netlist.\n"); + log(" -cell_map_file \n"); + log(" write the ckbuf into to the specified XML file. Writing of an " + "output file\n"); + log(" Specifying this switch turns it on.\n"); + log(" -K \n"); + log(" Specify the input size of LUT when running optimization. If " + "not specified, a default value will be applied. Please do not modify " + "this parameter except architecture exploration\n"); + log(" -parse_only\n"); + log(" Only apply verilog parsing. This is for rewriting purpose.\n"); + log(" Specifying this switch turns it on.\n"); + log("\n"); + log("The following commands are executed by this synthesis command:\n"); + log("\n"); + log(" -save_block_diagram \n"); + log(" generate a block diagram and save to the specified file\n"); + log(" supported formats: dot, png, svg, eps, pdf\n"); + log("\n"); + help_script(); + } + + std::string top_opt, edif_file, blif_file, family, currmodule, verilog_file, + cell_map_file, lib_path, block_diagram_file; + bool nodsp; + bool no_opt; + bool abc9; + bool inferAdder; + bool inferBram; + bool show_help; + bool insert_clock_buffer; + size_t DEFAULT_K = 5; + size_t MIN_K = 4; + size_t MAX_K = 6; + size_t max_lut_size = DEFAULT_K; + bool parse_only = false; + + void clear_flags() override { + top_opt = "-auto-top"; + edif_file = ""; + blif_file = ""; + cell_map_file = ""; + verilog_file = ""; + currmodule = ""; + family = ALKDL_DNAME; + inferAdder = true; + inferBram = true; + nodsp = false; + no_opt = false; + abc9 = false; + lib_path = "+/rapidflex/"; + show_help = false; + insert_clock_buffer = false; + max_lut_size = DEFAULT_K; + parse_only = false; + block_diagram_file = ""; + } + + void execute(std::vector args, RTLIL::Design *design) override { + string run_from, run_to; + clear_flags(); + lib_path = design->scratchpad_get_string("rf.lib_path", lib_path); + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) { + if (args[argidx] == "-run" && argidx + 1 < args.size()) { + size_t pos = args[argidx + 1].find(':'); + if (pos == std::string::npos) { + run_from = args[++argidx]; + run_to = args[argidx]; + } else { + run_from = args[++argidx].substr(0, pos); + run_to = args[argidx].substr(pos + 1); + } + continue; + } + if (args[argidx] == "-top" && argidx + 1 < args.size()) { + top_opt = "-top " + args[++argidx]; + continue; + } + if (args[argidx] == "-edif" && argidx + 1 < args.size()) { + edif_file = args[++argidx]; + continue; + } + + if (args[argidx] == "-family" && argidx + 1 < args.size()) { + family = args[++argidx]; + continue; + } + if (args[argidx] == "-blif" && argidx + 1 < args.size()) { + blif_file = args[++argidx]; + continue; + } + if (args[argidx] == "-cell_map_file" && argidx + 1 < args.size()) { + cell_map_file = args[++argidx]; + continue; + } + if (args[argidx] == "-verilog" && argidx + 1 < args.size()) { + verilog_file = args[++argidx]; + continue; + } + if (args[argidx] == "-K" && argidx + 1 < args.size()) { + max_lut_size = std::stoi(args[++argidx]); + continue; + } + if (args[argidx] == "-no_dsp") { + nodsp = true; + continue; + } + if (args[argidx] == "-no_adder") { + inferAdder = false; + continue; + } + if (args[argidx] == "-no_bram") { + inferBram = false; + continue; + } + if (args[argidx] == "-no_opt") { + no_opt = false; + continue; + } + if (args[argidx] == "-parse_only") { + parse_only = true; + continue; + } + if (args[argidx] == "-help") { + show_help = true; + continue; + } + if (args[argidx] == "-insert_clock_buffer") { + insert_clock_buffer = true; + continue; + } + if (args[argidx] == "-save_block_diagram") { + if (argidx + 1 < args.size() && args[argidx + 1][0] != '-') { + block_diagram_file = args[++argidx]; + } else { + block_diagram_file = ""; + } + continue; + } + break; + } + extra_args(args, argidx, design); + + if (show_help) { + help(); + return; + } + + if (!design->full_selection()) { + log_cmd_error("This command only operates on fully selected designs!\n"); + } + /* Pre-check on family name and confirm on selection*/ + if (family != ALKDL_DNAME && family != ALKDT_DNAME && + family != ALKDC_DNAME) { + log_cmd_error("Invalid family specified: '%s'\n", family.c_str()); + } + log("Selected device family: %s\n", family.c_str()); + /* Force to enable/disable options upon device limits */ + if (family == ALKDL_DNAME || family == ALKDC_DNAME) { + if (!nodsp) { + log_warning("Force to disable dsp inference as the selected device " + "does not contain dedicated resources\n"); + nodsp = true; + } + if (inferBram) { + log_warning("Force to disable RAM inference as the selected device " + "does not contain dedicated resources\n"); + inferBram = false; + } + } + /* By default, no opt should be enabled. Throw a warning if not */ + if (no_opt) { + log_warning("Force to disable any optimization, which may cast an " + "negative impact on QoR\n"); + } + if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { + log_warning("Delay target has not been set via SDC or scratchpad; " + "Assuming 1GHz clock.\n"); + design->scratchpad_set_int("abc9.W", + 1000); // set interconnet delay as 1ns + } + /* Sanity checks on max lut size */ + if (max_lut_size < MIN_K || max_lut_size > MAX_K) { + log_cmd_error( + "The provided K=%ld is out of the acceptable range [%ld, %ld]!\n", + max_lut_size, MIN_K, MAX_K); + return; + } + + log_header(design, "Executing SYNTH_RAPIDFLEX pass.\n"); + log_push(); + + run_script(design, run_from, run_to); + log_pop(); + } + + void script() override { + if (help_mode) { + family = ""; + } + + std::string noDFFArgs; + if (check_label("begin")) { + std::string family_path = " " + lib_path + family; + std::string read_vlog_args; + + // Read simulation library + read_vlog_args = family_path + "/cell_sim.v"; + + // Use -nomem2reg here to prevent Yosys from complaining about + // some block ram cell models. After all the only part of the cells + // library required here is cell port definitions plus specify blocks. + if (parse_only) { + run("read_verilog " + lib_path + "common/cells_sim.v" + read_vlog_args); + } else { + run("read_verilog -lib -specify -nomem2reg " + lib_path + + "common/cells_sim.v" + read_vlog_args); + } + run("logger -werror \"multiple conflicting drivers\""); + run("check"); + run(stringf("hierarchy -check %s", + help_mode ? "-top " : top_opt.c_str())); + run("stat"); + } + + if (check_label("prepare")) { + run("proc"); + run("flatten"); + if (parse_only) { + log("Running parse-only flow. Exit after flattening the design\n"); + return; + } + if (help_mode) { + run("tribuf -logic"); + } + if (!no_opt) { + run("opt_expr"); + run("opt_clean"); + } + run("deminout"); + if (!no_opt) { + run("opt -nodffe"); + } + + run("check"); + if (!no_opt) { + run("opt -nodffe"); + run("fsm"); + run("opt -nodffe"); + run("wreduce -keepdc"); + run("peepopt"); + run("pmuxtree"); + run("opt_clean"); + run("share"); + } + } + + if (check_label("map_dsp"), "(skip if -no_dsp)") { + struct DspParams { + size_t a_maxwidth; + size_t b_maxwidth; + size_t a_minwidth; + size_t b_minwidth; + std::string type; + }; + + const std::vector dsp_rules = { + {24, 20, 13, 11, "mult_24x20_map"}, + {12, 10, 2, 2, "mult_12x10_map"}, + }; + + if (help_mode || family == ALKDT_DNAME) { + if (help_mode || !nodsp) { + run("memory_dff", " (for alkaidT)"); + if (!no_opt) { + run("wreduce t:$mul", " (for alkaidT)"); + } + run("rf_new_dsp"); + for (const auto &rule : dsp_rules) { + run(stringf("techmap -map +/mul2dsp.v " + "-map %s/dsp_map.v " + "-D DSP_A_MAXWIDTH=%zu -D DSP_B_MAXWIDTH=%zu " + "-D DSP_A_MINWIDTH=%zu -D DSP_B_MINWIDTH=%zu " + "-D DSP_NAME=%s", + std::string(lib_path + family).c_str(), rule.a_maxwidth, + rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, + rule.type.c_str())); + /* Without the following command, some multiplier may be skipped */ + run("chtype -set $mul t:$__soft_mul", " (for alkaidT)"); + } + run("select a:mul2dsp", " (for alkaidT)"); + run("setattr -unset mul2dsp", " (for alkaidT)"); + if (!no_opt) { + run("opt_expr -fine", " (for alkaidT)"); + run("wreduce", " (for alkaidT)"); + } + run("select -clear", " (for alkaidT)"); + // Comment out for further development + // run("rf_dsp", " (for + // alkaidT)"); + run("chtype -set $mul t:$__soft_mul", " (for alkaidT)"); + } + } + } + + if (check_label("coarse")) { + run("techmap -map +/cmp2lut.v -D LUT_WIDTH=5"); + if (!no_opt) { + run("opt_expr"); + run("opt_clean"); + } + run("alumacc"); + run("pmuxtree"); + if (!no_opt) { + run("opt -nodffe"); + } + run("memory -nomap"); + if (!no_opt) { + run("opt_clean"); + } + } + + if (check_label("map_bram", "(skip if -no_bram)") && + ((help_mode || family == ALKDT_DNAME) && inferBram)) { + if (help_mode || family == ALKDT_DNAME) { + run("memory_bram -rules " + lib_path + family + "/bram.txt"); + } + /* TODO: Add bram initilization support */ + run("techmap -map " + lib_path + family + "/bram_map.v"); + } + if (check_label("map_ffram")) { + if (!no_opt) { + run("opt -fast -mux_undef -undriven -fine -nodffe"); + } + run("memory_map"); + if (!no_opt) { + run("opt -undriven -fine -nodffe"); + } + } + + if (check_label("map_gates")) { + if (help_mode || + (inferAdder && (family == ALKDL_DNAME || family == ALKDT_DNAME || + family == ALKDC_DNAME))) { + run("techmap -map +/techmap.v -map " + lib_path + family + + "/arith_map.v", + "(unless -no_adder)"); + } else { + run("techmap"); + } + if (!no_opt) { + run("opt -fast -nodffe"); + run("opt_expr"); + run("opt_merge"); + run("opt_clean"); + run("opt -nodffe"); + } + } + + if (check_label("map_ffs")) { + run("memory"); + /* TODO: Support shift-register mapping */ + /* Run 2 times dff mapping incase anything missing */ + run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ " + "01"); + run("techmap -map " + lib_path + family + "/dff_map.v"); + run("dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ " + "01"); + run("techmap -map " + lib_path + family + "/dff_map.v"); + run("opt_expr -mux_undef"); + run("simplemap"); + run("opt_expr"); + if (!no_opt) { + run("opt_merge"); + run("opt_dff -nodffe"); + run("opt_clean"); + run("opt -nodffe"); + } + } + + if (check_label("map_luts")) { + run("abc -lut " + std::to_string(max_lut_size)); + /* Map dff and adder again since ABC may generate new gates */ + run("techmap -map " + lib_path + family + "/dff_map.v"); + run("techmap -map " + lib_path + family + "/arith_map.v"); + } + + if (check_label("check")) { + run("autoname"); + run("hierarchy -check"); + run("stat"); + run("check -noinit"); + } + + if (check_label("finalize")) { + if (!no_opt) { + run("opt_clean -purge"); + } + run("check"); + } + + if (check_label("insert_clock_buffer", "(if -insert_clock_buffer)")) { + if (insert_clock_buffer) { + run(stringf("insert_clock_buffer -top %s -cell_map_file %s", + top_opt.c_str(), cell_map_file.c_str())); + } + } + + if (check_label("blif", "(if -blif)")) { + if (help_mode || !blif_file.empty()) { + run(stringf("write_blif -param %s ", + help_mode ? "" : blif_file.c_str())); + } + } + + if (check_label("verilog", "(if -verilog)")) { + if (help_mode || !verilog_file.empty()) { + run("write_verilog -noattr -nohex " + + (help_mode ? "" : verilog_file)); + } + } + + if (check_label("save_block_diagram", "(if -save_block_diagram)")) { + if (!block_diagram_file.empty()) { + size_t dot_pos = block_diagram_file.find_last_of('.'); + std::string ext, prefix; + if (dot_pos != std::string::npos && + dot_pos + 1 < block_diagram_file.length()) { + ext = block_diagram_file.substr(dot_pos + 1); + prefix = block_diagram_file.substr(0, dot_pos); + } else { + ext = "dot"; + prefix = block_diagram_file; + } + if (ext != "dot" && ext != "png" && ext != "svg" && ext != "eps" && + ext != "pdf") { + log_cmd_error("Unsupported block diagram file format: %s. Supported " + "formats: dot, png, svg, eps, pdf\n", + ext.c_str()); + return; + } + run(stringf("show -format %s -prefix %s", ext.c_str(), prefix.c_str())); + } else { + run("show -format dot"); + } + } + } + +} SynthRapidFlexPass; + +PRIVATE_NAMESPACE_END diff --git a/techlibs/rapidflex/util/pcnt_cell_sim_gen.py b/techlibs/rapidflex/util/pcnt_cell_sim_gen.py new file mode 100644 index 000000000..85b7e6922 --- /dev/null +++ b/techlibs/rapidflex/util/pcnt_cell_sim_gen.py @@ -0,0 +1,142 @@ +##################################################################### +# A script to generate cell sim for pcounters +##################################################################### +import os +from os.path import dirname, abspath +import argparse +import logging +import csv +import pcounter_ip_template_generator + +##################################################################### +# Error codes +##################################################################### +error_codes = {"SUCCESS": 0, "ERROR": 1, "FILE_ERROR": 3} + +##################################################################### +# Initialize logger +##################################################################### +logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO) + + +def generate_file_header(f0): + f0.write("//-------------------------------------------------\n") + f0.write("// IMPORTANT: This file is auto generated!!! DO NOT MODIFY BY HAND!!!\n") + f0.write("//-------------------------------------------------\n") + f0.write("// Pcounter Primitives\n") + f0.write("// Naming convention:\n") + f0.write( + "// pcounter_clk_rst_\n" + ) + f0.write( + "// size: [N | ] ranges from 0 to 31, representing the number of bits. N is a parameterized design, which is supposed not be exposed to users\n" + ) + f0.write("// trigger_type: [p|n] denotes [rising edge (posedge) | falling edge (negedge) ]\n") + f0.write("// reset_type: [a|s] denotes [ asynchronous | synchronous ]\n") + f0.write("// reset_polarity: [p|n] denotes [ active-high | active-low ]\n") + f0.write( + "// event_function : [ load | add | sub | sr | sl ] denotes [ load | add | substract | shift right | shift left ] on the data_i values\n" + ) + + +def generate_pcounter_ips(fpath): + pcnt_ip_tmpl_gen = pcounter_ip_template_generator.PcounterIpTemplateGenerator() + cnt = 0 + with open(fpath, "w") as cell_sim_fh: + generate_file_header(cell_sim_fh) + for clk_type in pcnt_ip_tmpl_gen.clock_types(): + for rst_type in pcnt_ip_tmpl_gen.reset_types(): + for rst_polar in pcnt_ip_tmpl_gen.reset_polarities(): + for event_type in pcnt_ip_tmpl_gen.event_types(): + logging.info( + f"Generating IPs: {pcnt_ip_tmpl_gen.ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..." + ) + logging.debug( + f"Generating IP template: {pcnt_ip_tmpl_gen.ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..." + ) + pcnt_ip_tmpl_gen.write_ip_template( + cell_sim_fh, clk_type, rst_type, rst_polar, event_type + ) + logging.debug(f"Done") + cnt += 1 + # Generate full-size (32-bit) version + d_size = pcnt_ip_tmpl_gen.max_data_size() + logging.debug( + f"Generating full-sized counter IP: {pcnt_ip_tmpl_gen.ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..." + ) + pcnt_ip_tmpl_gen.write_ip( + cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size + ) + logging.debug(f"Done") + cnt += 1 + # Generate half-size (16-bit) version + d_size = int(pcnt_ip_tmpl_gen.max_data_size() / 2) + logging.debug( + f"Generating half-sized counter IP: {pcnt_ip_tmpl_gen.ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..." + ) + pcnt_ip_tmpl_gen.write_ip( + cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size + ) + logging.debug(f"Done") + cnt += 1 + # Generate CCB + logging.info( + f"Generating ccb-related IPs: {pcnt_ip_tmpl_gen.ccb_ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..." + ) + logging.debug( + f"Generating ccb-related IP template: {pcnt_ip_tmpl_gen.ccb_ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..." + ) + pcnt_ip_tmpl_gen.write_ccb_ip_template( + cell_sim_fh, clk_type, rst_type, rst_polar, event_type + ) + logging.debug(f"Done") + cnt += 1 + d_size = pcnt_ip_tmpl_gen.max_data_size() + logging.debug( + f"Generating ccb-related full-sized IP: {pcnt_ip_tmpl_gen.ccb_ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..." + ) + pcnt_ip_tmpl_gen.write_ccb_ip( + cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size + ) + logging.debug(f"Done") + cnt += 1 + # Generate half-size (16-bit) version + d_size = int(pcnt_ip_tmpl_gen.max_data_size() / 2) + logging.debug( + f"Generating ccb-related half-sized IP: {pcnt_ip_tmpl_gen.ccb_ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..." + ) + pcnt_ip_tmpl_gen.write_ccb_ip( + cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size + ) + logging.debug(f"Done") + cnt += 1 + logging.info(f"Done") + + logging.info(f"Generated {cnt} IPs") + + return 0 + + +##################################################################### +# Main function +##################################################################### +if __name__ == "__main__": + # Execute when the module is not initialized from an import statement + + # Parse the options and apply sanity checks + parser = argparse.ArgumentParser(description="Generate cell sim Verilog for Pcounter") + parser.add_argument( + "--file", + required=True, + default="cell_sim_pcnt.v", + help="Path to the .v file that contains pcounter IPs", + ) + args = parser.parse_args() + + num_error = generate_pcounter_ips(args.file) + if num_error == 0: + logging.info("Generation succeed") + exit(error_codes["SUCCESS"]) + else: + logging.error("Generation failed in " + str(num_error) + " errors!") + exit(error_codes["ERROR"]) diff --git a/techlibs/rapidflex/util/pcounter_ip_template_generator.py b/techlibs/rapidflex/util/pcounter_ip_template_generator.py new file mode 100644 index 000000000..d2fe8009f --- /dev/null +++ b/techlibs/rapidflex/util/pcounter_ip_template_generator.py @@ -0,0 +1,482 @@ +import time +import logging +import yaml +import os +import re +import subprocess +from datetime import timedelta +from datetime import datetime +import threading +import csv + +# Constants +CLK_TYPE_RISE = "RISING" +CLK_TYPE_FALL = "FALLING" +RST_TYPE_SYNC = "SYNCHRONOUS" +RST_TYPE_ASYNC = "ASYNCHRONOUS" +RST_POLARITY_L = "ACTIVE-LOW" +RST_POLARITY_H = "ACTIVE-HIGH" +EVENT_TYPE_LOAD = "LOAD" +EVENT_TYPE_ADD = "ADD" +EVENT_TYPE_SUB = "SUBTRACT" +EVENT_TYPE_SR = "SHIFT-RIGHT" +EVENT_TYPE_SL = "SHIFT-LEFT" + + +# Class of an mini pin table +class PcounterIpTemplateGenerator: + def __init__(self): + # Constants + self.__CLK_TYPES_ = [CLK_TYPE_RISE, CLK_TYPE_FALL] + self.__RST_TYPES_ = [RST_TYPE_SYNC, RST_TYPE_ASYNC] + self.__RST_POLARITIES_ = [RST_POLARITY_L, RST_POLARITY_H] + self.__EVENT_TYPES_ = [ + EVENT_TYPE_LOAD, + EVENT_TYPE_ADD, + EVENT_TYPE_SUB, + EVENT_TYPE_SR, + EVENT_TYPE_SL, + ] + self.__MAX_DATA_SIZE_ = 32 + self.__CCB_POSTFIX_ = "_ccb" + # Internal switches + self.__include_q_ = False + + # Create a new row + def clock_types(self): + return self.__CLK_TYPES_ + + def reset_types(self): + return self.__RST_TYPES_ + + def reset_polarities(self): + return self.__RST_POLARITIES_ + + def event_types(self): + return self.__EVENT_TYPES_ + + def data_sizes(self): + return range(1, self.__MAX_DATA_SIZE_ + 1) + + def max_data_size(self): + return self.__MAX_DATA_SIZE_ + + def __verilog_clock_edge(self, edge_type): + if edge_type == CLK_TYPE_RISE: + return "posedge" + elif edge_type == CLK_TYPE_FALL: + return "negedge" + else: + raise Exception(f"Invalid clock type '{edge_type}'. Expect {self.__CLK_TYPES_}\n") + + def __verilog_reset_edge(self, edge_type): + if edge_type == RST_POLARITY_H: + return "posedge" + elif edge_type == RST_POLARITY_L: + return "negedge" + else: + raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_POLARITIES_}\n") + + def __verilog_reset_polarity(self, polarity_type): + if polarity_type == RST_POLARITY_L: + return "~" + elif polarity_type == RST_POLARITY_H: + return "" + else: + raise Exception( + f"Invalid reset type '{polarity_type}'. Expect {self.__RST_POLARITIES}\n" + ) + + def __verilog_event_op_ccb(self, event_type): + if event_type == EVENT_TYPE_LOAD: + return "ccb_load_val_i" + elif event_type == EVENT_TYPE_ADD: + return "q_o + ccb_load_val_i" + elif event_type == EVENT_TYPE_SUB: + return "q_o - ccb_load_val_i" + elif event_type == EVENT_TYPE_SL: + return "q_o << ccb_load_val_i" + elif event_type == EVENT_TYPE_SR: + return "q_o >> ccb_load_val_i" + else: + raise Exception(f"Invalid event type '{event_type}'. Expect {self.__EVENT_TYPES_}\n") + + def __verilog_event_op(self, event_type): + if event_type == EVENT_TYPE_LOAD: + return "LOAD_VAL" + elif event_type == EVENT_TYPE_ADD: + return "q_o + LOAD_VAL" + elif event_type == EVENT_TYPE_SUB: + return "q_o - LOAD_VAL" + elif event_type == EVENT_TYPE_SL: + return "q_o << LOAD_VAL" + elif event_type == EVENT_TYPE_SR: + return "q_o >> LOAD_VAL" + else: + raise Exception(f"Invalid event type '{event_type}'. Expect {self.__EVENT_TYPES_}\n") + + def __clock_type_str(self, edge_type): + if edge_type == CLK_TYPE_RISE: + return "clkp" + elif edge_type == CLK_TYPE_FALL: + return "clkn" + else: + raise Exception(f"Invalid clock type '{edge_type}'. Expect {self.__CLK_TYPES_}\n") + + def __reset_type_str(self, edge_type, polarity_type): + ret = "" + if edge_type == RST_TYPE_ASYNC: + ret = "arst" + elif edge_type == RST_TYPE_SYNC: + ret = "srst" + else: + raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_TYPES_}\n") + + if polarity_type == RST_POLARITY_L: + ret += "n" + elif polarity_type == RST_POLARITY_H: + ret += "p" + else: + raise Exception( + f"Invalid reset type '{polarity_type}'. Expect {self.__RST_POLARITIES}\n" + ) + + return ret + + def __event_type_str(self, event_type): + if event_type == EVENT_TYPE_LOAD: + return "load" + elif event_type == EVENT_TYPE_ADD: + return "add" + elif event_type == EVENT_TYPE_SUB: + return "sub" + elif event_type == EVENT_TYPE_SL: + return "sl" + elif event_type == EVENT_TYPE_SR: + return "sr" + else: + raise Exception(f"Invalid event type '{event_type}'. Expect {self.__EVENT_TYPES_}\n") + + def ccb_ip_template_name(self, c_type, r_type, r_polar, e_type): + return ( + "pcounterN_" + + self.__clock_type_str(c_type) + + "_" + + self.__reset_type_str(r_type, r_polar) + + "_" + + self.__event_type_str(e_type) + + self.__CCB_POSTFIX_ + ) + + def ip_template_name(self, c_type, r_type, r_polar, e_type): + return ( + "pcounterN_" + + self.__clock_type_str(c_type) + + "_" + + self.__reset_type_str(r_type, r_polar) + + "_" + + self.__event_type_str(e_type) + ) + + def ip_name(self, c_type, r_type, r_polar, e_type, d_size): + return ( + "pcounter" + + str(d_size) + + "_" + + self.__clock_type_str(c_type) + + "_" + + self.__reset_type_str(r_type, r_polar) + + "_" + + self.__event_type_str(e_type) + ) + + def ccb_ip_name(self, c_type, r_type, r_polar, e_type, d_size): + return ( + "pcounter" + + str(d_size) + + "_" + + self.__clock_type_str(c_type) + + "_" + + self.__reset_type_str(r_type, r_polar) + + "_" + + self.__event_type_str(e_type) + + self.__CCB_POSTFIX_ + ) + + def write_ccb_ip_template(self, f0, c_type, r_type, r_polar, e_type): + f0.write("//-------------------------------------------------\n\n") + f0.write( + "// Template of Programmable counter to be counting up or down as well as paused\n\n" + ) + f0.write(f"// triggered by {c_type.lower()} edge clock\n\n") + f0.write(f"// with {r_type.lower()} {r_polar.lower()} reset\n\n") + f0.write(f"// Capable of {e_type.lower()} values from inputs\n\n") + f0.write("`default_nettype none\n\n") + f0.write(f"module {self.ccb_ip_template_name(c_type, r_type, r_polar, e_type)} #(\n") + f0.write(f" parameter integer DATA_WIDTH = {self.__MAX_DATA_SIZE_}\n") + f0.write(")(\n") + f0.write(" input clk_i,\n") + f0.write(" input rst_i,\n") + f0.write(" input up_down_i,\n") + f0.write(" input event_i,\n") + f0.write(" input enable_i,\n") + f0.write(" input [0 : DATA_WIDTH - 1] ccb_match0_ref_i,\n") + f0.write(" input [0 : DATA_WIDTH - 1] ccb_match1_ref_i,\n") + f0.write(" input [0 : DATA_WIDTH - 1] ccb_load_val_i,\n") + f0.write(" output match0_o,\n") + f0.write(" output match1_o,\n") + f0.write(" output zero_o,\n") + f0.write(" output [0 : DATA_WIDTH - 1] q_o\n") + f0.write(");\n") + f0.write(" reg [0 : DATA_WIDTH - 1] q_o;\n") + + if r_type == RST_TYPE_ASYNC: + f0.write( + f" always@({self.__verilog_clock_edge(c_type)} clk_i or {self.__verilog_reset_edge(r_polar)} rst_i) \n" + ) + elif r_type == RST_TYPE_SYNC: + f0.write(f" always@({self.__verilog_clock_edge(c_type)} clk_i) \n") + else: + raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_TYPES_}\n") + + f0.write(" begin\n") + f0.write( + f" if ({self.__verilog_reset_polarity(r_polar)}rst_i) //Set Counter to Zero\n" + ) + f0.write(" q_o <= 0;\n") + f0.write(" else if(event_i)\n") + f0.write(f" q_o <= {self.__verilog_event_op_ccb(e_type)};\n") + f0.write(" else if (~enable_i)\n") + f0.write(" q_o <= q_o; // pause\n") + f0.write(" else if(up_down_i) //count down\n") + f0.write(" q_o <= q_o - 1;\n") + f0.write(" else //count up\n") + f0.write(" q_o <= q_o + 1;\n") + f0.write(" end\n") + f0.write(" assign zero_o = (q_o == 0) ? 1 : 0;\n") + f0.write(" assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0;\n") + f0.write(" assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0;\n") + f0.write("endmodule\n") + f0.write("`default_nettype wire\n") + + def write_ip_template(self, f0, c_type, r_type, r_polar, e_type): + f0.write("//-------------------------------------------------\n\n") + f0.write( + "// Template of Programmable counter to be counting up or down as well as paused\n\n" + ) + f0.write(f"// triggered by {c_type.lower()} edge clock\n\n") + f0.write(f"// with {r_type.lower()} {r_polar.lower()} reset\n\n") + f0.write(f"// Capable of {e_type.lower()} values from inputs\n\n") + f0.write("`default_nettype none\n\n") + f0.write(f"module {self.ip_template_name(c_type, r_type, r_polar, e_type)} #(\n") + f0.write(f" parameter integer DATA_WIDTH = {self.__MAX_DATA_SIZE_},\n") + f0.write(" parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}},\n") + f0.write(" parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}},\n") + f0.write(" parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}}\n") + f0.write(")(\n") + f0.write(" input clk_i,\n") + f0.write(" input rst_i,\n") + f0.write(" input up_down_i,\n") + f0.write(" input event_i,\n") + f0.write(" input enable_i,\n") + f0.write(" output match0_o,\n") + f0.write(" output match1_o,\n") + f0.write(" output zero_o") + if self.__include_q_: + f0.write(",\n") + f0.write(" output [0 : DATA_WIDTH - 1] q_o\n") + f0.write(");\n") + f0.write(" reg [0 : DATA_WIDTH - 1] q_o;\n") + + if r_type == RST_TYPE_ASYNC: + f0.write( + f" always@({self.__verilog_clock_edge(c_type)} clk_i or {self.__verilog_reset_edge(r_polar)} rst_i) \n" + ) + elif r_type == RST_TYPE_SYNC: + f0.write(f" always@({self.__verilog_clock_edge(c_type)} clk_i) \n") + else: + raise Exception(f"Invalid reset type '{edge_type}'. Expect {self.__RST_TYPES_}\n") + + f0.write(" begin\n") + f0.write( + f" if ({self.__verilog_reset_polarity(r_polar)}rst_i) //Set Counter to Zero\n" + ) + f0.write(" q_o <= 0;\n") + f0.write(" else if(event_i)\n") + f0.write(f" q_o <= {self.__verilog_event_op(e_type)};\n") + f0.write(" else if (~enable_i)\n") + f0.write(" q_o <= q_o; // pause\n") + f0.write(" else if(up_down_i) //count down\n") + f0.write(" q_o <= q_o - 1;\n") + f0.write(" else //count up\n") + f0.write(" q_o <= q_o + 1;\n") + f0.write(" end\n") + f0.write(" assign zero_o = (q_o == 0) ? 1 : 0;\n") + f0.write(" assign match0_o = (q_o == MATCH0_REF) ? 1 : 0;\n") + f0.write(" assign match1_o = (q_o == MATCH1_REF) ? 1 : 0;\n") + f0.write("endmodule\n") + f0.write("`default_nettype wire\n") + + def write_ccb_ip(self, f0, c_type, r_type, r_polar, e_type, d_size, require_padding=False): + d_msb = d_size - 1 + f0.write("`default_nettype none\n\n") + f0.write(f"module {self.ccb_ip_name(c_type, r_type, r_polar, e_type, d_size)} # (\n") + f0.write(" // Location constraints\n") + f0.write(" parameter FPGA_LOC_X = 0,\n") + f0.write(" parameter FPGA_LOC_Y = 0,\n") + f0.write(" parameter FPGA_LOC_Z = 0)(\n") + f0.write(" input clk_i,\n") + f0.write(" input rst_i,\n") + f0.write(" input up_down_i,\n") + f0.write(" input event_i,\n") + f0.write(" input enable_i,\n") + f0.write(f" input [0 : {d_msb}] ccb_match0_ref_i,\n") + f0.write(f" input [0 : {d_msb}] ccb_match1_ref_i,\n") + f0.write(f" input [0 : {d_msb}] ccb_load_val_i,\n") + f0.write(" output match0_o,\n") + f0.write(" output match1_o,\n") + f0.write(" output zero_o,\n") + f0.write(f" output [0 : {d_msb}] q_o\n") + f0.write(");\n") + + # Local wire + padding_size = self.__MAX_DATA_SIZE_ - d_size + # Padding + # q_padding_str = "q_o" + # if require_padding: + # if padding_size: + # q_padding_str = "{ q_o, {" + str(padding_size) + "{1'b0}} }" + # f0.write(f"wire [0: {self.__MAX_DATA_SIZE_ - 1}] q_wire;\n") + # f0.write(f"assign q_wire = {q_padding_str};\n") + # else: + # f0.write(f"wire [0: {d_size - 1}] q_wire;\n") + # f0.write(f"assign q_wire = q_o;\n") + + f0.write(f" {self.ccb_ip_template_name(c_type, r_type, r_polar, e_type)} #(\n") + if require_padding: + f0.write(f" .DATA_WIDTH({self.__MAX_DATA_SIZE_})\n") + else: + f0.write(f" .DATA_WIDTH({d_size})\n") + + load_val_padding_str = "ccb_load_val_i" + if require_padding: + if padding_size: + load_val_padding_str = "{ ccb_load_val_i, {" + str(padding_size) + "{1'b0}} }" + + match0_padding_str = "ccb_match0_ref_i" + if require_padding: + if padding_size: + match0_padding_str = "{ ccb_match0_ref_i, {" + str(padding_size) + "{1'b0}} }" + + match1_padding_str = "ccb_match1_ref_i" + if require_padding: + if padding_size: + match1_padding_str = "{ ccb_match1_ref_i, {" + str(padding_size) + "{1'b0}} }" + + f0.write(" ) core (\n") + f0.write(" .clk_i(clk_i),\n") + f0.write(" .rst_i(rst_i),\n") + f0.write(" .up_down_i(up_down_i),\n") + f0.write(" .event_i(event_i),\n") + f0.write(" .enable_i(enable_i),\n") + f0.write(f" .ccb_load_val_i({load_val_padding_str}),\n") + f0.write(f" .ccb_match0_ref_i({match0_padding_str}),\n") + f0.write(f" .ccb_match1_ref_i({match1_padding_str}),\n") + f0.write(" .match0_o(match0_o),\n") + f0.write(" .match1_o(match1_o),\n") + f0.write(" .zero_o(zero_o),\n") + f0.write(f" .q_o(q_o)\n") + + f0.write(" );\n") + f0.write("endmodule\n") + f0.write("`default_nettype wire\n") + + def write_ip(self, f0, c_type, r_type, r_polar, e_type, d_size, require_padding=False): + d_msb = d_size - 1 + f0.write("`default_nettype none\n\n") + f0.write(f"module {self.ip_name(c_type, r_type, r_polar, e_type, d_size)} #(\n") + f0.write(" // Location constraints\n") + f0.write(" parameter FPGA_LOC_X = 0,\n") + f0.write(" parameter FPGA_LOC_Y = 0,\n") + f0.write(" parameter FPGA_LOC_Z = 0,\n") + f0.write(" parameter [0 : " + str(d_msb) + "] LOAD_VAL = {" + str(d_size) + "{1'b0}},\n") + f0.write(" parameter [0 : " + str(d_msb) + "] MATCH0_REF = {" + str(d_size) + "{1'b0}},\n") + f0.write(" parameter [0 : " + str(d_msb) + "] MATCH1_REF = {" + str(d_size) + "{1'b0}}\n") + f0.write(")(\n") + f0.write(" input clk_i,\n") + f0.write(" input rst_i,\n") + f0.write(" input up_down_i,\n") + f0.write(" input event_i,\n") + f0.write(" input enable_i,\n") + f0.write(" output match0_o,\n") + f0.write(" output match1_o,\n") + f0.write(" output zero_o") + + if self.__include_q_: + f0.write(",\n") + f0.write(f" output [0 : {d_msb}] q_o\n") + else: + f0.write("\n") + + f0.write(");\n") + + # Local wire + padding_size = self.__MAX_DATA_SIZE_ - d_size + # if self.__include_q_: + # q_padding_str = "q_o" + # if require_padding: + # if padding_size: + # q_padding_str = "{ q_o, {" + str(padding_size) + "{1'b0}} }" + # f0.write(f"wire [0: {self.__MAX_DATA_SIZE_ - 1}] q_wire;\n") + # f0.write(f"assign q_wire = {q_padding_str};\n") + # else: + # f0.write(f"wire [0: {d_size - 1}] q_wire;\n") + # f0.write(f"assign q_wire = {q_padding_str};\n") + + f0.write(f" {self.ip_template_name(c_type, r_type, r_polar, e_type)} #(\n") + if require_padding: + f0.write(f" .DATA_WIDTH({self.__MAX_DATA_SIZE_})\n") + else: + f0.write(f" .DATA_WIDTH({d_size}),\n") + + load_val_padding_str = "LOAD_VAL" + if require_padding: + if padding_size: + load_val_padding_str = "{ LOAD_VAL, {" + str(padding_size) + "{1'b0}} }" + f0.write(f" .LOAD_VAL({load_val_padding_str}),\n") + + match0_padding_str = "MATCH0_REF" + if require_padding: + if padding_size: + match0_padding_str = "{ MATCH0_REF, {" + str(padding_size) + "{1'b0}} }" + f0.write(f" .MATCH0_REF({match0_padding_str}),\n") + + match1_padding_str = "MATCH1_REF" + if require_padding: + if padding_size: + match1_padding_str = "{ MATCH1_REF, {" + str(padding_size) + "{1'b0}} }" + f0.write(f" .MATCH1_REF({match1_padding_str})\n") + + f0.write(" ) core (\n") + f0.write(" .clk_i(clk_i),\n") + f0.write(" .rst_i(rst_i),\n") + f0.write(" .up_down_i(up_down_i),\n") + f0.write(" .event_i(event_i),\n") + f0.write(" .enable_i(enable_i),\n") + f0.write(" .match0_o(match0_o),\n") + f0.write(" .match1_o(match1_o),\n") + f0.write(" .zero_o(zero_o)") + + if self.__include_q_: + f0.write(",\n") + f0.write(f" .q_o(q_o)\n") + else: + f0.write("\n") + + f0.write(" );\n") + f0.write("endmodule\n") + f0.write("`default_nettype wire\n") + + # Clear all the data + def clear(self): + self.__init__() From ca3486cf67559d5a3e7eb6d2cade291d3ff1af0c Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 May 2026 17:48:40 -0700 Subject: [PATCH 04/15] [core] debug --- techlibs/rapidflex/Makefile.inc | 2 +- techlibs/rapidflex/alkaidC/cell_sim_pcnt.v | 9691 -------------------- 2 files changed, 1 insertion(+), 9692 deletions(-) delete mode 100644 techlibs/rapidflex/alkaidC/cell_sim_pcnt.v diff --git a/techlibs/rapidflex/Makefile.inc b/techlibs/rapidflex/Makefile.inc index 895a72bb0..d2f71ff2a 100644 --- a/techlibs/rapidflex/Makefile.inc +++ b/techlibs/rapidflex/Makefile.inc @@ -2,7 +2,7 @@ techlibs/rapidflex/alkaidC/cell_sim_pcnt.v: techlibs/rapidflex/util/pcnt_cell_sim_gen.py $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ --file $@ -CXXFLAGS += -Itechlibs/rapidflex/src/pugixml.hpp +CXXFLAGS += -Itechlibs/rapidflex/src/ OBJS += techlibs/rapidflex/src/pugixml.o OBJS += techlibs/rapidflex/src/synth_rapidflex.o OBJS += techlibs/rapidflex/src/clock_buffer_cmd.o diff --git a/techlibs/rapidflex/alkaidC/cell_sim_pcnt.v b/techlibs/rapidflex/alkaidC/cell_sim_pcnt.v deleted file mode 100644 index 1525c24c7..000000000 --- a/techlibs/rapidflex/alkaidC/cell_sim_pcnt.v +++ /dev/null @@ -1,9691 +0,0 @@ -//------------------------------------------------- -// IMPORTANT: This file is auto generated!!! DO NOT MODIFY BY HAND!!! -//------------------------------------------------- -// Pcounter Primitives -// Naming convention: -// pcounter_clk_rst_ -// size: [N | ] ranges from 0 to 31, representing the number of bits. N is a parameterized design, which is supposed not be exposed to users -// trigger_type: [p|n] denotes [rising edge (posedge) | falling edge (negedge) ] -// reset_type: [a|s] denotes [ asynchronous | synchronous ] -// reset_polarity: [p|n] denotes [ active-high | active-low ] -// event_function : [ load | add | sub | sr | sl ] denotes [ load | add | substract | shift right | shift left ] on the data_i values -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstn_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstn_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstn_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstn_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstn_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstn_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstn_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstn_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstn_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_srstn_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstn_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstn_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstp_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstp_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstp_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstp_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstp_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstp_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstp_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstp_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_srstp_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with synchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_srstp_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_srstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_srstp_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_srstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_srstp_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstn_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstn_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstn_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstn_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstn_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstn_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstn_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstn_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstn_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_arstn_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstn_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstn_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstp_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstp_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstp_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstp_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstp_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstp_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstp_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstp_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkp_arstp_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by rising edge clock - -// with asynchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkp_arstp_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(posedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkp_arstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkp_arstp_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkp_arstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkp_arstp_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstn_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstn_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstn_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstn_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstn_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstn_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstn_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstn_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstn_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_srstn_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstn_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstn_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstp_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstp_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstp_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstp_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstp_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstp_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstp_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstp_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_srstp_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with synchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_srstp_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_srstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_srstp_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_srstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_srstp_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstn_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstn_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstn_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstn_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstn_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstn_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstn_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstn_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstn_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-low reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_arstn_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or negedge rst_i) - begin - if (~rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstn_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstn_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstn_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_load #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_load #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_load #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_load #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of load values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_load_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstp_load_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_load_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstp_load_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_add #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_add #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_add #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_add #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of add values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_add_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o + ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstp_add_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_add_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstp_add_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_sub #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_sub #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_sub #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_sub #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of subtract values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_sub_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o - ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstp_sub_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_sub_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstp_sub_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_sr #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_sr #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_sr #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_sr #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of shift-right values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_sr_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o >> ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstp_sr_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_sr_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstp_sr_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_sl #( - parameter integer DATA_WIDTH = 32, - parameter [0 : DATA_WIDTH - 1] LOAD_VAL = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH0_REF = {DATA_WIDTH{1'b0}}, - parameter [0 : DATA_WIDTH - 1] MATCH1_REF = {DATA_WIDTH{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << LOAD_VAL; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == MATCH0_REF) ? 1 : 0; - assign match1_o = (q_o == MATCH1_REF) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 31] LOAD_VAL = {32{1'b0}}, - parameter [0 : 31] MATCH0_REF = {32{1'b0}}, - parameter [0 : 31] MATCH1_REF = {32{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_sl #( - .DATA_WIDTH(32), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_sl #( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0, - parameter [0 : 15] LOAD_VAL = {16{1'b0}}, - parameter [0 : 15] MATCH0_REF = {16{1'b0}}, - parameter [0 : 15] MATCH1_REF = {16{1'b0}} -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - output match0_o, - output match1_o, - output zero_o -); - pcounterN_clkn_arstp_sl #( - .DATA_WIDTH(16), - .LOAD_VAL(LOAD_VAL), - .MATCH0_REF(MATCH0_REF), - .MATCH1_REF(MATCH1_REF) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o) - ); -endmodule -`default_nettype wire -//------------------------------------------------- - -// Template of Programmable counter to be counting up or down as well as paused - -// triggered by falling edge clock - -// with asynchronous active-high reset - -// Capable of shift-left values from inputs - -`default_nettype none - -module pcounterN_clkn_arstp_sl_ccb #( - parameter integer DATA_WIDTH = 32 -)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : DATA_WIDTH - 1] ccb_match0_ref_i, - input [0 : DATA_WIDTH - 1] ccb_match1_ref_i, - input [0 : DATA_WIDTH - 1] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : DATA_WIDTH - 1] q_o -); - reg [0 : DATA_WIDTH - 1] q_o; - always@(negedge clk_i or posedge rst_i) - begin - if (rst_i) //Set Counter to Zero - q_o <= 0; - else if(event_i) - q_o <= q_o << ccb_load_val_i; - else if (~enable_i) - q_o <= q_o; // pause - else if(up_down_i) //count down - q_o <= q_o - 1; - else //count up - q_o <= q_o + 1; - end - assign zero_o = (q_o == 0) ? 1 : 0; - assign match0_o = (q_o == ccb_match0_ref_i) ? 1 : 0; - assign match1_o = (q_o == ccb_match1_ref_i) ? 1 : 0; -endmodule -`default_nettype wire -`default_nettype none - -module pcounter32_clkn_arstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 31] ccb_match0_ref_i, - input [0 : 31] ccb_match1_ref_i, - input [0 : 31] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 31] q_o -); - pcounterN_clkn_arstp_sl_ccb #( - .DATA_WIDTH(32) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire -`default_nettype none - -module pcounter16_clkn_arstp_sl_ccb # ( - // Location constraints - parameter FPGA_LOC_X = 0, - parameter FPGA_LOC_Y = 0, - parameter FPGA_LOC_Z = 0)( - input clk_i, - input rst_i, - input up_down_i, - input event_i, - input enable_i, - input [0 : 15] ccb_match0_ref_i, - input [0 : 15] ccb_match1_ref_i, - input [0 : 15] ccb_load_val_i, - output match0_o, - output match1_o, - output zero_o, - output [0 : 15] q_o -); - pcounterN_clkn_arstp_sl_ccb #( - .DATA_WIDTH(16) - ) core ( - .clk_i(clk_i), - .rst_i(rst_i), - .up_down_i(up_down_i), - .event_i(event_i), - .enable_i(enable_i), - .ccb_load_val_i(ccb_load_val_i), - .ccb_match0_ref_i(ccb_match0_ref_i), - .ccb_match1_ref_i(ccb_match1_ref_i), - .match0_o(match0_o), - .match1_o(match1_o), - .zero_o(zero_o), - .q_o(q_o) - ); -endmodule -`default_nettype wire From f4eec92605617a2fcd3ca638d50ce46c7637881b Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 May 2026 17:52:30 -0700 Subject: [PATCH 05/15] [core] add missing file --- techlibs/rapidflex/src/pugiconfig.hpp | 75 +++++++++++++++++++++++++++ 1 file changed, 75 insertions(+) create mode 100644 techlibs/rapidflex/src/pugiconfig.hpp diff --git a/techlibs/rapidflex/src/pugiconfig.hpp b/techlibs/rapidflex/src/pugiconfig.hpp new file mode 100644 index 000000000..e10565a6c --- /dev/null +++ b/techlibs/rapidflex/src/pugiconfig.hpp @@ -0,0 +1,75 @@ +/** + * pugixml parser - version 1.7 + * -------------------------------------------------------- + * Copyright (C) 2006-2015, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com) + * Report bugs and download new versions at http://pugixml.org/ + * + * This library is distributed under the MIT License. See notice at the end + * of this file. + * + * This work is based on the pugxml parser, which is: + * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net) + */ + +#ifndef HEADER_PUGICONFIG_HPP +#define HEADER_PUGICONFIG_HPP + +// Uncomment this to enable wchar_t mode +// #define PUGIXML_WCHAR_MODE + +// Uncomment this to enable compact mode +// #define PUGIXML_COMPACT + +// Uncomment this to disable XPath +// #define PUGIXML_NO_XPATH + +// Uncomment this to disable STL +// #define PUGIXML_NO_STL + +// Uncomment this to disable exceptions +// #define PUGIXML_NO_EXCEPTIONS + +// Set this to control attributes for public classes/functions, i.e.: +// #define PUGIXML_API __declspec(dllexport) // to export all public symbols +// from DLL #define PUGIXML_CLASS __declspec(dllimport) // to import all classes +// from DLL #define PUGIXML_FUNCTION __fastcall // to set calling conventions to +// all public functions to fastcall In absence of PUGIXML_CLASS/PUGIXML_FUNCTION +// definitions PUGIXML_API is used instead + +// Tune these constants to adjust memory-related behavior +// #define PUGIXML_MEMORY_PAGE_SIZE 32768 +// #define PUGIXML_MEMORY_OUTPUT_STACK 10240 +// #define PUGIXML_MEMORY_XPATH_PAGE_SIZE 4096 + +// Uncomment this to switch to header-only version +// #define PUGIXML_HEADER_ONLY + +// Uncomment this to enable long long support +// #define PUGIXML_HAS_LONG_LONG + +#endif + +/** + * Copyright (c) 2006-2015 Arseny Kapoulkine + * + * Permission is hereby granted, free of charge, to any person + * obtaining a copy of this software and associated documentation + * files (the "Software"), to deal in the Software without + * restriction, including without limitation the rights to use, + * copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following + * conditions: + * + * The above copyright notice and this permission notice shall be + * included in all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, + * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND + * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT + * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, + * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + */ From c98dddfe324390c1c53267d89cab7110a9873468 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 May 2026 17:53:42 -0700 Subject: [PATCH 06/15] [core] rename --- techlibs/rapidflex/src/{synth_rf_alkaid.cc => synth_rapidflex.cc} | 0 1 file changed, 0 insertions(+), 0 deletions(-) rename techlibs/rapidflex/src/{synth_rf_alkaid.cc => synth_rapidflex.cc} (100%) diff --git a/techlibs/rapidflex/src/synth_rf_alkaid.cc b/techlibs/rapidflex/src/synth_rapidflex.cc similarity index 100% rename from techlibs/rapidflex/src/synth_rf_alkaid.cc rename to techlibs/rapidflex/src/synth_rapidflex.cc From 75a2ff3ed8f8d463ba6ceac4abb35d8957e07cc0 Mon Sep 17 00:00:00 2001 From: tangxifan Date: Thu, 14 May 2026 17:57:12 -0700 Subject: [PATCH 07/15] [core] debug --- techlibs/rapidflex/src/clock_buffer_cmd.cc | 10 +++++----- techlibs/rapidflex/src/rf_dsp_mad.cc | 2 +- techlibs/rapidflex/src/rf_new_dsp.cc | 4 ++-- 3 files changed, 8 insertions(+), 8 deletions(-) diff --git a/techlibs/rapidflex/src/clock_buffer_cmd.cc b/techlibs/rapidflex/src/clock_buffer_cmd.cc index 2deb9ee04..253260522 100644 --- a/techlibs/rapidflex/src/clock_buffer_cmd.cc +++ b/techlibs/rapidflex/src/clock_buffer_cmd.cc @@ -104,9 +104,9 @@ struct InsertClockBuffer : public Pass { void rewire_subckt(RTLIL::Module *module, RTLIL::Cell *cell, RTLIL::IdString id_name, std::string C_input) { std::string C_output = C_input + "_ckbuf"; - if (!module->wire("\\" + C_output)) { - auto output_wire = module->addWire("\\" + C_output, 1); - } +// if (!module->wire("\\" + C_output)) { +// auto output_wire = module->addWire("\\" + C_output, 1); +// } /* connect new ckbuf to the subckt */ cell->unsetPort(id_name); // unsetPort("C") cell->setPort(id_name, module->wire("\\" + C_output)); @@ -186,7 +186,7 @@ struct InsertClockBuffer : public Pass { representing internally generated signals. When such a signal is found, it invokes rewire_subckt.*/ std::set - find_internal_clk_r_signal(RTLIL::Module *module, RTLIL::Design *design, + find_internal_clk_r_signal(RTLIL::Module *module, std::map &ckbuf_type) { std::set ckbuf_info; /*get input ports of the top module*/ @@ -528,7 +528,7 @@ struct InsertClockBuffer : public Pass { if (module->name == RTLIL::escape_id(top_module_name)) { std::map ckbuf_type; std::set ckbuf_info = - find_internal_clk_r_signal(module, design, ckbuf_type); + find_internal_clk_r_signal(module, ckbuf_type); /*insert ckbuf and rewire dff */ insert_ckbuf(module, ckbuf_info); diff --git a/techlibs/rapidflex/src/rf_dsp_mad.cc b/techlibs/rapidflex/src/rf_dsp_mad.cc index 1ccdf4a79..7f943eadb 100644 --- a/techlibs/rapidflex/src/rf_dsp_mad.cc +++ b/techlibs/rapidflex/src/rf_dsp_mad.cc @@ -4,7 +4,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#include "pmgen/rf_dsp_mad.h" +#include "rf_dsp_mad_pm.h" static void create_rf_mad_dsp(rf_dsp_mad_pm &pm) { auto &st = pm.st_rf_dsp_mad; diff --git a/techlibs/rapidflex/src/rf_new_dsp.cc b/techlibs/rapidflex/src/rf_new_dsp.cc index aa42742e2..50d11ec05 100644 --- a/techlibs/rapidflex/src/rf_new_dsp.cc +++ b/techlibs/rapidflex/src/rf_new_dsp.cc @@ -4,7 +4,7 @@ USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN -#include "pmgen/rf_new_dsp.h" +#include "rf_new_dsp_pm.h" void swapinput(RTLIL::SigSpec &sigA, RTLIL::SigSpec &sigB) { if (GetSize(sigA) < GetSize(sigB)) { @@ -438,4 +438,4 @@ struct RfNewDSP : public Pass { } } RfNewDsp; -PRIVATE_NAMESPACE_END \ No newline at end of file +PRIVATE_NAMESPACE_END From 3c5ba1337e5639748045dc0cf0ad5073334949ac Mon Sep 17 00:00:00 2001 From: treelin611 Date: Tue, 19 May 2026 14:30:31 +0800 Subject: [PATCH 08/15] mod according to code comment --- techlibs/rapidflex/Makefile.inc | 4 +- techlibs/rapidflex/alkaidC/.gitignore | 1 + techlibs/rapidflex/src/clock_buffer_cmd.cc | 46 +- techlibs/rapidflex/src/pugiconfig.hpp | 75 - techlibs/rapidflex/src/pugixml.cpp | 12313 ----------------- techlibs/rapidflex/src/pugixml.hpp | 1544 --- techlibs/rapidflex/util/pcnt_cell_sim_gen.py | 2 +- 7 files changed, 40 insertions(+), 13945 deletions(-) create mode 100644 techlibs/rapidflex/alkaidC/.gitignore delete mode 100644 techlibs/rapidflex/src/pugiconfig.hpp delete mode 100644 techlibs/rapidflex/src/pugixml.cpp delete mode 100644 techlibs/rapidflex/src/pugixml.hpp diff --git a/techlibs/rapidflex/Makefile.inc b/techlibs/rapidflex/Makefile.inc index d2f71ff2a..cc090bd33 100644 --- a/techlibs/rapidflex/Makefile.inc +++ b/techlibs/rapidflex/Makefile.inc @@ -1,9 +1,8 @@ -# cell lib generation +# cell lib generation techlibs/rapidflex/alkaidC/cell_sim_pcnt.v: techlibs/rapidflex/util/pcnt_cell_sim_gen.py $(P) mkdir -p $(dir $@) && $(PYTHON_EXECUTABLE) $^ --file $@ CXXFLAGS += -Itechlibs/rapidflex/src/ -OBJS += techlibs/rapidflex/src/pugixml.o OBJS += techlibs/rapidflex/src/synth_rapidflex.o OBJS += techlibs/rapidflex/src/clock_buffer_cmd.o @@ -26,7 +25,6 @@ $(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/ $(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_arith.v)) $(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_ccb.v)) $(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_ff.v)) -$(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_pcnt.v)) $(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim.v)) $(eval $(call add_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/dff_map.v)) $(eval $(call add_gen_share_file,share/rapidflex/alkaidC,techlibs/rapidflex/alkaidC/cell_sim_pcnt.v)) diff --git a/techlibs/rapidflex/alkaidC/.gitignore b/techlibs/rapidflex/alkaidC/.gitignore new file mode 100644 index 000000000..26149bb8e --- /dev/null +++ b/techlibs/rapidflex/alkaidC/.gitignore @@ -0,0 +1 @@ +/cell_sim_pcnt.v diff --git a/techlibs/rapidflex/src/clock_buffer_cmd.cc b/techlibs/rapidflex/src/clock_buffer_cmd.cc index 253260522..72536c2d8 100644 --- a/techlibs/rapidflex/src/clock_buffer_cmd.cc +++ b/techlibs/rapidflex/src/clock_buffer_cmd.cc @@ -1,4 +1,4 @@ -#include +#include #include #include #include @@ -10,7 +10,6 @@ #include "kernel/rtlil.h" #include "kernel/sigtools.h" #include "kernel/yosys.h" -#include "pugixml.hpp" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -223,12 +222,41 @@ struct InsertClockBuffer : public Pass { } } + static std::string xml_escape(const std::string &s) { + std::string out; + out.reserve(s.size()); + for (char c : s) { + switch (c) { + case '&': + out += "&"; + break; + case '"': + out += """; + break; + case '<': + out += "<"; + break; + case '>': + out += ">"; + break; + default: + out += c; + break; + } + } + return out; + } + /*This function is for generating cell map file*/ void generate_cell_map(const char *fname, const std::set &ckbuf_info, const std::map &ckbuf_type) { - pugi::xml_document out_xml; - pugi::xml_node root_node = out_xml.append_child("ckbuf_cell_map"); + FILE *f = fopen(fname, "w"); + if (f == nullptr) + log_error("Can't open file `%s` for writing.\n", fname); + + fprintf(f, "\n"); + fprintf(f, "\n"); for (const std::string &ckbuf : ckbuf_info) { std::string in = ckbuf; std::string out = ckbuf + "_ckbuf"; @@ -241,12 +269,12 @@ struct InsertClockBuffer : public Pass { log_error("No port type defined for ckbuf %s \n", out.c_str()); } - pugi::xml_node ckbuf_node = root_node.append_child("ckbuf"); - ckbuf_node.append_attribute("input_net") = in.c_str(); - ckbuf_node.append_attribute("cell") = out.c_str(); - ckbuf_node.append_attribute("type") = type.c_str(); + fprintf(f, " \n", + xml_escape(in).c_str(), xml_escape(out).c_str(), + xml_escape(type).c_str()); } - out_xml.save_file(fname); + fprintf(f, "\n"); + fclose(f); log("cell map is stored in file %s \n", fname); } void rewire_lut_primitive(RTLIL::Cell *cell, diff --git a/techlibs/rapidflex/src/pugiconfig.hpp b/techlibs/rapidflex/src/pugiconfig.hpp deleted file mode 100644 index e10565a6c..000000000 --- a/techlibs/rapidflex/src/pugiconfig.hpp +++ /dev/null @@ -1,75 +0,0 @@ -/** - * pugixml parser - version 1.7 - * -------------------------------------------------------- - * Copyright (C) 2006-2015, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com) - * Report bugs and download new versions at http://pugixml.org/ - * - * This library is distributed under the MIT License. See notice at the end - * of this file. - * - * This work is based on the pugxml parser, which is: - * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net) - */ - -#ifndef HEADER_PUGICONFIG_HPP -#define HEADER_PUGICONFIG_HPP - -// Uncomment this to enable wchar_t mode -// #define PUGIXML_WCHAR_MODE - -// Uncomment this to enable compact mode -// #define PUGIXML_COMPACT - -// Uncomment this to disable XPath -// #define PUGIXML_NO_XPATH - -// Uncomment this to disable STL -// #define PUGIXML_NO_STL - -// Uncomment this to disable exceptions -// #define PUGIXML_NO_EXCEPTIONS - -// Set this to control attributes for public classes/functions, i.e.: -// #define PUGIXML_API __declspec(dllexport) // to export all public symbols -// from DLL #define PUGIXML_CLASS __declspec(dllimport) // to import all classes -// from DLL #define PUGIXML_FUNCTION __fastcall // to set calling conventions to -// all public functions to fastcall In absence of PUGIXML_CLASS/PUGIXML_FUNCTION -// definitions PUGIXML_API is used instead - -// Tune these constants to adjust memory-related behavior -// #define PUGIXML_MEMORY_PAGE_SIZE 32768 -// #define PUGIXML_MEMORY_OUTPUT_STACK 10240 -// #define PUGIXML_MEMORY_XPATH_PAGE_SIZE 4096 - -// Uncomment this to switch to header-only version -// #define PUGIXML_HEADER_ONLY - -// Uncomment this to enable long long support -// #define PUGIXML_HAS_LONG_LONG - -#endif - -/** - * Copyright (c) 2006-2015 Arseny Kapoulkine - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ diff --git a/techlibs/rapidflex/src/pugixml.cpp b/techlibs/rapidflex/src/pugixml.cpp deleted file mode 100644 index 15cad0fd1..000000000 --- a/techlibs/rapidflex/src/pugixml.cpp +++ /dev/null @@ -1,12313 +0,0 @@ -/** - * pugixml parser - version 1.7 - * -------------------------------------------------------- - * Copyright (C) 2006-2015, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com) - * Report bugs and download new versions at http://pugixml.org/ - * - * This library is distributed under the MIT License. See notice at the end - * of this file. - * - * This work is based on the pugxml parser, which is: - * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net) - */ - -#ifndef SOURCE_PUGIXML_CPP -#define SOURCE_PUGIXML_CPP - -#include "pugixml.hpp" - -#include -#include -#include -#include -#include - -#ifdef PUGIXML_WCHAR_MODE -#include -#endif - -#ifndef PUGIXML_NO_XPATH -#include -#include -#ifdef PUGIXML_NO_EXCEPTIONS -#include -#endif -#endif - -#ifndef PUGIXML_NO_STL -#include -#include -#include -#endif - -// For placement new -#include - -#ifdef _MSC_VER -#pragma warning(push) -#pragma warning(disable : 4127) // conditional expression is constant -#pragma warning( \ - disable : 4324) // structure was padded due to __declspec(align()) -#pragma warning(disable : 4611) // interaction between '_setjmp' and C++ object - // destruction is non-portable -#pragma warning(disable : 4702) // unreachable code -#pragma warning(disable : 4996) // this function or variable may be unsafe -#pragma warning(disable : 4793) // function compiled as native: presence of - // '_setjmp' makes a function unmanaged -#endif - -#ifdef __INTEL_COMPILER -#pragma warning(disable : 177) // function was declared but never referenced -#pragma warning(disable : 279) // controlling expression is constant -#pragma warning(disable : 1478 1786) // function was declared "deprecated" -#pragma warning( \ - disable : 1684) // conversion from pointer to same-sized integral type -#endif - -#if defined(__BORLANDC__) && defined(PUGIXML_HEADER_ONLY) -#pragma warn - 8080 // symbol is declared but never used; disabling this inside - // push/pop bracket does not make the warning go away -#endif - -#ifdef __BORLANDC__ -#pragma option push -#pragma warn - 8008 // condition is always false -#pragma warn - 8066 // unreachable code -#endif - -#ifdef __SNC__ -// Using diag_push/diag_pop does not disable the warnings inside templates due -// to a compiler bug -#pragma diag_suppress = 178 // function was declared but never referenced -#pragma diag_suppress = 237 // controlling expression is constant -#endif - -// Inlining controls -#if defined(_MSC_VER) && _MSC_VER >= 1300 -#define PUGI__NO_INLINE __declspec(noinline) -#elif defined(__GNUC__) -#define PUGI__NO_INLINE __attribute__((noinline)) -#else -#define PUGI__NO_INLINE -#endif - -// Branch weight controls -#if defined(__GNUC__) -#define PUGI__UNLIKELY(cond) __builtin_expect(cond, 0) -#else -#define PUGI__UNLIKELY(cond) (cond) -#endif - -// Simple static assertion -#define PUGI__STATIC_ASSERT(cond) \ - { \ - static const char condition_failed[(cond) ? 1 : -1] = {0}; \ - (void)condition_failed[0]; \ - } - -// Digital Mars C++ bug workaround for passing char loaded from memory via stack -#ifdef __DMC__ -#define PUGI__DMC_VOLATILE volatile -#else -#define PUGI__DMC_VOLATILE -#endif - -// Borland C++ bug workaround for not defining ::memcpy depending on header -// include order (can't always use std::memcpy because some compilers don't have -// it at all) -#if defined(__BORLANDC__) && !defined(__MEM_H_USING_LIST) -using std::memcpy; -using std::memmove; -using std::memset; -#endif - -// In some environments MSVC is a compiler but the CRT lacks certain -// MSVC-specific features -#if defined(_MSC_VER) && !defined(__S3E__) -#define PUGI__MSVC_CRT_VERSION _MSC_VER -#endif - -#ifdef PUGIXML_HEADER_ONLY -#define PUGI__NS_BEGIN \ - namespace pugi { \ - namespace impl { -#define PUGI__NS_END \ - } \ - } -#define PUGI__FN inline -#define PUGI__FN_NO_INLINE inline -#else -#if defined(_MSC_VER) && \ - _MSC_VER < 1300 // MSVC6 seems to have an amusing bug with anonymous - // namespaces inside namespaces -#define PUGI__NS_BEGIN \ - namespace pugi { \ - namespace impl { -#define PUGI__NS_END \ - } \ - } -#else -#define PUGI__NS_BEGIN \ - namespace pugi { \ - namespace impl { \ - namespace { -#define PUGI__NS_END \ - } \ - } \ - } -#endif -#define PUGI__FN -#define PUGI__FN_NO_INLINE PUGI__NO_INLINE -#endif - -// uintptr_t -#if !defined(_MSC_VER) || _MSC_VER >= 1600 -#include -#else -namespace pugi { -#ifndef _UINTPTR_T_DEFINED -typedef size_t uintptr_t; -#endif - -typedef unsigned __int8 uint8_t; -typedef unsigned __int16 uint16_t; -typedef unsigned __int32 uint32_t; -} // namespace pugi -#endif - -// Memory allocation -PUGI__NS_BEGIN -PUGI__FN void *default_allocate(size_t size) { return malloc(size); } - -PUGI__FN void default_deallocate(void *ptr) { free(ptr); } - -template struct xml_memory_management_function_storage { - static allocation_function allocate; - static deallocation_function deallocate; -}; - -// Global allocation functions are stored in class statics so that in header -// mode linker deduplicates them Without a template<> we'll get multiple -// definitions of the same static -template -allocation_function xml_memory_management_function_storage::allocate = - default_allocate; -template -deallocation_function xml_memory_management_function_storage::deallocate = - default_deallocate; - -typedef xml_memory_management_function_storage xml_memory; -PUGI__NS_END - -// String utilities -PUGI__NS_BEGIN -// Get string length -PUGI__FN size_t strlength(const char_t *s) { - assert(s); - -#ifdef PUGIXML_WCHAR_MODE - return wcslen(s); -#else - return strlen(s); -#endif -} - -// Compare two strings -PUGI__FN bool strequal(const char_t *src, const char_t *dst) { - assert(src && dst); - -#ifdef PUGIXML_WCHAR_MODE - return wcscmp(src, dst) == 0; -#else - return strcmp(src, dst) == 0; -#endif -} - -// Compare lhs with [rhs_begin, rhs_end) -PUGI__FN bool strequalrange(const char_t *lhs, const char_t *rhs, - size_t count) { - for (size_t i = 0; i < count; ++i) - if (lhs[i] != rhs[i]) - return false; - - return lhs[count] == 0; -} - -// Get length of wide string, even if CRT lacks wide character support -PUGI__FN size_t strlength_wide(const wchar_t *s) { - assert(s); - -#ifdef PUGIXML_WCHAR_MODE - return wcslen(s); -#else - const wchar_t *end = s; - while (*end) - end++; - return static_cast(end - s); -#endif -} -PUGI__NS_END - -// auto_ptr-like object for exception recovery -PUGI__NS_BEGIN -template struct auto_deleter { - T *data; - D deleter; - - auto_deleter(T *data_, D deleter_) : data(data_), deleter(deleter_) {} - - ~auto_deleter() { - if (data) - deleter(data); - } - - T *release() { - T *result = data; - data = 0; - return result; - } -}; -PUGI__NS_END - -#ifdef PUGIXML_COMPACT -PUGI__NS_BEGIN -class compact_hash_table { -public: - compact_hash_table() : _items(0), _capacity(0), _count(0) {} - - void clear() { - if (_items) { - xml_memory::deallocate(_items); - _items = 0; - _capacity = 0; - _count = 0; - } - } - - void **find(const void *key) { - assert(key); - - if (_capacity == 0) - return 0; - - size_t hashmod = _capacity - 1; - size_t bucket = hash(key) & hashmod; - - for (size_t probe = 0; probe <= hashmod; ++probe) { - item_t &probe_item = _items[bucket]; - - if (probe_item.key == key) - return &probe_item.value; - - if (probe_item.key == 0) - return 0; - - // hash collision, quadratic probing - bucket = (bucket + probe + 1) & hashmod; - } - - assert(!"Hash table is full"); - return 0; - } - - void **insert(const void *key) { - assert(key); - assert(_capacity != 0 && _count < _capacity - _capacity / 4); - - size_t hashmod = _capacity - 1; - size_t bucket = hash(key) & hashmod; - - for (size_t probe = 0; probe <= hashmod; ++probe) { - item_t &probe_item = _items[bucket]; - - if (probe_item.key == 0) { - probe_item.key = key; - _count++; - return &probe_item.value; - } - - if (probe_item.key == key) - return &probe_item.value; - - // hash collision, quadratic probing - bucket = (bucket + probe + 1) & hashmod; - } - - assert(!"Hash table is full"); - return 0; - } - - bool reserve() { - if (_count + 16 >= _capacity - _capacity / 4) - return rehash(); - - return true; - } - -private: - struct item_t { - const void *key; - void *value; - }; - - item_t *_items; - size_t _capacity; - - size_t _count; - - bool rehash(); - - static unsigned int hash(const void *key) { - unsigned int h = - static_cast(reinterpret_cast(key)); - - // MurmurHash3 32-bit finalizer - h ^= h >> 16; - h *= 0x85ebca6bu; - h ^= h >> 13; - h *= 0xc2b2ae35u; - h ^= h >> 16; - - return h; - } -}; - -PUGI__FN_NO_INLINE bool compact_hash_table::rehash() { - compact_hash_table rt; - rt._capacity = (_capacity == 0) ? 32 : _capacity * 2; - rt._items = static_cast( - xml_memory::allocate(sizeof(item_t) * rt._capacity)); - - if (!rt._items) - return false; - - memset(rt._items, 0, sizeof(item_t) * rt._capacity); - - for (size_t i = 0; i < _capacity; ++i) - if (_items[i].key) - *rt.insert(_items[i].key) = _items[i].value; - - if (_items) - xml_memory::deallocate(_items); - - _capacity = rt._capacity; - _items = rt._items; - - assert(_count == rt._count); - - return true; -} - -PUGI__NS_END -#endif - -PUGI__NS_BEGIN -static const size_t xml_memory_page_size = -#ifdef PUGIXML_MEMORY_PAGE_SIZE - PUGIXML_MEMORY_PAGE_SIZE -#else - 32768 -#endif - ; - -#ifdef PUGIXML_COMPACT -static const uintptr_t xml_memory_block_alignment = 4; - -static const uintptr_t xml_memory_page_alignment = sizeof(void *); -#else -static const uintptr_t xml_memory_block_alignment = sizeof(void *); - -static const uintptr_t xml_memory_page_alignment = 64; -static const uintptr_t xml_memory_page_pointer_mask = - ~(xml_memory_page_alignment - 1); -#endif - -// extra metadata bits -static const uintptr_t xml_memory_page_contents_shared_mask = 32; -static const uintptr_t xml_memory_page_name_allocated_mask = 16; -static const uintptr_t xml_memory_page_value_allocated_mask = 8; -static const uintptr_t xml_memory_page_type_mask = 7; - -// combined masks for string uniqueness -static const uintptr_t xml_memory_page_name_allocated_or_shared_mask = - xml_memory_page_name_allocated_mask | xml_memory_page_contents_shared_mask; -static const uintptr_t xml_memory_page_value_allocated_or_shared_mask = - xml_memory_page_value_allocated_mask | xml_memory_page_contents_shared_mask; - -#ifdef PUGIXML_COMPACT -#define PUGI__GETPAGE_IMPL(header) (header).get_page() -#else -#define PUGI__GETPAGE_IMPL(header) \ - reinterpret_cast( \ - (header)&impl::xml_memory_page_pointer_mask) -#endif - -#define PUGI__GETPAGE(n) PUGI__GETPAGE_IMPL((n)->header) -#define PUGI__NODETYPE(n) \ - static_cast(((n)->header & impl::xml_memory_page_type_mask) + \ - 1) - -struct xml_allocator; - -struct xml_memory_page { - static xml_memory_page *construct(void *memory) { - xml_memory_page *result = static_cast(memory); - - result->allocator = 0; - result->prev = 0; - result->next = 0; - result->busy_size = 0; - result->freed_size = 0; - -#ifdef PUGIXML_COMPACT - result->compact_string_base = 0; - result->compact_shared_parent = 0; - result->compact_page_marker = 0; -#endif - - return result; - } - - xml_allocator *allocator; - - xml_memory_page *prev; - xml_memory_page *next; - - size_t busy_size; - size_t freed_size; - -#ifdef PUGIXML_COMPACT - char_t *compact_string_base; - void *compact_shared_parent; - uint32_t *compact_page_marker; -#endif -}; - -struct xml_memory_string_header { - uint16_t page_offset; // offset from page->data - uint16_t full_size; // 0 if string occupies whole page -}; - -struct xml_allocator { - xml_allocator(xml_memory_page *root) - : _root(root), _busy_size(root->busy_size) { -#ifdef PUGIXML_COMPACT - _hash = 0; -#endif - } - - xml_memory_page *allocate_page(size_t data_size) { - size_t size = sizeof(xml_memory_page) + data_size; - - // allocate block with some alignment, leaving memory for worst-case padding - void *memory = xml_memory::allocate(size + xml_memory_page_alignment); - if (!memory) - return 0; - - // align to next page boundary (note: this guarantees at least 1 usable byte - // before the page) - char *page_memory = reinterpret_cast( - (reinterpret_cast(memory) + xml_memory_page_alignment) & - ~(xml_memory_page_alignment - 1)); - - // prepare page structure - xml_memory_page *page = xml_memory_page::construct(page_memory); - assert(page); - - page->allocator = _root->allocator; - - // record the offset for freeing the memory block - assert(page_memory > memory && - page_memory - static_cast(memory) <= 127); - page_memory[-1] = - static_cast(page_memory - static_cast(memory)); - - return page; - } - - static void deallocate_page(xml_memory_page *page) { - char *page_memory = reinterpret_cast(page); - - xml_memory::deallocate(page_memory - page_memory[-1]); - } - - void *allocate_memory_oob(size_t size, xml_memory_page *&out_page); - - void *allocate_memory(size_t size, xml_memory_page *&out_page) { - if (PUGI__UNLIKELY(_busy_size + size > xml_memory_page_size)) - return allocate_memory_oob(size, out_page); - - void *buf = - reinterpret_cast(_root) + sizeof(xml_memory_page) + _busy_size; - - _busy_size += size; - - out_page = _root; - - return buf; - } - -#ifdef PUGIXML_COMPACT - void *allocate_object(size_t size, xml_memory_page *&out_page) { - void *result = allocate_memory(size + sizeof(uint32_t), out_page); - if (!result) - return 0; - - // adjust for marker - ptrdiff_t offset = static_cast(result) - - reinterpret_cast(out_page->compact_page_marker); - - if (PUGI__UNLIKELY(static_cast(offset) >= - 256 * xml_memory_block_alignment)) { - // insert new marker - uint32_t *marker = static_cast(result); - - *marker = static_cast(reinterpret_cast(marker) - - reinterpret_cast(out_page)); - out_page->compact_page_marker = marker; - - // since we don't reuse the page space until we reallocate it, we can just - // pretend that we freed the marker block this will make sure - // deallocate_memory correctly tracks the size - out_page->freed_size += sizeof(uint32_t); - - return marker + 1; - } else { - // roll back uint32_t part - _busy_size -= sizeof(uint32_t); - - return result; - } - } -#else - void *allocate_object(size_t size, xml_memory_page *&out_page) { - return allocate_memory(size, out_page); - } -#endif - - void deallocate_memory(void *ptr, size_t size, xml_memory_page *page) { - if (page == _root) - page->busy_size = _busy_size; - - assert(ptr >= reinterpret_cast(page) + sizeof(xml_memory_page) && - ptr < reinterpret_cast(page) + sizeof(xml_memory_page) + - page->busy_size); - (void)!ptr; - - page->freed_size += size; - assert(page->freed_size <= page->busy_size); - - if (page->freed_size == page->busy_size) { - if (page->next == 0) { - assert(_root == page); - - // top page freed, just reset sizes - page->busy_size = 0; - page->freed_size = 0; - -#ifdef PUGIXML_COMPACT - // reset compact state to maximize efficiency - page->compact_string_base = 0; - page->compact_shared_parent = 0; - page->compact_page_marker = 0; -#endif - - _busy_size = 0; - } else { - assert(_root != page); - assert(page->prev); - - // remove from the list - page->prev->next = page->next; - page->next->prev = page->prev; - - // deallocate - deallocate_page(page); - } - } - } - - char_t *allocate_string(size_t length) { - static const size_t max_encoded_offset = - (1 << 16) * xml_memory_block_alignment; - - PUGI__STATIC_ASSERT(xml_memory_page_size <= max_encoded_offset); - - // allocate memory for string and header block - size_t size = sizeof(xml_memory_string_header) + length * sizeof(char_t); - - // round size up to block alignment boundary - size_t full_size = (size + (xml_memory_block_alignment - 1)) & - ~(xml_memory_block_alignment - 1); - - xml_memory_page *page; - xml_memory_string_header *header = static_cast( - allocate_memory(full_size, page)); - - if (!header) - return 0; - - // setup header - ptrdiff_t page_offset = reinterpret_cast(header) - - reinterpret_cast(page) - - sizeof(xml_memory_page); - - assert(page_offset % xml_memory_block_alignment == 0); - assert(page_offset >= 0 && - static_cast(page_offset) < max_encoded_offset); - header->page_offset = static_cast( - static_cast(page_offset) / xml_memory_block_alignment); - - // full_size == 0 for large strings that occupy the whole page - assert(full_size % xml_memory_block_alignment == 0); - assert(full_size < max_encoded_offset || - (page->busy_size == full_size && page_offset == 0)); - header->full_size = static_cast( - full_size < max_encoded_offset ? full_size / xml_memory_block_alignment - : 0); - - // round-trip through void* to avoid 'cast increases required alignment of - // target type' warning header is guaranteed a pointer-sized alignment, - // which should be enough for char_t - return static_cast(static_cast(header + 1)); - } - - void deallocate_string(char_t *string) { - // this function casts pointers through void* to avoid 'cast increases - // required alignment of target type' warnings we're guaranteed the proper - // (pointer-sized) alignment on the input string if it was allocated via - // allocate_string - - // get header - xml_memory_string_header *header = - static_cast(static_cast(string)) - - 1; - assert(header); - - // deallocate - size_t page_offset = sizeof(xml_memory_page) + - header->page_offset * xml_memory_block_alignment; - xml_memory_page *page = reinterpret_cast( - static_cast(reinterpret_cast(header) - page_offset)); - - // if full_size == 0 then this string occupies the whole page - size_t full_size = header->full_size == 0 - ? page->busy_size - : header->full_size * xml_memory_block_alignment; - - deallocate_memory(header, full_size, page); - } - - bool reserve() { -#ifdef PUGIXML_COMPACT - return _hash->reserve(); -#else - return true; -#endif - } - - xml_memory_page *_root; - size_t _busy_size; - -#ifdef PUGIXML_COMPACT - compact_hash_table *_hash; -#endif -}; - -PUGI__FN_NO_INLINE void * -xml_allocator::allocate_memory_oob(size_t size, xml_memory_page *&out_page) { - const size_t large_allocation_threshold = xml_memory_page_size / 4; - - xml_memory_page *page = allocate_page( - size <= large_allocation_threshold ? xml_memory_page_size : size); - out_page = page; - - if (!page) - return 0; - - if (size <= large_allocation_threshold) { - _root->busy_size = _busy_size; - - // insert page at the end of linked list - page->prev = _root; - _root->next = page; - _root = page; - - _busy_size = size; - } else { - // insert page before the end of linked list, so that it is deleted as soon - // as possible the last page is not deleted even if it's empty (see - // deallocate_memory) - assert(_root->prev); - - page->prev = _root->prev; - page->next = _root; - - _root->prev->next = page; - _root->prev = page; - - page->busy_size = size; - } - - return reinterpret_cast(page) + sizeof(xml_memory_page); -} -PUGI__NS_END - -#ifdef PUGIXML_COMPACT -PUGI__NS_BEGIN -static const uintptr_t compact_alignment_log2 = 2; -static const uintptr_t compact_alignment = 1 << compact_alignment_log2; - -class compact_header { -public: - compact_header(xml_memory_page *page, unsigned int flags) { - PUGI__STATIC_ASSERT(xml_memory_block_alignment == compact_alignment); - - ptrdiff_t offset = (reinterpret_cast(this) - - reinterpret_cast(page->compact_page_marker)); - assert(offset % compact_alignment == 0 && - static_cast(offset) < 256 * compact_alignment); - - _page = static_cast(offset >> compact_alignment_log2); - _flags = static_cast(flags); - } - - void operator&=(uintptr_t mod) { _flags &= static_cast(mod); } - - void operator|=(uintptr_t mod) { _flags |= static_cast(mod); } - - uintptr_t operator&(uintptr_t mod) const { return _flags & mod; } - - xml_memory_page *get_page() const { - // round-trip through void* to silence 'cast increases required alignment of - // target type' warnings - const char *page_marker = reinterpret_cast(this) - - (_page << compact_alignment_log2); - const char *page = - page_marker - *reinterpret_cast( - static_cast(page_marker)); - - return const_cast( - reinterpret_cast( - static_cast(page))); - } - -private: - unsigned char _page; - unsigned char _flags; -}; - -PUGI__FN xml_memory_page *compact_get_page(const void *object, - int header_offset) { - const compact_header *header = reinterpret_cast( - static_cast(object) - header_offset); - - return header->get_page(); -} - -template -PUGI__FN_NO_INLINE T *compact_get_value(const void *object) { - return static_cast( - *compact_get_page(object, header_offset)->allocator->_hash->find(object)); -} - -template -PUGI__FN_NO_INLINE void compact_set_value(const void *object, T *value) { - *compact_get_page(object, header_offset)->allocator->_hash->insert(object) = - value; -} - -template -class compact_pointer { -public: - compact_pointer() : _data(0) {} - - void operator=(const compact_pointer &rhs) { *this = rhs + 0; } - - void operator=(T *value) { - if (value) { - // value is guaranteed to be compact-aligned; 'this' is not - // our decoding is based on 'this' aligned to compact alignment downwards - // (see operator T*) so for negative offsets (e.g. -3) we need to adjust - // the diff by compact_alignment - 1 to compensate for arithmetic shift - // rounding for negative values - ptrdiff_t diff = - reinterpret_cast(value) - reinterpret_cast(this); - ptrdiff_t offset = - ((diff + int(compact_alignment - 1)) >> compact_alignment_log2) - - start; - - if (static_cast(offset) <= 253) - _data = static_cast(offset + 1); - else { - compact_set_value(this, value); - - _data = 255; - } - } else - _data = 0; - } - - operator T *() const { - if (_data) { - if (_data < 255) { - uintptr_t base = - reinterpret_cast(this) & ~(compact_alignment - 1); - - return reinterpret_cast( - base + ((_data - 1 + start) << compact_alignment_log2)); - } else - return compact_get_value(this); - } else - return 0; - } - - T *operator->() const { return *this; } - -private: - unsigned char _data; -}; - -template class compact_pointer_parent { -public: - compact_pointer_parent() : _data(0) {} - - void operator=(const compact_pointer_parent &rhs) { *this = rhs + 0; } - - void operator=(T *value) { - if (value) { - // value is guaranteed to be compact-aligned; 'this' is not - // our decoding is based on 'this' aligned to compact alignment downwards - // (see operator T*) so for negative offsets (e.g. -3) we need to adjust - // the diff by compact_alignment - 1 to compensate for arithmetic shift - // behavior for negative values - ptrdiff_t diff = - reinterpret_cast(value) - reinterpret_cast(this); - ptrdiff_t offset = - ((diff + int(compact_alignment - 1)) >> compact_alignment_log2) + - 65533; - - if (static_cast(offset) <= 65533) { - _data = static_cast(offset + 1); - } else { - xml_memory_page *page = compact_get_page(this, header_offset); - - if (PUGI__UNLIKELY(page->compact_shared_parent == 0)) - page->compact_shared_parent = value; - - if (page->compact_shared_parent == value) { - _data = 65534; - } else { - compact_set_value(this, value); - - _data = 65535; - } - } - } else { - _data = 0; - } - } - - operator T *() const { - if (_data) { - if (_data < 65534) { - uintptr_t base = - reinterpret_cast(this) & ~(compact_alignment - 1); - - return reinterpret_cast( - base + ((_data - 1 - 65533) << compact_alignment_log2)); - } else if (_data == 65534) - return static_cast( - compact_get_page(this, header_offset)->compact_shared_parent); - else - return compact_get_value(this); - } else - return 0; - } - - T *operator->() const { return *this; } - -private: - uint16_t _data; -}; - -template class compact_string { -public: - compact_string() : _data(0) {} - - void operator=(const compact_string &rhs) { *this = rhs + 0; } - - void operator=(char_t *value) { - if (value) { - xml_memory_page *page = compact_get_page(this, header_offset); - - if (PUGI__UNLIKELY(page->compact_string_base == 0)) - page->compact_string_base = value; - - ptrdiff_t offset = value - page->compact_string_base; - - if (static_cast(offset) < (65535 << 7)) { - // round-trip through void* to silence 'cast increases required - // alignment of target type' warnings - uint16_t *base = reinterpret_cast( - static_cast(reinterpret_cast(this) - base_offset)); - - if (*base == 0) { - *base = static_cast((offset >> 7) + 1); - _data = static_cast((offset & 127) + 1); - } else { - ptrdiff_t remainder = offset - ((*base - 1) << 7); - - if (static_cast(remainder) <= 253) { - _data = static_cast(remainder + 1); - } else { - compact_set_value(this, value); - - _data = 255; - } - } - } else { - compact_set_value(this, value); - - _data = 255; - } - } else { - _data = 0; - } - } - - operator char_t *() const { - if (_data) { - if (_data < 255) { - xml_memory_page *page = compact_get_page(this, header_offset); - - // round-trip through void* to silence 'cast increases required - // alignment of target type' warnings - const uint16_t *base = - reinterpret_cast(static_cast( - reinterpret_cast(this) - base_offset)); - assert(*base); - - ptrdiff_t offset = ((*base - 1) << 7) + (_data - 1); - - return page->compact_string_base + offset; - } else { - return compact_get_value(this); - } - } else - return 0; - } - -private: - unsigned char _data; -}; -PUGI__NS_END -#endif - -#ifdef PUGIXML_COMPACT -namespace pugi { -struct xml_attribute_struct { - xml_attribute_struct(impl::xml_memory_page *page) - : header(page, 0), namevalue_base(0) { - PUGI__STATIC_ASSERT(sizeof(xml_attribute_struct) == 8); - } - - impl::compact_header header; - - uint16_t namevalue_base; - - impl::compact_string<4, 2> name; - impl::compact_string<5, 3> value; - - impl::compact_pointer prev_attribute_c; - impl::compact_pointer next_attribute; -}; - -struct xml_node_struct { - xml_node_struct(impl::xml_memory_page *page, xml_node_type type) - : header(page, type - 1), namevalue_base(0) { - PUGI__STATIC_ASSERT(sizeof(xml_node_struct) == 12); - } - - impl::compact_header header; - - uint16_t namevalue_base; - - impl::compact_string<4, 2> name; - impl::compact_string<5, 3> value; - - impl::compact_pointer_parent parent; - - impl::compact_pointer first_child; - - impl::compact_pointer prev_sibling_c; - impl::compact_pointer next_sibling; - - impl::compact_pointer first_attribute; -}; -} // namespace pugi -#else -namespace pugi { -struct xml_attribute_struct { - xml_attribute_struct(impl::xml_memory_page *page) - : header(reinterpret_cast(page)), name(0), value(0), - prev_attribute_c(0), next_attribute(0) {} - - uintptr_t header; - - char_t *name; - char_t *value; - - xml_attribute_struct *prev_attribute_c; - xml_attribute_struct *next_attribute; -}; - -struct xml_node_struct { - xml_node_struct(impl::xml_memory_page *page, xml_node_type type) - : header(reinterpret_cast(page) | (type - 1)), name(0), - value(0), parent(0), first_child(0), prev_sibling_c(0), next_sibling(0), - first_attribute(0) {} - - uintptr_t header; - - char_t *name; - char_t *value; - - xml_node_struct *parent; - - xml_node_struct *first_child; - - xml_node_struct *prev_sibling_c; - xml_node_struct *next_sibling; - - xml_attribute_struct *first_attribute; -}; -} // namespace pugi -#endif - -PUGI__NS_BEGIN -struct xml_extra_buffer { - char_t *buffer; - xml_extra_buffer *next; -}; - -struct xml_document_struct : public xml_node_struct, public xml_allocator { - xml_document_struct(xml_memory_page *page) - : xml_node_struct(page, node_document), xml_allocator(page), buffer(0), - extra_buffers(0) { -#ifdef PUGIXML_COMPACT - _hash = &hash; -#endif - } - - const char_t *buffer; - - xml_extra_buffer *extra_buffers; - -#ifdef PUGIXML_COMPACT - compact_hash_table hash; -#endif -}; - -template -inline xml_allocator &get_allocator(const Object *object) { - assert(object); - - return *PUGI__GETPAGE(object)->allocator; -} - -template -inline xml_document_struct &get_document(const Object *object) { - assert(object); - - return *static_cast(PUGI__GETPAGE(object)->allocator); -} -PUGI__NS_END - -// Low-level DOM operations -PUGI__NS_BEGIN -inline xml_attribute_struct *allocate_attribute(xml_allocator &alloc) { - xml_memory_page *page; - void *memory = alloc.allocate_object(sizeof(xml_attribute_struct), page); - if (!memory) - return 0; - - return new (memory) xml_attribute_struct(page); -} - -inline xml_node_struct *allocate_node(xml_allocator &alloc, - xml_node_type type) { - xml_memory_page *page; - void *memory = alloc.allocate_object(sizeof(xml_node_struct), page); - if (!memory) - return 0; - - return new (memory) xml_node_struct(page, type); -} - -inline void destroy_attribute(xml_attribute_struct *a, xml_allocator &alloc) { - if (a->header & impl::xml_memory_page_name_allocated_mask) - alloc.deallocate_string(a->name); - - if (a->header & impl::xml_memory_page_value_allocated_mask) - alloc.deallocate_string(a->value); - - alloc.deallocate_memory(a, sizeof(xml_attribute_struct), PUGI__GETPAGE(a)); -} - -inline void destroy_node(xml_node_struct *n, xml_allocator &alloc) { - if (n->header & impl::xml_memory_page_name_allocated_mask) - alloc.deallocate_string(n->name); - - if (n->header & impl::xml_memory_page_value_allocated_mask) - alloc.deallocate_string(n->value); - - for (xml_attribute_struct *attr = n->first_attribute; attr;) { - xml_attribute_struct *next = attr->next_attribute; - - destroy_attribute(attr, alloc); - - attr = next; - } - - for (xml_node_struct *child = n->first_child; child;) { - xml_node_struct *next = child->next_sibling; - - destroy_node(child, alloc); - - child = next; - } - - alloc.deallocate_memory(n, sizeof(xml_node_struct), PUGI__GETPAGE(n)); -} - -inline void append_node(xml_node_struct *child, xml_node_struct *node) { - child->parent = node; - - xml_node_struct *head = node->first_child; - - if (head) { - xml_node_struct *tail = head->prev_sibling_c; - - tail->next_sibling = child; - child->prev_sibling_c = tail; - head->prev_sibling_c = child; - } else { - node->first_child = child; - child->prev_sibling_c = child; - } -} - -inline void prepend_node(xml_node_struct *child, xml_node_struct *node) { - child->parent = node; - - xml_node_struct *head = node->first_child; - - if (head) { - child->prev_sibling_c = head->prev_sibling_c; - head->prev_sibling_c = child; - } else - child->prev_sibling_c = child; - - child->next_sibling = head; - node->first_child = child; -} - -inline void insert_node_after(xml_node_struct *child, xml_node_struct *node) { - xml_node_struct *parent = node->parent; - - child->parent = parent; - - if (node->next_sibling) - node->next_sibling->prev_sibling_c = child; - else - parent->first_child->prev_sibling_c = child; - - child->next_sibling = node->next_sibling; - child->prev_sibling_c = node; - - node->next_sibling = child; -} - -inline void insert_node_before(xml_node_struct *child, xml_node_struct *node) { - xml_node_struct *parent = node->parent; - - child->parent = parent; - - if (node->prev_sibling_c->next_sibling) - node->prev_sibling_c->next_sibling = child; - else - parent->first_child = child; - - child->prev_sibling_c = node->prev_sibling_c; - child->next_sibling = node; - - node->prev_sibling_c = child; -} - -inline void remove_node(xml_node_struct *node) { - xml_node_struct *parent = node->parent; - - if (node->next_sibling) - node->next_sibling->prev_sibling_c = node->prev_sibling_c; - else - parent->first_child->prev_sibling_c = node->prev_sibling_c; - - if (node->prev_sibling_c->next_sibling) - node->prev_sibling_c->next_sibling = node->next_sibling; - else - parent->first_child = node->next_sibling; - - node->parent = 0; - node->prev_sibling_c = 0; - node->next_sibling = 0; -} - -inline void append_attribute(xml_attribute_struct *attr, - xml_node_struct *node) { - xml_attribute_struct *head = node->first_attribute; - - if (head) { - xml_attribute_struct *tail = head->prev_attribute_c; - - tail->next_attribute = attr; - attr->prev_attribute_c = tail; - head->prev_attribute_c = attr; - } else { - node->first_attribute = attr; - attr->prev_attribute_c = attr; - } -} - -inline void prepend_attribute(xml_attribute_struct *attr, - xml_node_struct *node) { - xml_attribute_struct *head = node->first_attribute; - - if (head) { - attr->prev_attribute_c = head->prev_attribute_c; - head->prev_attribute_c = attr; - } else - attr->prev_attribute_c = attr; - - attr->next_attribute = head; - node->first_attribute = attr; -} - -inline void insert_attribute_after(xml_attribute_struct *attr, - xml_attribute_struct *place, - xml_node_struct *node) { - if (place->next_attribute) - place->next_attribute->prev_attribute_c = attr; - else - node->first_attribute->prev_attribute_c = attr; - - attr->next_attribute = place->next_attribute; - attr->prev_attribute_c = place; - place->next_attribute = attr; -} - -inline void insert_attribute_before(xml_attribute_struct *attr, - xml_attribute_struct *place, - xml_node_struct *node) { - if (place->prev_attribute_c->next_attribute) - place->prev_attribute_c->next_attribute = attr; - else - node->first_attribute = attr; - - attr->prev_attribute_c = place->prev_attribute_c; - attr->next_attribute = place; - place->prev_attribute_c = attr; -} - -inline void remove_attribute(xml_attribute_struct *attr, - xml_node_struct *node) { - if (attr->next_attribute) - attr->next_attribute->prev_attribute_c = attr->prev_attribute_c; - else - node->first_attribute->prev_attribute_c = attr->prev_attribute_c; - - if (attr->prev_attribute_c->next_attribute) - attr->prev_attribute_c->next_attribute = attr->next_attribute; - else - node->first_attribute = attr->next_attribute; - - attr->prev_attribute_c = 0; - attr->next_attribute = 0; -} - -PUGI__FN_NO_INLINE xml_node_struct * -append_new_node(xml_node_struct *node, xml_allocator &alloc, - xml_node_type type = node_element) { - if (!alloc.reserve()) - return 0; - - xml_node_struct *child = allocate_node(alloc, type); - if (!child) - return 0; - - append_node(child, node); - - return child; -} - -PUGI__FN_NO_INLINE xml_attribute_struct * -append_new_attribute(xml_node_struct *node, xml_allocator &alloc) { - if (!alloc.reserve()) - return 0; - - xml_attribute_struct *attr = allocate_attribute(alloc); - if (!attr) - return 0; - - append_attribute(attr, node); - - return attr; -} -PUGI__NS_END - -// Helper classes for code generation -PUGI__NS_BEGIN -struct opt_false { - enum { value = 0 }; -}; - -struct opt_true { - enum { value = 1 }; -}; -PUGI__NS_END - -// Unicode utilities -PUGI__NS_BEGIN -inline uint16_t endian_swap(uint16_t value) { - return static_cast(((value & 0xff) << 8) | (value >> 8)); -} - -inline uint32_t endian_swap(uint32_t value) { - return ((value & 0xff) << 24) | ((value & 0xff00) << 8) | - ((value & 0xff0000) >> 8) | (value >> 24); -} - -struct utf8_counter { - typedef size_t value_type; - - static value_type low(value_type result, uint32_t ch) { - // U+0000..U+007F - if (ch < 0x80) - return result + 1; - // U+0080..U+07FF - else if (ch < 0x800) - return result + 2; - // U+0800..U+FFFF - else - return result + 3; - } - - static value_type high(value_type result, uint32_t) { - // U+10000..U+10FFFF - return result + 4; - } -}; - -struct utf8_writer { - typedef uint8_t *value_type; - - static value_type low(value_type result, uint32_t ch) { - // U+0000..U+007F - if (ch < 0x80) { - *result = static_cast(ch); - return result + 1; - } - // U+0080..U+07FF - else if (ch < 0x800) { - result[0] = static_cast(0xC0 | (ch >> 6)); - result[1] = static_cast(0x80 | (ch & 0x3F)); - return result + 2; - } - // U+0800..U+FFFF - else { - result[0] = static_cast(0xE0 | (ch >> 12)); - result[1] = static_cast(0x80 | ((ch >> 6) & 0x3F)); - result[2] = static_cast(0x80 | (ch & 0x3F)); - return result + 3; - } - } - - static value_type high(value_type result, uint32_t ch) { - // U+10000..U+10FFFF - result[0] = static_cast(0xF0 | (ch >> 18)); - result[1] = static_cast(0x80 | ((ch >> 12) & 0x3F)); - result[2] = static_cast(0x80 | ((ch >> 6) & 0x3F)); - result[3] = static_cast(0x80 | (ch & 0x3F)); - return result + 4; - } - - static value_type any(value_type result, uint32_t ch) { - return (ch < 0x10000) ? low(result, ch) : high(result, ch); - } -}; - -struct utf16_counter { - typedef size_t value_type; - - static value_type low(value_type result, uint32_t) { return result + 1; } - - static value_type high(value_type result, uint32_t) { return result + 2; } -}; - -struct utf16_writer { - typedef uint16_t *value_type; - - static value_type low(value_type result, uint32_t ch) { - *result = static_cast(ch); - - return result + 1; - } - - static value_type high(value_type result, uint32_t ch) { - uint32_t msh = static_cast(ch - 0x10000) >> 10; - uint32_t lsh = static_cast(ch - 0x10000) & 0x3ff; - - result[0] = static_cast(0xD800 + msh); - result[1] = static_cast(0xDC00 + lsh); - - return result + 2; - } - - static value_type any(value_type result, uint32_t ch) { - return (ch < 0x10000) ? low(result, ch) : high(result, ch); - } -}; - -struct utf32_counter { - typedef size_t value_type; - - static value_type low(value_type result, uint32_t) { return result + 1; } - - static value_type high(value_type result, uint32_t) { return result + 1; } -}; - -struct utf32_writer { - typedef uint32_t *value_type; - - static value_type low(value_type result, uint32_t ch) { - *result = ch; - - return result + 1; - } - - static value_type high(value_type result, uint32_t ch) { - *result = ch; - - return result + 1; - } - - static value_type any(value_type result, uint32_t ch) { - *result = ch; - - return result + 1; - } -}; - -struct latin1_writer { - typedef uint8_t *value_type; - - static value_type low(value_type result, uint32_t ch) { - *result = static_cast(ch > 255 ? '?' : ch); - - return result + 1; - } - - static value_type high(value_type result, uint32_t ch) { - (void)ch; - - *result = '?'; - - return result + 1; - } -}; - -struct utf8_decoder { - typedef uint8_t type; - - template - static inline typename Traits::value_type - process(const uint8_t *data, size_t size, typename Traits::value_type result, - Traits) { - const uint8_t utf8_byte_mask = 0x3f; - - while (size) { - uint8_t lead = *data; - - // 0xxxxxxx -> U+0000..U+007F - if (lead < 0x80) { - result = Traits::low(result, lead); - data += 1; - size -= 1; - - // process aligned single-byte (ascii) blocks - if ((reinterpret_cast(data) & 3) == 0) { - // round-trip through void* to silence 'cast increases required - // alignment of target type' warnings - while (size >= 4 && (*static_cast( - static_cast(data)) & - 0x80808080) == 0) { - result = Traits::low(result, data[0]); - result = Traits::low(result, data[1]); - result = Traits::low(result, data[2]); - result = Traits::low(result, data[3]); - data += 4; - size -= 4; - } - } - } - // 110xxxxx -> U+0080..U+07FF - else if (static_cast(lead - 0xC0) < 0x20 && size >= 2 && - (data[1] & 0xc0) == 0x80) { - result = Traits::low(result, ((lead & ~0xC0) << 6) | - (data[1] & utf8_byte_mask)); - data += 2; - size -= 2; - } - // 1110xxxx -> U+0800-U+FFFF - else if (static_cast(lead - 0xE0) < 0x10 && size >= 3 && - (data[1] & 0xc0) == 0x80 && (data[2] & 0xc0) == 0x80) { - result = Traits::low(result, ((lead & ~0xE0) << 12) | - ((data[1] & utf8_byte_mask) << 6) | - (data[2] & utf8_byte_mask)); - data += 3; - size -= 3; - } - // 11110xxx -> U+10000..U+10FFFF - else if (static_cast(lead - 0xF0) < 0x08 && size >= 4 && - (data[1] & 0xc0) == 0x80 && (data[2] & 0xc0) == 0x80 && - (data[3] & 0xc0) == 0x80) { - result = Traits::high(result, ((lead & ~0xF0) << 18) | - ((data[1] & utf8_byte_mask) << 12) | - ((data[2] & utf8_byte_mask) << 6) | - (data[3] & utf8_byte_mask)); - data += 4; - size -= 4; - } - // 10xxxxxx or 11111xxx -> invalid - else { - data += 1; - size -= 1; - } - } - - return result; - } -}; - -template struct utf16_decoder { - typedef uint16_t type; - - template - static inline typename Traits::value_type - process(const uint16_t *data, size_t size, typename Traits::value_type result, - Traits) { - while (size) { - uint16_t lead = opt_swap::value ? endian_swap(*data) : *data; - - // U+0000..U+D7FF - if (lead < 0xD800) { - result = Traits::low(result, lead); - data += 1; - size -= 1; - } - // U+E000..U+FFFF - else if (static_cast(lead - 0xE000) < 0x2000) { - result = Traits::low(result, lead); - data += 1; - size -= 1; - } - // surrogate pair lead - else if (static_cast(lead - 0xD800) < 0x400 && size >= 2) { - uint16_t next = opt_swap::value ? endian_swap(data[1]) : data[1]; - - if (static_cast(next - 0xDC00) < 0x400) { - result = Traits::high(result, 0x10000 + ((lead & 0x3ff) << 10) + - (next & 0x3ff)); - data += 2; - size -= 2; - } else { - data += 1; - size -= 1; - } - } else { - data += 1; - size -= 1; - } - } - - return result; - } -}; - -template struct utf32_decoder { - typedef uint32_t type; - - template - static inline typename Traits::value_type - process(const uint32_t *data, size_t size, typename Traits::value_type result, - Traits) { - while (size) { - uint32_t lead = opt_swap::value ? endian_swap(*data) : *data; - - // U+0000..U+FFFF - if (lead < 0x10000) { - result = Traits::low(result, lead); - data += 1; - size -= 1; - } - // U+10000..U+10FFFF - else { - result = Traits::high(result, lead); - data += 1; - size -= 1; - } - } - - return result; - } -}; - -struct latin1_decoder { - typedef uint8_t type; - - template - static inline typename Traits::value_type - process(const uint8_t *data, size_t size, typename Traits::value_type result, - Traits) { - while (size) { - result = Traits::low(result, *data); - data += 1; - size -= 1; - } - - return result; - } -}; - -template struct wchar_selector; - -template <> struct wchar_selector<2> { - typedef uint16_t type; - typedef utf16_counter counter; - typedef utf16_writer writer; - typedef utf16_decoder decoder; -}; - -template <> struct wchar_selector<4> { - typedef uint32_t type; - typedef utf32_counter counter; - typedef utf32_writer writer; - typedef utf32_decoder decoder; -}; - -typedef wchar_selector::counter wchar_counter; -typedef wchar_selector::writer wchar_writer; - -struct wchar_decoder { - typedef wchar_t type; - - template - static inline typename Traits::value_type - process(const wchar_t *data, size_t size, typename Traits::value_type result, - Traits traits) { - typedef wchar_selector::decoder decoder; - - return decoder::process( - reinterpret_cast(data), size, result, - traits); - } -}; - -#ifdef PUGIXML_WCHAR_MODE -PUGI__FN void convert_wchar_endian_swap(wchar_t *result, const wchar_t *data, - size_t length) { - for (size_t i = 0; i < length; ++i) - result[i] = static_cast(endian_swap( - static_cast::type>(data[i]))); -} -#endif -PUGI__NS_END - -PUGI__NS_BEGIN -enum chartype_t { - ct_parse_pcdata = 1, // \0, &, \r, < - ct_parse_attr = 2, // \0, &, \r, ', " - ct_parse_attr_ws = 4, // \0, &, \r, ', ", \n, tab - ct_space = 8, // \r, \n, space, tab - ct_parse_cdata = 16, // \0, ], >, \r - ct_parse_comment = 32, // \0, -, >, \r - ct_symbol = 64, // Any symbol > 127, a-z, A-Z, 0-9, _, :, -, . - ct_start_symbol = 128 // Any symbol > 127, a-z, A-Z, _, : -}; - -static const unsigned char chartype_table[256] = { - 55, 0, 0, 0, 0, 0, 0, 0, 0, 12, 12, 0, 0, 63, - 0, 0, // 0-15 - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, - 0, 0, // 16-31 - 8, 0, 6, 0, 0, 0, 7, 6, 0, 0, 0, 0, 0, 96, - 64, 0, // 32-47 - 64, 64, 64, 64, 64, 64, 64, 64, 64, 64, 192, 0, 1, 0, - 48, 0, // 48-63 - 0, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, // 64-79 - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 0, 0, 16, - 0, 192, // 80-95 - 0, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, // 96-111 - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 0, 0, 0, - 0, 0, // 112-127 - - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, // 128+ - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, - 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192, 192}; - -enum chartypex_t { - ctx_special_pcdata = - 1, // Any symbol >= 0 and < 32 (except \t, \r, \n), &, <, > - ctx_special_attr = 2, // Any symbol >= 0 and < 32 (except \t), &, <, >, " - ctx_start_symbol = 4, // Any symbol > 127, a-z, A-Z, _ - ctx_digit = 8, // 0-9 - ctx_symbol = 16 // Any symbol > 127, a-z, A-Z, 0-9, _, -, . -}; - -static const unsigned char chartypex_table[256] = { - 3, 3, 3, 3, 3, 3, 3, 3, 3, 0, 2, 3, 3, 2, 3, 3, // 0-15 - 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, 3, // 16-31 - 0, 0, 2, 0, 0, 0, 3, 0, 0, 0, 0, 0, 0, 16, 16, 0, // 32-47 - 24, 24, 24, 24, 24, 24, 24, 24, 24, 24, 0, 0, 3, 0, 3, 0, // 48-63 - - 0, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, // 64-79 - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 0, 0, 0, 0, 20, // 80-95 - 0, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, // 96-111 - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 0, 0, 0, 0, 0, // 112-127 - - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, // 128+ - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, - 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20, 20}; - -#ifdef PUGIXML_WCHAR_MODE -#define PUGI__IS_CHARTYPE_IMPL(c, ct, table) \ - ((static_cast(c) < 128 ? table[static_cast(c)] \ - : table[128]) & \ - (ct)) -#else -#define PUGI__IS_CHARTYPE_IMPL(c, ct, table) \ - (table[static_cast(c)] & (ct)) -#endif - -#define PUGI__IS_CHARTYPE(c, ct) PUGI__IS_CHARTYPE_IMPL(c, ct, chartype_table) -#define PUGI__IS_CHARTYPEX(c, ct) PUGI__IS_CHARTYPE_IMPL(c, ct, chartypex_table) - -PUGI__FN bool is_little_endian() { - unsigned int ui = 1; - - return *reinterpret_cast(&ui) == 1; -} - -PUGI__FN xml_encoding get_wchar_encoding() { - PUGI__STATIC_ASSERT(sizeof(wchar_t) == 2 || sizeof(wchar_t) == 4); - - if (sizeof(wchar_t) == 2) - return is_little_endian() ? encoding_utf16_le : encoding_utf16_be; - else - return is_little_endian() ? encoding_utf32_le : encoding_utf32_be; -} - -PUGI__FN xml_encoding guess_buffer_encoding(uint8_t d0, uint8_t d1, uint8_t d2, - uint8_t d3) { - // look for BOM in first few bytes - if (d0 == 0 && d1 == 0 && d2 == 0xfe && d3 == 0xff) - return encoding_utf32_be; - if (d0 == 0xff && d1 == 0xfe && d2 == 0 && d3 == 0) - return encoding_utf32_le; - if (d0 == 0xfe && d1 == 0xff) - return encoding_utf16_be; - if (d0 == 0xff && d1 == 0xfe) - return encoding_utf16_le; - if (d0 == 0xef && d1 == 0xbb && d2 == 0xbf) - return encoding_utf8; - - // look for <, (contents); - - PUGI__DMC_VOLATILE uint8_t d0 = data[0], d1 = data[1], d2 = data[2], - d3 = data[3]; - - return guess_buffer_encoding(d0, d1, d2, d3); -} - -PUGI__FN bool get_mutable_buffer(char_t *&out_buffer, size_t &out_length, - const void *contents, size_t size, - bool is_mutable) { - size_t length = size / sizeof(char_t); - - if (is_mutable) { - out_buffer = static_cast(const_cast(contents)); - out_length = length; - } else { - char_t *buffer = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!buffer) - return false; - - if (contents) - memcpy(buffer, contents, length * sizeof(char_t)); - else - assert(length == 0); - - buffer[length] = 0; - - out_buffer = buffer; - out_length = length + 1; - } - - return true; -} - -#ifdef PUGIXML_WCHAR_MODE -PUGI__FN bool need_endian_swap_utf(xml_encoding le, xml_encoding re) { - return (le == encoding_utf16_be && re == encoding_utf16_le) || - (le == encoding_utf16_le && re == encoding_utf16_be) || - (le == encoding_utf32_be && re == encoding_utf32_le) || - (le == encoding_utf32_le && re == encoding_utf32_be); -} - -PUGI__FN bool convert_buffer_endian_swap(char_t *&out_buffer, - size_t &out_length, - const void *contents, size_t size, - bool is_mutable) { - const char_t *data = static_cast(contents); - size_t length = size / sizeof(char_t); - - if (is_mutable) { - char_t *buffer = const_cast(data); - - convert_wchar_endian_swap(buffer, data, length); - - out_buffer = buffer; - out_length = length; - } else { - char_t *buffer = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!buffer) - return false; - - convert_wchar_endian_swap(buffer, data, length); - buffer[length] = 0; - - out_buffer = buffer; - out_length = length + 1; - } - - return true; -} - -template -PUGI__FN bool convert_buffer_generic(char_t *&out_buffer, size_t &out_length, - const void *contents, size_t size, D) { - const typename D::type *data = - static_cast(contents); - size_t data_length = size / sizeof(typename D::type); - - // first pass: get length in wchar_t units - size_t length = D::process(data, data_length, 0, wchar_counter()); - - // allocate buffer of suitable length - char_t *buffer = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!buffer) - return false; - - // second pass: convert utf16 input to wchar_t - wchar_writer::value_type obegin = - reinterpret_cast(buffer); - wchar_writer::value_type oend = - D::process(data, data_length, obegin, wchar_writer()); - - assert(oend == obegin + length); - *oend = 0; - - out_buffer = buffer; - out_length = length + 1; - - return true; -} - -PUGI__FN bool convert_buffer(char_t *&out_buffer, size_t &out_length, - xml_encoding encoding, const void *contents, - size_t size, bool is_mutable) { - // get native encoding - xml_encoding wchar_encoding = get_wchar_encoding(); - - // fast path: no conversion required - if (encoding == wchar_encoding) - return get_mutable_buffer(out_buffer, out_length, contents, size, - is_mutable); - - // only endian-swapping is required - if (need_endian_swap_utf(encoding, wchar_encoding)) - return convert_buffer_endian_swap(out_buffer, out_length, contents, size, - is_mutable); - - // source encoding is utf8 - if (encoding == encoding_utf8) - return convert_buffer_generic(out_buffer, out_length, contents, size, - utf8_decoder()); - - // source encoding is utf16 - if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf16_le : encoding_utf16_be; - - return (native_encoding == encoding) - ? convert_buffer_generic(out_buffer, out_length, contents, size, - utf16_decoder()) - : convert_buffer_generic(out_buffer, out_length, contents, size, - utf16_decoder()); - } - - // source encoding is utf32 - if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf32_le : encoding_utf32_be; - - return (native_encoding == encoding) - ? convert_buffer_generic(out_buffer, out_length, contents, size, - utf32_decoder()) - : convert_buffer_generic(out_buffer, out_length, contents, size, - utf32_decoder()); - } - - // source encoding is latin1 - if (encoding == encoding_latin1) - return convert_buffer_generic(out_buffer, out_length, contents, size, - latin1_decoder()); - - assert(!"Invalid encoding"); - return false; -} -#else -template -PUGI__FN bool convert_buffer_generic(char_t *&out_buffer, size_t &out_length, - const void *contents, size_t size, D) { - const typename D::type *data = - static_cast(contents); - size_t data_length = size / sizeof(typename D::type); - - // first pass: get length in utf8 units - size_t length = D::process(data, data_length, 0, utf8_counter()); - - // allocate buffer of suitable length - char_t *buffer = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!buffer) - return false; - - // second pass: convert utf16 input to utf8 - uint8_t *obegin = reinterpret_cast(buffer); - uint8_t *oend = D::process(data, data_length, obegin, utf8_writer()); - - assert(oend == obegin + length); - *oend = 0; - - out_buffer = buffer; - out_length = length + 1; - - return true; -} - -PUGI__FN size_t get_latin1_7bit_prefix_length(const uint8_t *data, - size_t size) { - for (size_t i = 0; i < size; ++i) - if (data[i] > 127) - return i; - - return size; -} - -PUGI__FN bool convert_buffer_latin1(char_t *&out_buffer, size_t &out_length, - const void *contents, size_t size, - bool is_mutable) { - const uint8_t *data = static_cast(contents); - size_t data_length = size; - - // get size of prefix that does not need utf8 conversion - size_t prefix_length = get_latin1_7bit_prefix_length(data, data_length); - assert(prefix_length <= data_length); - - const uint8_t *postfix = data + prefix_length; - size_t postfix_length = data_length - prefix_length; - - // if no conversion is needed, just return the original buffer - if (postfix_length == 0) - return get_mutable_buffer(out_buffer, out_length, contents, size, - is_mutable); - - // first pass: get length in utf8 units - size_t length = - prefix_length + - latin1_decoder::process(postfix, postfix_length, 0, utf8_counter()); - - // allocate buffer of suitable length - char_t *buffer = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!buffer) - return false; - - // second pass: convert latin1 input to utf8 - memcpy(buffer, data, prefix_length); - - uint8_t *obegin = reinterpret_cast(buffer); - uint8_t *oend = latin1_decoder::process( - postfix, postfix_length, obegin + prefix_length, utf8_writer()); - - assert(oend == obegin + length); - *oend = 0; - - out_buffer = buffer; - out_length = length + 1; - - return true; -} - -PUGI__FN bool convert_buffer(char_t *&out_buffer, size_t &out_length, - xml_encoding encoding, const void *contents, - size_t size, bool is_mutable) { - // fast path: no conversion required - if (encoding == encoding_utf8) - return get_mutable_buffer(out_buffer, out_length, contents, size, - is_mutable); - - // source encoding is utf16 - if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf16_le : encoding_utf16_be; - - return (native_encoding == encoding) - ? convert_buffer_generic(out_buffer, out_length, contents, size, - utf16_decoder()) - : convert_buffer_generic(out_buffer, out_length, contents, size, - utf16_decoder()); - } - - // source encoding is utf32 - if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf32_le : encoding_utf32_be; - - return (native_encoding == encoding) - ? convert_buffer_generic(out_buffer, out_length, contents, size, - utf32_decoder()) - : convert_buffer_generic(out_buffer, out_length, contents, size, - utf32_decoder()); - } - - // source encoding is latin1 - if (encoding == encoding_latin1) - return convert_buffer_latin1(out_buffer, out_length, contents, size, - is_mutable); - - assert(!"Invalid encoding"); - return false; -} -#endif - -PUGI__FN size_t as_utf8_begin(const wchar_t *str, size_t length) { - // get length in utf8 characters - return wchar_decoder::process(str, length, 0, utf8_counter()); -} - -PUGI__FN void as_utf8_end(char *buffer, size_t size, const wchar_t *str, - size_t length) { - // convert to utf8 - uint8_t *begin = reinterpret_cast(buffer); - uint8_t *end = wchar_decoder::process(str, length, begin, utf8_writer()); - - assert(begin + size == end); - (void)!end; - (void)!size; -} - -#ifndef PUGIXML_NO_STL -PUGI__FN std::string as_utf8_impl(const wchar_t *str, size_t length) { - // first pass: get length in utf8 characters - size_t size = as_utf8_begin(str, length); - - // allocate resulting string - std::string result; - result.resize(size); - - // second pass: convert to utf8 - if (size > 0) - as_utf8_end(&result[0], size, str, length); - - return result; -} - -PUGI__FN std::basic_string as_wide_impl(const char *str, size_t size) { - const uint8_t *data = reinterpret_cast(str); - - // first pass: get length in wchar_t units - size_t length = utf8_decoder::process(data, size, 0, wchar_counter()); - - // allocate resulting string - std::basic_string result; - result.resize(length); - - // second pass: convert to wchar_t - if (length > 0) { - wchar_writer::value_type begin = - reinterpret_cast(&result[0]); - wchar_writer::value_type end = - utf8_decoder::process(data, size, begin, wchar_writer()); - - assert(begin + length == end); - (void)!end; - } - - return result; -} -#endif - -template -inline bool strcpy_insitu_allow(size_t length, const Header &header, - uintptr_t header_mask, char_t *target) { - // never reuse shared memory - if (header & xml_memory_page_contents_shared_mask) - return false; - - size_t target_length = strlength(target); - - // always reuse document buffer memory if possible - if ((header & header_mask) == 0) - return target_length >= length; - - // reuse heap memory if waste is not too great - const size_t reuse_threshold = 32; - - return target_length >= length && - (target_length < reuse_threshold || - target_length - length < target_length / 2); -} - -template -PUGI__FN bool strcpy_insitu(String &dest, Header &header, uintptr_t header_mask, - const char_t *source, size_t source_length) { - if (source_length == 0) { - // empty string and null pointer are equivalent, so just deallocate old - // memory - xml_allocator *alloc = PUGI__GETPAGE_IMPL(header)->allocator; - - if (header & header_mask) - alloc->deallocate_string(dest); - - // mark the string as not allocated - dest = 0; - header &= ~header_mask; - - return true; - } else if (dest && - strcpy_insitu_allow(source_length, header, header_mask, dest)) { - // we can reuse old buffer, so just copy the new data (including zero - // terminator) - memcpy(dest, source, source_length * sizeof(char_t)); - dest[source_length] = 0; - - return true; - } else { - xml_allocator *alloc = PUGI__GETPAGE_IMPL(header)->allocator; - - if (!alloc->reserve()) - return false; - - // allocate new buffer - char_t *buf = alloc->allocate_string(source_length + 1); - if (!buf) - return false; - - // copy the string (including zero terminator) - memcpy(buf, source, source_length * sizeof(char_t)); - buf[source_length] = 0; - - // deallocate old buffer (*after* the above to protect against overlapping - // memory and/or allocation failures) - if (header & header_mask) - alloc->deallocate_string(dest); - - // the string is now allocated, so set the flag - dest = buf; - header |= header_mask; - - return true; - } -} - -struct gap { - char_t *end; - size_t size; - - gap() : end(0), size(0) {} - - // Push new gap, move s count bytes further (skipping the gap). - // Collapse previous gap. - void push(char_t *&s, size_t count) { - if (end) // there was a gap already; collapse it - { - // Move [old_gap_end, new_gap_start) to [old_gap_start, ...) - assert(s >= end); - memmove(end - size, end, - reinterpret_cast(s) - reinterpret_cast(end)); - } - - s += count; // end of current gap - - // "merge" two gaps - end = s; - size += count; - } - - // Collapse all gaps, return past-the-end pointer - char_t *flush(char_t *s) { - if (end) { - // Move [old_gap_end, current_pos) to [old_gap_start, ...) - assert(s >= end); - memmove(end - size, end, - reinterpret_cast(s) - reinterpret_cast(end)); - - return s - size; - } else - return s; - } -}; - -PUGI__FN char_t *strconv_escape(char_t *s, gap &g) { - char_t *stre = s + 1; - - switch (*stre) { - case '#': // &#... - { - unsigned int ucsc = 0; - - if (stre[1] == 'x') // &#x... (hex code) - { - stre += 2; - - char_t ch = *stre; - - if (ch == ';') - return stre; - - for (;;) { - if (static_cast(ch - '0') <= 9) - ucsc = 16 * ucsc + (ch - '0'); - else if (static_cast((ch | ' ') - 'a') <= 5) - ucsc = 16 * ucsc + ((ch | ' ') - 'a' + 10); - else if (ch == ';') - break; - else // cancel - return stre; - - ch = *++stre; - } - - ++stre; - } else // &#... (dec code) - { - char_t ch = *++stre; - - if (ch == ';') - return stre; - - for (;;) { - if (static_cast(static_cast(ch) - '0') <= 9) - ucsc = 10 * ucsc + (ch - '0'); - else if (ch == ';') - break; - else // cancel - return stre; - - ch = *++stre; - } - - ++stre; - } - -#ifdef PUGIXML_WCHAR_MODE - s = reinterpret_cast( - wchar_writer::any(reinterpret_cast(s), ucsc)); -#else - s = reinterpret_cast( - utf8_writer::any(reinterpret_cast(s), ucsc)); -#endif - - g.push(s, stre - s); - return stre; - } - - case 'a': // &a - { - ++stre; - - if (*stre == 'm') // &am - { - if (*++stre == 'p' && *++stre == ';') // & - { - *s++ = '&'; - ++stre; - - g.push(s, stre - s); - return stre; - } - } else if (*stre == 'p') // &ap - { - if (*++stre == 'o' && *++stre == 's' && *++stre == ';') // ' - { - *s++ = '\''; - ++stre; - - g.push(s, stre - s); - return stre; - } - } - break; - } - - case 'g': // &g - { - if (*++stre == 't' && *++stre == ';') // > - { - *s++ = '>'; - ++stre; - - g.push(s, stre - s); - return stre; - } - break; - } - - case 'l': // &l - { - if (*++stre == 't' && *++stre == ';') // < - { - *s++ = '<'; - ++stre; - - g.push(s, stre - s); - return stre; - } - break; - } - - case 'q': // &q - { - if (*++stre == 'u' && *++stre == 'o' && *++stre == 't' && - *++stre == ';') // " - { - *s++ = '"'; - ++stre; - - g.push(s, stre - s); - return stre; - } - break; - } - - default: - break; - } - - return stre; -} - -// Parser utilities -#define PUGI__ENDSWITH(c, e) ((c) == (e) || ((c) == 0 && endch == (e))) -#define PUGI__SKIPWS() \ - { \ - while (PUGI__IS_CHARTYPE(*s, ct_space)) \ - ++s; \ - } -#define PUGI__OPTSET(OPT) (optmsk & (OPT)) -#define PUGI__PUSHNODE(TYPE) \ - { \ - cursor = append_new_node(cursor, alloc, TYPE); \ - if (!cursor) \ - PUGI__THROW_ERROR(status_out_of_memory, s); \ - } -#define PUGI__POPNODE() \ - { cursor = cursor->parent; } -#define PUGI__SCANFOR(X) \ - { \ - while (*s != 0 && !(X)) \ - ++s; \ - } -#define PUGI__SCANWHILE(X) \ - { \ - while (X) \ - ++s; \ - } -#define PUGI__SCANWHILE_UNROLL(X) \ - { \ - for (;;) { \ - char_t ss = s[0]; \ - if (PUGI__UNLIKELY(!(X))) { \ - break; \ - } \ - ss = s[1]; \ - if (PUGI__UNLIKELY(!(X))) { \ - s += 1; \ - break; \ - } \ - ss = s[2]; \ - if (PUGI__UNLIKELY(!(X))) { \ - s += 2; \ - break; \ - } \ - ss = s[3]; \ - if (PUGI__UNLIKELY(!(X))) { \ - s += 3; \ - break; \ - } \ - s += 4; \ - } \ - } -#define PUGI__ENDSEG() \ - { \ - ch = *s; \ - *s = 0; \ - ++s; \ - } -#define PUGI__THROW_ERROR(err, m) \ - return error_offset = m, error_status = err, static_cast(0) -#define PUGI__CHECK_ERROR(err, m) \ - { \ - if (*s == 0) \ - PUGI__THROW_ERROR(err, m); \ - } - -PUGI__FN char_t *strconv_comment(char_t *s, char_t endch) { - gap g; - - while (true) { - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_comment)); - - if (*s == '\r') // Either a single 0x0d or 0x0d 0x0a pair - { - *s++ = '\n'; // replace first one with 0x0a - - if (*s == '\n') - g.push(s, 1); - } else if (s[0] == '-' && s[1] == '-' && - PUGI__ENDSWITH(s[2], '>')) // comment ends here - { - *g.flush(s) = 0; - - return s + (s[2] == '>' ? 3 : 2); - } else if (*s == 0) { - return 0; - } else - ++s; - } -} - -PUGI__FN char_t *strconv_cdata(char_t *s, char_t endch) { - gap g; - - while (true) { - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_cdata)); - - if (*s == '\r') // Either a single 0x0d or 0x0d 0x0a pair - { - *s++ = '\n'; // replace first one with 0x0a - - if (*s == '\n') - g.push(s, 1); - } else if (s[0] == ']' && s[1] == ']' && - PUGI__ENDSWITH(s[2], '>')) // CDATA ends here - { - *g.flush(s) = 0; - - return s + 1; - } else if (*s == 0) { - return 0; - } else - ++s; - } -} - -typedef char_t *(*strconv_pcdata_t)(char_t *); - -template -struct strconv_pcdata_impl { - static char_t *parse(char_t *s) { - gap g; - - char_t *begin = s; - - while (true) { - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_pcdata)); - - if (*s == '<') // PCDATA ends here - { - char_t *end = g.flush(s); - - if (opt_trim::value) - while (end > begin && PUGI__IS_CHARTYPE(end[-1], ct_space)) - --end; - - *end = 0; - - return s + 1; - } else if (opt_eol::value && - *s == '\r') // Either a single 0x0d or 0x0d 0x0a pair - { - *s++ = '\n'; // replace first one with 0x0a - - if (*s == '\n') - g.push(s, 1); - } else if (opt_escape::value && *s == '&') { - s = strconv_escape(s, g); - } else if (*s == 0) { - char_t *end = g.flush(s); - - if (opt_trim::value) - while (end > begin && PUGI__IS_CHARTYPE(end[-1], ct_space)) - --end; - - *end = 0; - - return s; - } else - ++s; - } - } -}; - -PUGI__FN strconv_pcdata_t get_strconv_pcdata(unsigned int optmask) { - PUGI__STATIC_ASSERT(parse_escapes == 0x10 && parse_eol == 0x20 && - parse_trim_pcdata == 0x0800); - - switch (((optmask >> 4) & 3) | - ((optmask >> 9) & 4)) // get bitmask for flags (eol escapes trim) - { - case 0: - return strconv_pcdata_impl::parse; - case 1: - return strconv_pcdata_impl::parse; - case 2: - return strconv_pcdata_impl::parse; - case 3: - return strconv_pcdata_impl::parse; - case 4: - return strconv_pcdata_impl::parse; - case 5: - return strconv_pcdata_impl::parse; - case 6: - return strconv_pcdata_impl::parse; - case 7: - return strconv_pcdata_impl::parse; - default: - assert(false); - return 0; // should not get here - } -} - -typedef char_t *(*strconv_attribute_t)(char_t *, char_t); - -template struct strconv_attribute_impl { - static char_t *parse_wnorm(char_t *s, char_t end_quote) { - gap g; - - // trim leading whitespaces - if (PUGI__IS_CHARTYPE(*s, ct_space)) { - char_t *str = s; - - do - ++str; - while (PUGI__IS_CHARTYPE(*str, ct_space)); - - g.push(s, str - s); - } - - while (true) { - PUGI__SCANWHILE_UNROLL( - !PUGI__IS_CHARTYPE(ss, ct_parse_attr_ws | ct_space)); - - if (*s == end_quote) { - char_t *str = g.flush(s); - - do - *str-- = 0; - while (PUGI__IS_CHARTYPE(*str, ct_space)); - - return s + 1; - } else if (PUGI__IS_CHARTYPE(*s, ct_space)) { - *s++ = ' '; - - if (PUGI__IS_CHARTYPE(*s, ct_space)) { - char_t *str = s + 1; - while (PUGI__IS_CHARTYPE(*str, ct_space)) - ++str; - - g.push(s, str - s); - } - } else if (opt_escape::value && *s == '&') { - s = strconv_escape(s, g); - } else if (!*s) { - return 0; - } else - ++s; - } - } - - static char_t *parse_wconv(char_t *s, char_t end_quote) { - gap g; - - while (true) { - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr_ws)); - - if (*s == end_quote) { - *g.flush(s) = 0; - - return s + 1; - } else if (PUGI__IS_CHARTYPE(*s, ct_space)) { - if (*s == '\r') { - *s++ = ' '; - - if (*s == '\n') - g.push(s, 1); - } else - *s++ = ' '; - } else if (opt_escape::value && *s == '&') { - s = strconv_escape(s, g); - } else if (!*s) { - return 0; - } else - ++s; - } - } - - static char_t *parse_eol(char_t *s, char_t end_quote) { - gap g; - - while (true) { - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr)); - - if (*s == end_quote) { - *g.flush(s) = 0; - - return s + 1; - } else if (*s == '\r') { - *s++ = '\n'; - - if (*s == '\n') - g.push(s, 1); - } else if (opt_escape::value && *s == '&') { - s = strconv_escape(s, g); - } else if (!*s) { - return 0; - } else - ++s; - } - } - - static char_t *parse_simple(char_t *s, char_t end_quote) { - gap g; - - while (true) { - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPE(ss, ct_parse_attr)); - - if (*s == end_quote) { - *g.flush(s) = 0; - - return s + 1; - } else if (opt_escape::value && *s == '&') { - s = strconv_escape(s, g); - } else if (!*s) { - return 0; - } else - ++s; - } - } -}; - -PUGI__FN strconv_attribute_t get_strconv_attribute(unsigned int optmask) { - PUGI__STATIC_ASSERT(parse_escapes == 0x10 && parse_eol == 0x20 && - parse_wconv_attribute == 0x40 && - parse_wnorm_attribute == 0x80); - - switch ((optmask >> 4) & - 15) // get bitmask for flags (wconv wnorm eol escapes) - { - case 0: - return strconv_attribute_impl::parse_simple; - case 1: - return strconv_attribute_impl::parse_simple; - case 2: - return strconv_attribute_impl::parse_eol; - case 3: - return strconv_attribute_impl::parse_eol; - case 4: - return strconv_attribute_impl::parse_wconv; - case 5: - return strconv_attribute_impl::parse_wconv; - case 6: - return strconv_attribute_impl::parse_wconv; - case 7: - return strconv_attribute_impl::parse_wconv; - case 8: - return strconv_attribute_impl::parse_wnorm; - case 9: - return strconv_attribute_impl::parse_wnorm; - case 10: - return strconv_attribute_impl::parse_wnorm; - case 11: - return strconv_attribute_impl::parse_wnorm; - case 12: - return strconv_attribute_impl::parse_wnorm; - case 13: - return strconv_attribute_impl::parse_wnorm; - case 14: - return strconv_attribute_impl::parse_wnorm; - case 15: - return strconv_attribute_impl::parse_wnorm; - default: - assert(false); - return 0; // should not get here - } -} - -inline xml_parse_result make_parse_result(xml_parse_status status, - ptrdiff_t offset = 0) { - xml_parse_result result; - result.status = status; - result.offset = offset; - - return result; -} - -struct xml_parser { - xml_allocator alloc; - xml_allocator *alloc_state; - char_t *error_offset; - xml_parse_status error_status; - - xml_parser(xml_allocator *alloc_) - : alloc(*alloc_), alloc_state(alloc_), error_offset(0), - error_status(status_ok) {} - - ~xml_parser() { *alloc_state = alloc; } - - // DOCTYPE consists of nested sections of the following possible types: - // , , "...", '...' - // - // - // First group can not contain nested groups - // Second group can contain nested groups of the same type - // Third group can contain all other groups - char_t *parse_doctype_primitive(char_t *s) { - if (*s == '"' || *s == '\'') { - // quoted string - char_t ch = *s++; - PUGI__SCANFOR(*s == ch); - if (!*s) - PUGI__THROW_ERROR(status_bad_doctype, s); - - s++; - } else if (s[0] == '<' && s[1] == '?') { - // - s += 2; - PUGI__SCANFOR(s[0] == '?' && - s[1] == '>'); // no need for ENDSWITH because ?> can't - // terminate proper doctype - if (!*s) - PUGI__THROW_ERROR(status_bad_doctype, s); - - s += 2; - } else if (s[0] == '<' && s[1] == '!' && s[2] == '-' && s[3] == '-') { - s += 4; - PUGI__SCANFOR(s[0] == '-' && s[1] == '-' && - s[2] == '>'); // no need for ENDSWITH because --> can't - // terminate proper doctype - if (!*s) - PUGI__THROW_ERROR(status_bad_doctype, s); - - s += 3; - } else - PUGI__THROW_ERROR(status_bad_doctype, s); - - return s; - } - - char_t *parse_doctype_ignore(char_t *s) { - size_t depth = 0; - - assert(s[0] == '<' && s[1] == '!' && s[2] == '['); - s += 3; - - while (*s) { - if (s[0] == '<' && s[1] == '!' && s[2] == '[') { - // nested ignore section - s += 3; - depth++; - } else if (s[0] == ']' && s[1] == ']' && s[2] == '>') { - // ignore section end - s += 3; - - if (depth == 0) - return s; - - depth--; - } else - s++; - } - - PUGI__THROW_ERROR(status_bad_doctype, s); - } - - char_t *parse_doctype_group(char_t *s, char_t endch) { - size_t depth = 0; - - assert((s[0] == '<' || s[0] == 0) && s[1] == '!'); - s += 2; - - while (*s) { - if (s[0] == '<' && s[1] == '!' && s[2] != '-') { - if (s[2] == '[') { - // ignore - s = parse_doctype_ignore(s); - if (!s) - return s; - } else { - // some control group - s += 2; - depth++; - } - } else if (s[0] == '<' || s[0] == '"' || s[0] == '\'') { - // unknown tag (forbidden), or some primitive group - s = parse_doctype_primitive(s); - if (!s) - return s; - } else if (*s == '>') { - if (depth == 0) - return s; - - depth--; - s++; - } else - s++; - } - - if (depth != 0 || endch != '>') - PUGI__THROW_ERROR(status_bad_doctype, s); - - return s; - } - - char_t *parse_exclamation(char_t *s, xml_node_struct *cursor, - unsigned int optmsk, char_t endch) { - // parse node contents, starting with exclamation mark - ++s; - - if (*s == '-') // 'value = s; // Save the offset. - } - - if (PUGI__OPTSET(parse_eol) && PUGI__OPTSET(parse_comments)) { - s = strconv_comment(s, endch); - - if (!s) - PUGI__THROW_ERROR(status_bad_comment, cursor->value); - } else { - // Scan for terminating '-->'. - PUGI__SCANFOR(s[0] == '-' && s[1] == '-' && - PUGI__ENDSWITH(s[2], '>')); - PUGI__CHECK_ERROR(status_bad_comment, s); - - if (PUGI__OPTSET(parse_comments)) - *s = 0; // Zero-terminate this segment at the first terminating '-'. - - s += (s[2] == '>' ? 3 : 2); // Step over the '\0->'. - } - } else - PUGI__THROW_ERROR(status_bad_comment, s); - } else if (*s == '[') { - // 'value = s; // Save the offset. - - if (PUGI__OPTSET(parse_eol)) { - s = strconv_cdata(s, endch); - - if (!s) - PUGI__THROW_ERROR(status_bad_cdata, cursor->value); - } else { - // Scan for terminating ']]>'. - PUGI__SCANFOR(s[0] == ']' && s[1] == ']' && - PUGI__ENDSWITH(s[2], '>')); - PUGI__CHECK_ERROR(status_bad_cdata, s); - - *s++ = 0; // Zero-terminate this segment. - } - } else // Flagged for discard, but we still have to scan for the - // terminator. - { - // Scan for terminating ']]>'. - PUGI__SCANFOR(s[0] == ']' && s[1] == ']' && - PUGI__ENDSWITH(s[2], '>')); - PUGI__CHECK_ERROR(status_bad_cdata, s); - - ++s; - } - - s += (s[1] == '>' ? 2 : 1); // Step over the last ']>'. - } else - PUGI__THROW_ERROR(status_bad_cdata, s); - } else if (s[0] == 'D' && s[1] == 'O' && s[2] == 'C' && s[3] == 'T' && - s[4] == 'Y' && s[5] == 'P' && PUGI__ENDSWITH(s[6], 'E')) { - s -= 2; - - if (cursor->parent) - PUGI__THROW_ERROR(status_bad_doctype, s); - - char_t *mark = s + 9; - - s = parse_doctype_group(s, endch); - if (!s) - return s; - - assert((*s == 0 && endch == '>') || *s == '>'); - if (*s) - *s++ = 0; - - if (PUGI__OPTSET(parse_doctype)) { - while (PUGI__IS_CHARTYPE(*mark, ct_space)) - ++mark; - - PUGI__PUSHNODE(node_doctype); - - cursor->value = mark; - } - } else if (*s == 0 && endch == '-') - PUGI__THROW_ERROR(status_bad_comment, s); - else if (*s == 0 && endch == '[') - PUGI__THROW_ERROR(status_bad_cdata, s); - else - PUGI__THROW_ERROR(status_unrecognized_tag, s); - - return s; - } - - char_t *parse_question(char_t *s, xml_node_struct *&ref_cursor, - unsigned int optmsk, char_t endch) { - // load into registers - xml_node_struct *cursor = ref_cursor; - char_t ch = 0; - - // parse node contents, starting with question mark - ++s; - - // read PI target - char_t *target = s; - - if (!PUGI__IS_CHARTYPE(*s, ct_start_symbol)) - PUGI__THROW_ERROR(status_bad_pi, s); - - PUGI__SCANWHILE(PUGI__IS_CHARTYPE(*s, ct_symbol)); - PUGI__CHECK_ERROR(status_bad_pi, s); - - // determine node type; stricmp / strcasecmp is not portable - bool declaration = (target[0] | ' ') == 'x' && (target[1] | ' ') == 'm' && - (target[2] | ' ') == 'l' && target + 3 == s; - - if (declaration ? PUGI__OPTSET(parse_declaration) - : PUGI__OPTSET(parse_pi)) { - if (declaration) { - // disallow non top-level declarations - if (cursor->parent) - PUGI__THROW_ERROR(status_bad_pi, s); - - PUGI__PUSHNODE(node_declaration); - } else { - PUGI__PUSHNODE(node_pi); - } - - cursor->name = target; - - PUGI__ENDSEG(); - - // parse value/attributes - if (ch == '?') { - // empty node - if (!PUGI__ENDSWITH(*s, '>')) - PUGI__THROW_ERROR(status_bad_pi, s); - s += (*s == '>'); - - PUGI__POPNODE(); - } else if (PUGI__IS_CHARTYPE(ch, ct_space)) { - PUGI__SKIPWS(); - - // scan for tag end - char_t *value = s; - - PUGI__SCANFOR(s[0] == '?' && PUGI__ENDSWITH(s[1], '>')); - PUGI__CHECK_ERROR(status_bad_pi, s); - - if (declaration) { - // replace ending ? with / so that 'element' terminates properly - *s = '/'; - - // we exit from this function with cursor at node_declaration, which - // is a signal to parse() to go to LOC_ATTRIBUTES - s = value; - } else { - // store value and step over > - cursor->value = value; - - PUGI__POPNODE(); - - PUGI__ENDSEG(); - - s += (*s == '>'); - } - } else - PUGI__THROW_ERROR(status_bad_pi, s); - } else { - // scan for tag end - PUGI__SCANFOR(s[0] == '?' && PUGI__ENDSWITH(s[1], '>')); - PUGI__CHECK_ERROR(status_bad_pi, s); - - s += (s[1] == '>' ? 2 : 1); - } - - // store from registers - ref_cursor = cursor; - - return s; - } - - char_t *parse_tree(char_t *s, xml_node_struct *root, unsigned int optmsk, - char_t endch) { - strconv_attribute_t strconv_attribute = get_strconv_attribute(optmsk); - strconv_pcdata_t strconv_pcdata = get_strconv_pcdata(optmsk); - - char_t ch = 0; - xml_node_struct *cursor = root; - char_t *mark = s; - - while (*s != 0) { - if (*s == '<') { - ++s; - - LOC_TAG: - if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) // '<#...' - { - PUGI__PUSHNODE(node_element); // Append a new node to the tree. - - cursor->name = s; - - PUGI__SCANWHILE_UNROLL( - PUGI__IS_CHARTYPE(ss, ct_symbol)); // Scan for a terminator. - PUGI__ENDSEG(); // Save char in 'ch', terminate & step over. - - if (ch == '>') { - // end of tag - } else if (PUGI__IS_CHARTYPE(ch, ct_space)) { - LOC_ATTRIBUTES: - while (true) { - PUGI__SKIPWS(); // Eat any whitespace. - - if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) // <... #... - { - xml_attribute_struct *a = append_new_attribute( - cursor, alloc); // Make space for this attribute. - if (!a) - PUGI__THROW_ERROR(status_out_of_memory, s); - - a->name = s; // Save the offset. - - PUGI__SCANWHILE_UNROLL( - PUGI__IS_CHARTYPE(ss, ct_symbol)); // Scan for a terminator. - PUGI__ENDSEG(); // Save char in 'ch', terminate & step over. - - if (PUGI__IS_CHARTYPE(ch, ct_space)) { - PUGI__SKIPWS(); // Eat any whitespace. - - ch = *s; - ++s; - } - - if (ch == '=') // '<... #=...' - { - PUGI__SKIPWS(); // Eat any whitespace. - - if (*s == '"' || *s == '\'') // '<... #="...' - { - ch = *s; // Save quote char to avoid breaking on "''" -or- - // '""'. - ++s; // Step over the quote. - a->value = s; // Save the offset. - - s = strconv_attribute(s, ch); - - if (!s) - PUGI__THROW_ERROR(status_bad_attribute, a->value); - - // After this line the loop continues from the start; - // Whitespaces, / and > are ok, symbols and EOF are wrong, - // everything else will be detected - if (PUGI__IS_CHARTYPE(*s, ct_start_symbol)) - PUGI__THROW_ERROR(status_bad_attribute, s); - } else - PUGI__THROW_ERROR(status_bad_attribute, s); - } else - PUGI__THROW_ERROR(status_bad_attribute, s); - } else if (*s == '/') { - ++s; - - if (*s == '>') { - PUGI__POPNODE(); - s++; - break; - } else if (*s == 0 && endch == '>') { - PUGI__POPNODE(); - break; - } else - PUGI__THROW_ERROR(status_bad_start_element, s); - } else if (*s == '>') { - ++s; - - break; - } else if (*s == 0 && endch == '>') { - break; - } else - PUGI__THROW_ERROR(status_bad_start_element, s); - } - - // !!! - } else if (ch == '/') // '<#.../' - { - if (!PUGI__ENDSWITH(*s, '>')) - PUGI__THROW_ERROR(status_bad_start_element, s); - - PUGI__POPNODE(); // Pop. - - s += (*s == '>'); - } else if (ch == 0) { - // we stepped over null terminator, backtrack & handle closing tag - --s; - - if (endch != '>') - PUGI__THROW_ERROR(status_bad_start_element, s); - } else - PUGI__THROW_ERROR(status_bad_start_element, s); - } else if (*s == '/') { - ++s; - - char_t *name = cursor->name; - if (!name) - PUGI__THROW_ERROR(status_end_element_mismatch, s); - - while (PUGI__IS_CHARTYPE(*s, ct_symbol)) { - if (*s++ != *name++) - PUGI__THROW_ERROR(status_end_element_mismatch, s); - } - - if (*name) { - if (*s == 0 && name[0] == endch && name[1] == 0) - PUGI__THROW_ERROR(status_bad_end_element, s); - else - PUGI__THROW_ERROR(status_end_element_mismatch, s); - } - - PUGI__POPNODE(); // Pop. - - PUGI__SKIPWS(); - - if (*s == 0) { - if (endch != '>') - PUGI__THROW_ERROR(status_bad_end_element, s); - } else { - if (*s != '>') - PUGI__THROW_ERROR(status_bad_end_element, s); - ++s; - } - } else if (*s == '?') // 'first_child) - continue; - } - } - - if (!PUGI__OPTSET(parse_trim_pcdata)) - s = mark; - - if (cursor->parent || PUGI__OPTSET(parse_fragment)) { - PUGI__PUSHNODE(node_pcdata); // Append a new node on the tree. - cursor->value = s; // Save the offset. - - s = strconv_pcdata(s); - - PUGI__POPNODE(); // Pop since this is a standalone. - - if (!*s) - break; - } else { - PUGI__SCANFOR(*s == '<'); // '...<' - if (!*s) - break; - - ++s; - } - - // We're after '<' - goto LOC_TAG; - } - } - - // check that last tag is closed - if (cursor != root) - PUGI__THROW_ERROR(status_end_element_mismatch, s); - - return s; - } - -#ifdef PUGIXML_WCHAR_MODE - static char_t *parse_skip_bom(char_t *s) { - unsigned int bom = 0xfeff; - return (s[0] == static_cast(bom)) ? s + 1 : s; - } -#else - static char_t *parse_skip_bom(char_t *s) { - return (s[0] == '\xef' && s[1] == '\xbb' && s[2] == '\xbf') ? s + 3 : s; - } -#endif - - static bool has_element_node_siblings(xml_node_struct *node) { - while (node) { - if (PUGI__NODETYPE(node) == node_element) - return true; - - node = node->next_sibling; - } - - return false; - } - - static xml_parse_result parse(char_t *buffer, size_t length, - xml_document_struct *xmldoc, - xml_node_struct *root, unsigned int optmsk) { - // early-out for empty documents - if (length == 0) - return make_parse_result(PUGI__OPTSET(parse_fragment) - ? status_ok - : status_no_document_element); - - // get last child of the root before parsing - xml_node_struct *last_root_child = - root->first_child ? root->first_child->prev_sibling_c + 0 : 0; - - // create parser on stack - xml_parser parser(static_cast(xmldoc)); - - // save last character and make buffer zero-terminated (speeds up parsing) - char_t endch = buffer[length - 1]; - buffer[length - 1] = 0; - - // skip BOM to make sure it does not end up as part of parse output - char_t *buffer_data = parse_skip_bom(buffer); - - // perform actual parsing - parser.parse_tree(buffer_data, root, optmsk, endch); - - xml_parse_result result = make_parse_result( - parser.error_status, - parser.error_offset ? parser.error_offset - buffer : 0); - assert(result.offset >= 0 && static_cast(result.offset) <= length); - - if (result) { - // since we removed last character, we have to handle the only possible - // false positive (stray <) - if (endch == '<') - return make_parse_result(status_unrecognized_tag, length - 1); - - // check if there are any element nodes parsed - xml_node_struct *first_root_child_parsed = - last_root_child ? last_root_child->next_sibling + 0 - : root->first_child + 0; - - if (!PUGI__OPTSET(parse_fragment) && - !has_element_node_siblings(first_root_child_parsed)) - return make_parse_result(status_no_document_element, length - 1); - } else { - // roll back offset if it occurs on a null terminator in the source buffer - if (result.offset > 0 && - static_cast(result.offset) == length - 1 && endch == 0) - result.offset--; - } - - return result; - } -}; - -// Output facilities -PUGI__FN xml_encoding get_write_native_encoding() { -#ifdef PUGIXML_WCHAR_MODE - return get_wchar_encoding(); -#else - return encoding_utf8; -#endif -} - -PUGI__FN xml_encoding get_write_encoding(xml_encoding encoding) { - // replace wchar encoding with utf implementation - if (encoding == encoding_wchar) - return get_wchar_encoding(); - - // replace utf16 encoding with utf16 with specific endianness - if (encoding == encoding_utf16) - return is_little_endian() ? encoding_utf16_le : encoding_utf16_be; - - // replace utf32 encoding with utf32 with specific endianness - if (encoding == encoding_utf32) - return is_little_endian() ? encoding_utf32_le : encoding_utf32_be; - - // only do autodetection if no explicit encoding is requested - if (encoding != encoding_auto) - return encoding; - - // assume utf8 encoding - return encoding_utf8; -} - -template -PUGI__FN size_t convert_buffer_output_generic(typename T::value_type dest, - const char_t *data, size_t length, - D, T) { - PUGI__STATIC_ASSERT(sizeof(char_t) == sizeof(typename D::type)); - - typename T::value_type end = D::process( - reinterpret_cast(data), length, dest, T()); - - return static_cast(end - dest) * sizeof(*dest); -} - -template -PUGI__FN size_t convert_buffer_output_generic(typename T::value_type dest, - const char_t *data, size_t length, - D, T, bool opt_swap) { - PUGI__STATIC_ASSERT(sizeof(char_t) == sizeof(typename D::type)); - - typename T::value_type end = D::process( - reinterpret_cast(data), length, dest, T()); - - if (opt_swap) { - for (typename T::value_type i = dest; i != end; ++i) - *i = endian_swap(*i); - } - - return static_cast(end - dest) * sizeof(*dest); -} - -#ifdef PUGIXML_WCHAR_MODE -PUGI__FN size_t get_valid_length(const char_t *data, size_t length) { - if (length < 1) - return 0; - - // discard last character if it's the lead of a surrogate pair - return (sizeof(wchar_t) == 2 && - static_cast(static_cast(data[length - 1]) - - 0xD800) < 0x400) - ? length - 1 - : length; -} - -PUGI__FN size_t convert_buffer_output(char_t *r_char, uint8_t *r_u8, - uint16_t *r_u16, uint32_t *r_u32, - const char_t *data, size_t length, - xml_encoding encoding) { - // only endian-swapping is required - if (need_endian_swap_utf(encoding, get_wchar_encoding())) { - convert_wchar_endian_swap(r_char, data, length); - - return length * sizeof(char_t); - } - - // convert to utf8 - if (encoding == encoding_utf8) - return convert_buffer_output_generic(r_u8, data, length, wchar_decoder(), - utf8_writer()); - - // convert to utf16 - if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf16_le : encoding_utf16_be; - - return convert_buffer_output_generic(r_u16, data, length, wchar_decoder(), - utf16_writer(), - native_encoding != encoding); - } - - // convert to utf32 - if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf32_le : encoding_utf32_be; - - return convert_buffer_output_generic(r_u32, data, length, wchar_decoder(), - utf32_writer(), - native_encoding != encoding); - } - - // convert to latin1 - if (encoding == encoding_latin1) - return convert_buffer_output_generic(r_u8, data, length, wchar_decoder(), - latin1_writer()); - - assert(!"Invalid encoding"); - return 0; -} -#else -PUGI__FN size_t get_valid_length(const char_t *data, size_t length) { - if (length < 5) - return 0; - - for (size_t i = 1; i <= 4; ++i) { - uint8_t ch = static_cast(data[length - i]); - - // either a standalone character or a leading one - if ((ch & 0xc0) != 0x80) - return length - i; - } - - // there are four non-leading characters at the end, sequence tail is broken - // so might as well process the whole chunk - return length; -} - -PUGI__FN size_t convert_buffer_output(char_t * /* r_char */, uint8_t *r_u8, - uint16_t *r_u16, uint32_t *r_u32, - const char_t *data, size_t length, - xml_encoding encoding) { - if (encoding == encoding_utf16_be || encoding == encoding_utf16_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf16_le : encoding_utf16_be; - - return convert_buffer_output_generic(r_u16, data, length, utf8_decoder(), - utf16_writer(), - native_encoding != encoding); - } - - if (encoding == encoding_utf32_be || encoding == encoding_utf32_le) { - xml_encoding native_encoding = - is_little_endian() ? encoding_utf32_le : encoding_utf32_be; - - return convert_buffer_output_generic(r_u32, data, length, utf8_decoder(), - utf32_writer(), - native_encoding != encoding); - } - - if (encoding == encoding_latin1) - return convert_buffer_output_generic(r_u8, data, length, utf8_decoder(), - latin1_writer()); - - assert(!"Invalid encoding"); - return 0; -} -#endif - -class xml_buffered_writer { - xml_buffered_writer(const xml_buffered_writer &); - xml_buffered_writer &operator=(const xml_buffered_writer &); - -public: - xml_buffered_writer(xml_writer &writer_, xml_encoding user_encoding) - : writer(writer_), bufsize(0), - encoding(get_write_encoding(user_encoding)) { - PUGI__STATIC_ASSERT(bufcapacity >= 8); - } - - size_t flush() { - flush(buffer, bufsize); - bufsize = 0; - return 0; - } - - void flush(const char_t *data, size_t size) { - if (size == 0) - return; - - // fast path, just write data - if (encoding == get_write_native_encoding()) - writer.write(data, size * sizeof(char_t)); - else { - // convert chunk - size_t result = convert_buffer_output(scratch.data_char, scratch.data_u8, - scratch.data_u16, scratch.data_u32, - data, size, encoding); - assert(result <= sizeof(scratch)); - - // write data - writer.write(scratch.data_u8, result); - } - } - - void write_direct(const char_t *data, size_t length) { - // flush the remaining buffer contents - flush(); - - // handle large chunks - if (length > bufcapacity) { - if (encoding == get_write_native_encoding()) { - // fast path, can just write data chunk - writer.write(data, length * sizeof(char_t)); - return; - } - - // need to convert in suitable chunks - while (length > bufcapacity) { - // get chunk size by selecting such number of characters that are - // guaranteed to fit into scratch buffer and form a complete codepoint - // sequence (i.e. discard start of last codepoint if necessary) - size_t chunk_size = get_valid_length(data, bufcapacity); - assert(chunk_size); - - // convert chunk and write - flush(data, chunk_size); - - // iterate - data += chunk_size; - length -= chunk_size; - } - - // small tail is copied below - bufsize = 0; - } - - memcpy(buffer + bufsize, data, length * sizeof(char_t)); - bufsize += length; - } - - void write_buffer(const char_t *data, size_t length) { - size_t offset = bufsize; - - if (offset + length <= bufcapacity) { - memcpy(buffer + offset, data, length * sizeof(char_t)); - bufsize = offset + length; - } else { - write_direct(data, length); - } - } - - void write_string(const char_t *data) { - // write the part of the string that fits in the buffer - size_t offset = bufsize; - - while (*data && offset < bufcapacity) - buffer[offset++] = *data++; - - // write the rest - if (offset < bufcapacity) { - bufsize = offset; - } else { - // backtrack a bit if we have split the codepoint - size_t length = offset - bufsize; - size_t extra = length - get_valid_length(data - length, length); - - bufsize = offset - extra; - - write_direct(data - extra, strlength(data) + extra); - } - } - - void write(char_t d0) { - size_t offset = bufsize; - if (offset > bufcapacity - 1) - offset = flush(); - - buffer[offset + 0] = d0; - bufsize = offset + 1; - } - - void write(char_t d0, char_t d1) { - size_t offset = bufsize; - if (offset > bufcapacity - 2) - offset = flush(); - - buffer[offset + 0] = d0; - buffer[offset + 1] = d1; - bufsize = offset + 2; - } - - void write(char_t d0, char_t d1, char_t d2) { - size_t offset = bufsize; - if (offset > bufcapacity - 3) - offset = flush(); - - buffer[offset + 0] = d0; - buffer[offset + 1] = d1; - buffer[offset + 2] = d2; - bufsize = offset + 3; - } - - void write(char_t d0, char_t d1, char_t d2, char_t d3) { - size_t offset = bufsize; - if (offset > bufcapacity - 4) - offset = flush(); - - buffer[offset + 0] = d0; - buffer[offset + 1] = d1; - buffer[offset + 2] = d2; - buffer[offset + 3] = d3; - bufsize = offset + 4; - } - - void write(char_t d0, char_t d1, char_t d2, char_t d3, char_t d4) { - size_t offset = bufsize; - if (offset > bufcapacity - 5) - offset = flush(); - - buffer[offset + 0] = d0; - buffer[offset + 1] = d1; - buffer[offset + 2] = d2; - buffer[offset + 3] = d3; - buffer[offset + 4] = d4; - bufsize = offset + 5; - } - - void write(char_t d0, char_t d1, char_t d2, char_t d3, char_t d4, char_t d5) { - size_t offset = bufsize; - if (offset > bufcapacity - 6) - offset = flush(); - - buffer[offset + 0] = d0; - buffer[offset + 1] = d1; - buffer[offset + 2] = d2; - buffer[offset + 3] = d3; - buffer[offset + 4] = d4; - buffer[offset + 5] = d5; - bufsize = offset + 6; - } - - // utf8 maximum expansion: x4 (-> utf32) - // utf16 maximum expansion: x2 (-> utf32) - // utf32 maximum expansion: x1 - enum { - bufcapacitybytes = -#ifdef PUGIXML_MEMORY_OUTPUT_STACK - PUGIXML_MEMORY_OUTPUT_STACK -#else - 10240 -#endif - , - bufcapacity = bufcapacitybytes / (sizeof(char_t) + 4) - }; - - char_t buffer[bufcapacity]; - - union { - uint8_t data_u8[4 * bufcapacity]; - uint16_t data_u16[2 * bufcapacity]; - uint32_t data_u32[bufcapacity]; - char_t data_char[bufcapacity]; - } scratch; - - xml_writer &writer; - size_t bufsize; - xml_encoding encoding; -}; - -PUGI__FN void text_output_escaped(xml_buffered_writer &writer, const char_t *s, - chartypex_t type) { - while (*s) { - const char_t *prev = s; - - // While *s is a usual symbol - PUGI__SCANWHILE_UNROLL(!PUGI__IS_CHARTYPEX(ss, type)); - - writer.write_buffer(prev, static_cast(s - prev)); - - switch (*s) { - case 0: - break; - case '&': - writer.write('&', 'a', 'm', 'p', ';'); - ++s; - break; - case '<': - writer.write('&', 'l', 't', ';'); - ++s; - break; - case '>': - writer.write('&', 'g', 't', ';'); - ++s; - break; - case '"': - writer.write('&', 'q', 'u', 'o', 't', ';'); - ++s; - break; - default: // s is not a usual symbol - { - unsigned int ch = static_cast(*s++); - assert(ch < 32); - - writer.write('&', '#', static_cast((ch / 10) + '0'), - static_cast((ch % 10) + '0'), ';'); - } - } - } -} - -PUGI__FN void text_output(xml_buffered_writer &writer, const char_t *s, - chartypex_t type, unsigned int flags) { - if (flags & format_no_escapes) - writer.write_string(s); - else - text_output_escaped(writer, s, type); -} - -PUGI__FN void text_output_cdata(xml_buffered_writer &writer, const char_t *s) { - do { - writer.write('<', '!', '[', 'C', 'D'); - writer.write('A', 'T', 'A', '['); - - const char_t *prev = s; - - // look for ]]> sequence - we can't output it as is since it terminates - // CDATA - while (*s && !(s[0] == ']' && s[1] == ']' && s[2] == '>')) - ++s; - - // skip ]] if we stopped at ]]>, > will go to the next CDATA section - if (*s) - s += 2; - - writer.write_buffer(prev, static_cast(s - prev)); - - writer.write(']', ']', '>'); - } while (*s); -} - -PUGI__FN void text_output_indent(xml_buffered_writer &writer, - const char_t *indent, size_t indent_length, - unsigned int depth) { - switch (indent_length) { - case 1: { - for (unsigned int i = 0; i < depth; ++i) - writer.write(indent[0]); - break; - } - - case 2: { - for (unsigned int i = 0; i < depth; ++i) - writer.write(indent[0], indent[1]); - break; - } - - case 3: { - for (unsigned int i = 0; i < depth; ++i) - writer.write(indent[0], indent[1], indent[2]); - break; - } - - case 4: { - for (unsigned int i = 0; i < depth; ++i) - writer.write(indent[0], indent[1], indent[2], indent[3]); - break; - } - - default: { - for (unsigned int i = 0; i < depth; ++i) - writer.write_buffer(indent, indent_length); - } - } -} - -PUGI__FN void node_output_comment(xml_buffered_writer &writer, - const char_t *s) { - writer.write('<', '!', '-', '-'); - - while (*s) { - const char_t *prev = s; - - // look for -\0 or -- sequence - we can't output it since -- is illegal in - // comment body - while (*s && !(s[0] == '-' && (s[1] == '-' || s[1] == 0))) - ++s; - - writer.write_buffer(prev, static_cast(s - prev)); - - if (*s) { - assert(*s == '-'); - - writer.write('-', ' '); - ++s; - } - } - - writer.write('-', '-', '>'); -} - -PUGI__FN void node_output_pi_value(xml_buffered_writer &writer, - const char_t *s) { - while (*s) { - const char_t *prev = s; - - // look for ?> sequence - we can't output it since ?> terminates PI - while (*s && !(s[0] == '?' && s[1] == '>')) - ++s; - - writer.write_buffer(prev, static_cast(s - prev)); - - if (*s) { - assert(s[0] == '?' && s[1] == '>'); - - writer.write('?', ' ', '>'); - s += 2; - } - } -} - -PUGI__FN void node_output_attributes(xml_buffered_writer &writer, - xml_node_struct *node, - const char_t *indent, size_t indent_length, - unsigned int flags, unsigned int depth) { - const char_t *default_name = PUGIXML_TEXT(":anonymous"); - - for (xml_attribute_struct *a = node->first_attribute; a; - a = a->next_attribute) { - if ((flags & (format_indent_attributes | format_raw)) == - format_indent_attributes) { - writer.write('\n'); - - text_output_indent(writer, indent, indent_length, depth + 1); - } else { - writer.write(' '); - } - - writer.write_string(a->name ? a->name + 0 : default_name); - writer.write('=', '"'); - - if (a->value) - text_output(writer, a->value, ctx_special_attr, flags); - - writer.write('"'); - } -} - -PUGI__FN bool node_output_start(xml_buffered_writer &writer, - xml_node_struct *node, const char_t *indent, - size_t indent_length, unsigned int flags, - unsigned int depth) { - const char_t *default_name = PUGIXML_TEXT(":anonymous"); - const char_t *name = node->name ? node->name + 0 : default_name; - - writer.write('<'); - writer.write_string(name); - - if (node->first_attribute) - node_output_attributes(writer, node, indent, indent_length, flags, depth); - - if (!node->first_child) { - writer.write(' ', '/', '>'); - - return false; - } else { - writer.write('>'); - - return true; - } -} - -PUGI__FN void node_output_end(xml_buffered_writer &writer, - xml_node_struct *node) { - const char_t *default_name = PUGIXML_TEXT(":anonymous"); - const char_t *name = node->name ? node->name + 0 : default_name; - - writer.write('<', '/'); - writer.write_string(name); - writer.write('>'); -} - -PUGI__FN void node_output_simple(xml_buffered_writer &writer, - xml_node_struct *node, unsigned int flags) { - const char_t *default_name = PUGIXML_TEXT(":anonymous"); - - switch (PUGI__NODETYPE(node)) { - case node_pcdata: - text_output(writer, node->value ? node->value + 0 : PUGIXML_TEXT(""), - ctx_special_pcdata, flags); - break; - - case node_cdata: - text_output_cdata(writer, node->value ? node->value + 0 : PUGIXML_TEXT("")); - break; - - case node_comment: - node_output_comment(writer, - node->value ? node->value + 0 : PUGIXML_TEXT("")); - break; - - case node_pi: - writer.write('<', '?'); - writer.write_string(node->name ? node->name + 0 : default_name); - - if (node->value) { - writer.write(' '); - node_output_pi_value(writer, node->value); - } - - writer.write('?', '>'); - break; - - case node_declaration: - writer.write('<', '?'); - writer.write_string(node->name ? node->name + 0 : default_name); - node_output_attributes(writer, node, PUGIXML_TEXT(""), 0, - flags | format_raw, 0); - writer.write('?', '>'); - break; - - case node_doctype: - writer.write('<', '!', 'D', 'O', 'C'); - writer.write('T', 'Y', 'P', 'E'); - - if (node->value) { - writer.write(' '); - writer.write_string(node->value); - } - - writer.write('>'); - break; - - default: - assert(!"Invalid node type"); - } -} - -enum indent_flags_t { indent_newline = 1, indent_indent = 2 }; - -PUGI__FN void node_output(xml_buffered_writer &writer, xml_node_struct *root, - const char_t *indent, unsigned int flags, - unsigned int depth) { - size_t indent_length = - ((flags & (format_indent | format_indent_attributes)) && - (flags & format_raw) == 0) - ? strlength(indent) - : 0; - unsigned int indent_flags = indent_indent; - - xml_node_struct *node = root; - - do { - assert(node); - - // begin writing current node - if (PUGI__NODETYPE(node) == node_pcdata || - PUGI__NODETYPE(node) == node_cdata) { - node_output_simple(writer, node, flags); - - indent_flags = 0; - } else { - if ((indent_flags & indent_newline) && (flags & format_raw) == 0) - writer.write('\n'); - - if ((indent_flags & indent_indent) && indent_length) - text_output_indent(writer, indent, indent_length, depth); - - if (PUGI__NODETYPE(node) == node_element) { - indent_flags = indent_newline | indent_indent; - - if (node_output_start(writer, node, indent, indent_length, flags, - depth)) { - node = node->first_child; - depth++; - continue; - } - } else if (PUGI__NODETYPE(node) == node_document) { - indent_flags = indent_indent; - - if (node->first_child) { - node = node->first_child; - continue; - } - } else { - node_output_simple(writer, node, flags); - - indent_flags = indent_newline | indent_indent; - } - } - - // continue to the next node - while (node != root) { - if (node->next_sibling) { - node = node->next_sibling; - break; - } - - node = node->parent; - - // write closing node - if (PUGI__NODETYPE(node) == node_element) { - depth--; - - if ((indent_flags & indent_newline) && (flags & format_raw) == 0) - writer.write('\n'); - - if ((indent_flags & indent_indent) && indent_length) - text_output_indent(writer, indent, indent_length, depth); - - node_output_end(writer, node); - - indent_flags = indent_newline | indent_indent; - } - } - } while (node != root); - - if ((indent_flags & indent_newline) && (flags & format_raw) == 0) - writer.write('\n'); -} - -PUGI__FN bool has_declaration(xml_node_struct *node) { - for (xml_node_struct *child = node->first_child; child; - child = child->next_sibling) { - xml_node_type type = PUGI__NODETYPE(child); - - if (type == node_declaration) - return true; - if (type == node_element) - return false; - } - - return false; -} - -PUGI__FN bool is_attribute_of(xml_attribute_struct *attr, - xml_node_struct *node) { - for (xml_attribute_struct *a = node->first_attribute; a; - a = a->next_attribute) - if (a == attr) - return true; - - return false; -} - -PUGI__FN bool allow_insert_attribute(xml_node_type parent) { - return parent == node_element || parent == node_declaration; -} - -PUGI__FN bool allow_insert_child(xml_node_type parent, xml_node_type child) { - if (parent != node_document && parent != node_element) - return false; - if (child == node_document || child == node_null) - return false; - if (parent != node_document && - (child == node_declaration || child == node_doctype)) - return false; - - return true; -} - -PUGI__FN bool allow_move(xml_node parent, xml_node child) { - // check that child can be a child of parent - if (!allow_insert_child(parent.type(), child.type())) - return false; - - // check that node is not moved between documents - if (parent.root() != child.root()) - return false; - - // check that new parent is not in the child subtree - xml_node cur = parent; - - while (cur) { - if (cur == child) - return false; - - cur = cur.parent(); - } - - return true; -} - -template -PUGI__FN void node_copy_string(String &dest, Header &header, - uintptr_t header_mask, char_t *source, - Header &source_header, xml_allocator *alloc) { - assert(!dest && (header & header_mask) == 0); - - if (source) { - if (alloc && (source_header & header_mask) == 0) { - dest = source; - - // since strcpy_insitu can reuse document buffer memory we need to mark - // both source and dest as shared - header |= xml_memory_page_contents_shared_mask; - source_header |= xml_memory_page_contents_shared_mask; - } else - strcpy_insitu(dest, header, header_mask, source, strlength(source)); - } -} - -PUGI__FN void node_copy_contents(xml_node_struct *dn, xml_node_struct *sn, - xml_allocator *shared_alloc) { - node_copy_string(dn->name, dn->header, xml_memory_page_name_allocated_mask, - sn->name, sn->header, shared_alloc); - node_copy_string(dn->value, dn->header, xml_memory_page_value_allocated_mask, - sn->value, sn->header, shared_alloc); - - for (xml_attribute_struct *sa = sn->first_attribute; sa; - sa = sa->next_attribute) { - xml_attribute_struct *da = append_new_attribute(dn, get_allocator(dn)); - - if (da) { - node_copy_string(da->name, da->header, - xml_memory_page_name_allocated_mask, sa->name, - sa->header, shared_alloc); - node_copy_string(da->value, da->header, - xml_memory_page_value_allocated_mask, sa->value, - sa->header, shared_alloc); - } - } -} - -PUGI__FN void node_copy_tree(xml_node_struct *dn, xml_node_struct *sn) { - xml_allocator &alloc = get_allocator(dn); - xml_allocator *shared_alloc = (&alloc == &get_allocator(sn)) ? &alloc : 0; - - node_copy_contents(dn, sn, shared_alloc); - - xml_node_struct *dit = dn; - xml_node_struct *sit = sn->first_child; - - while (sit && sit != sn) { - if (sit != dn) { - xml_node_struct *copy = append_new_node(dit, alloc, PUGI__NODETYPE(sit)); - - if (copy) { - node_copy_contents(copy, sit, shared_alloc); - - if (sit->first_child) { - dit = copy; - sit = sit->first_child; - continue; - } - } - } - - // continue to the next node - do { - if (sit->next_sibling) { - sit = sit->next_sibling; - break; - } - - sit = sit->parent; - dit = dit->parent; - } while (sit != sn); - } -} - -PUGI__FN void node_copy_attribute(xml_attribute_struct *da, - xml_attribute_struct *sa) { - xml_allocator &alloc = get_allocator(da); - xml_allocator *shared_alloc = (&alloc == &get_allocator(sa)) ? &alloc : 0; - - node_copy_string(da->name, da->header, xml_memory_page_name_allocated_mask, - sa->name, sa->header, shared_alloc); - node_copy_string(da->value, da->header, xml_memory_page_value_allocated_mask, - sa->value, sa->header, shared_alloc); -} - -inline bool is_text_node(xml_node_struct *node) { - xml_node_type type = PUGI__NODETYPE(node); - - return type == node_pcdata || type == node_cdata; -} - -// get value with conversion functions -template -U string_to_integer(const char_t *value, U minneg, U maxpos) { - U result = 0; - const char_t *s = value; - - while (PUGI__IS_CHARTYPE(*s, ct_space)) - s++; - - bool negative = (*s == '-'); - - s += (*s == '+' || *s == '-'); - - bool overflow = false; - - if (s[0] == '0' && (s[1] | ' ') == 'x') { - s += 2; - - // since overflow detection relies on length of the sequence skip leading - // zeros - while (*s == '0') - s++; - - const char_t *start = s; - - for (;;) { - if (static_cast(*s - '0') < 10) - result = result * 16 + (*s - '0'); - else if (static_cast((*s | ' ') - 'a') < 6) - result = result * 16 + ((*s | ' ') - 'a' + 10); - else - break; - - s++; - } - - size_t digits = static_cast(s - start); - - overflow = digits > sizeof(U) * 2; - } else { - // since overflow detection relies on length of the sequence skip leading - // zeros - while (*s == '0') - s++; - - const char_t *start = s; - - for (;;) { - if (static_cast(*s - '0') < 10) - result = result * 10 + (*s - '0'); - else - break; - - s++; - } - - size_t digits = static_cast(s - start); - - PUGI__STATIC_ASSERT(sizeof(U) == 8 || sizeof(U) == 4 || sizeof(U) == 2); - - const size_t max_digits10 = sizeof(U) == 8 ? 20 : sizeof(U) == 4 ? 10 : 5; - const char_t max_lead = sizeof(U) == 8 ? '1' : sizeof(U) == 4 ? '4' : '6'; - const size_t high_bit = sizeof(U) * 8 - 1; - - overflow = - digits >= max_digits10 && - !(digits == max_digits10 && - (*start < max_lead || (*start == max_lead && result >> high_bit))); - } - - if (negative) - return (overflow || result > minneg) ? 0 - minneg : 0 - result; - else - return (overflow || result > maxpos) ? maxpos : result; -} - -PUGI__FN int get_value_int(const char_t *value) { - return string_to_integer( - value, 0 - static_cast(INT_MIN), INT_MAX); -} - -PUGI__FN unsigned int get_value_uint(const char_t *value) { - return string_to_integer(value, 0, UINT_MAX); -} - -PUGI__FN double get_value_double(const char_t *value) { -#ifdef PUGIXML_WCHAR_MODE - return wcstod(value, 0); -#else - return strtod(value, 0); -#endif -} - -PUGI__FN float get_value_float(const char_t *value) { -#ifdef PUGIXML_WCHAR_MODE - return static_cast(wcstod(value, 0)); -#else - return static_cast(strtod(value, 0)); -#endif -} - -PUGI__FN bool get_value_bool(const char_t *value) { - // only look at first char - char_t first = *value; - - // 1*, t* (true), T* (True), y* (yes), Y* (YES) - return (first == '1' || first == 't' || first == 'T' || first == 'y' || - first == 'Y'); -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN long long get_value_llong(const char_t *value) { - return string_to_integer( - value, 0 - static_cast(LLONG_MIN), LLONG_MAX); -} - -PUGI__FN unsigned long long get_value_ullong(const char_t *value) { - return string_to_integer(value, 0, ULLONG_MAX); -} -#endif - -template -PUGI__FN char_t *integer_to_string(char_t *begin, char_t *end, U value, - bool negative) { - char_t *result = end - 1; - U rest = negative ? 0 - value : value; - - do { - *result-- = static_cast('0' + (rest % 10)); - rest /= 10; - } while (rest); - - assert(result >= begin); - (void)begin; - - *result = '-'; - - return result + !negative; -} - -// set value with conversion functions -template -PUGI__FN bool set_value_ascii(String &dest, Header &header, - uintptr_t header_mask, char *buf) { -#ifdef PUGIXML_WCHAR_MODE - char_t wbuf[128]; - assert(strlen(buf) < sizeof(wbuf) / sizeof(wbuf[0])); - - size_t offset = 0; - for (; buf[offset]; ++offset) - wbuf[offset] = buf[offset]; - - return strcpy_insitu(dest, header, header_mask, wbuf, offset); -#else - return strcpy_insitu(dest, header, header_mask, buf, strlen(buf)); -#endif -} - -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, int value) { - char_t buf[64]; - char_t *end = buf + sizeof(buf) / sizeof(buf[0]); - char_t *begin = integer_to_string(buf, end, value, value < 0); - - return strcpy_insitu(dest, header, header_mask, begin, end - begin); -} - -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, unsigned int value) { - char_t buf[64]; - char_t *end = buf + sizeof(buf) / sizeof(buf[0]); - char_t *begin = integer_to_string(buf, end, value, false); - - return strcpy_insitu(dest, header, header_mask, begin, end - begin); -} - -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, float value) { - char buf[128]; - sprintf(buf, "%.9g", value); - - return set_value_ascii(dest, header, header_mask, buf); -} - -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, double value) { - char buf[128]; - sprintf(buf, "%.17g", value); - - return set_value_ascii(dest, header, header_mask, buf); -} - -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, bool value) { - return strcpy_insitu(dest, header, header_mask, - value ? PUGIXML_TEXT("true") : PUGIXML_TEXT("false"), - value ? 4 : 5); -} - -#ifdef PUGIXML_HAS_LONG_LONG -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, long long value) { - char_t buf[64]; - char_t *end = buf + sizeof(buf) / sizeof(buf[0]); - char_t *begin = - integer_to_string(buf, end, value, value < 0); - - return strcpy_insitu(dest, header, header_mask, begin, end - begin); -} - -template -PUGI__FN bool set_value_convert(String &dest, Header &header, - uintptr_t header_mask, - unsigned long long value) { - char_t buf[64]; - char_t *end = buf + sizeof(buf) / sizeof(buf[0]); - char_t *begin = integer_to_string(buf, end, value, false); - - return strcpy_insitu(dest, header, header_mask, begin, end - begin); -} -#endif - -PUGI__FN xml_parse_result load_buffer_impl( - xml_document_struct *doc, xml_node_struct *root, void *contents, - size_t size, unsigned int options, xml_encoding encoding, bool is_mutable, - bool own, char_t **out_buffer) { - // check input buffer - if (!contents && size) - return make_parse_result(status_io_error); - - // get actual encoding - xml_encoding buffer_encoding = - impl::get_buffer_encoding(encoding, contents, size); - - // get private buffer - char_t *buffer = 0; - size_t length = 0; - - if (!impl::convert_buffer(buffer, length, buffer_encoding, contents, size, - is_mutable)) - return impl::make_parse_result(status_out_of_memory); - - // delete original buffer if we performed a conversion - if (own && buffer != contents && contents) - impl::xml_memory::deallocate(contents); - - // grab onto buffer if it's our buffer, user is responsible for deallocating - // contents himself - if (own || buffer != contents) - *out_buffer = buffer; - - // store buffer for offset_debug - doc->buffer = buffer; - - // parse - xml_parse_result res = - impl::xml_parser::parse(buffer, length, doc, root, options); - - // remember encoding - res.encoding = buffer_encoding; - - return res; -} - -// we need to get length of entire file to load it in memory; the only -// (relatively) sane way to do it is via seek/tell trick -PUGI__FN xml_parse_status get_file_size(FILE *file, size_t &out_result) { -#if defined(PUGI__MSVC_CRT_VERSION) && PUGI__MSVC_CRT_VERSION >= 1400 && \ - !defined(_WIN32_WCE) - // there are 64-bit versions of fseek/ftell, let's use them - typedef __int64 length_type; - - _fseeki64(file, 0, SEEK_END); - length_type length = _ftelli64(file); - _fseeki64(file, 0, SEEK_SET); -#elif defined(__MINGW32__) && !defined(__NO_MINGW_LFS) && \ - (!defined(__STRICT_ANSI__) || defined(__MINGW64_VERSION_MAJOR)) - // there are 64-bit versions of fseek/ftell, let's use them - typedef off64_t length_type; - - fseeko64(file, 0, SEEK_END); - length_type length = ftello64(file); - fseeko64(file, 0, SEEK_SET); -#else - // if this is a 32-bit OS, long is enough; if this is a unix system, long is - // 64-bit, which is enough; otherwise we can't do anything anyway. - typedef long length_type; - - fseek(file, 0, SEEK_END); - length_type length = ftell(file); - fseek(file, 0, SEEK_SET); -#endif - - // check for I/O errors - if (length < 0) - return status_io_error; - - // check for overflow - size_t result = static_cast(length); - - if (static_cast(result) != length) - return status_out_of_memory; - - // finalize - out_result = result; - - return status_ok; -} - -// This function assumes that buffer has extra sizeof(char_t) writable bytes -// after size -PUGI__FN size_t zero_terminate_buffer(void *buffer, size_t size, - xml_encoding encoding) { - // We only need to zero-terminate if encoding conversion does not do it for us -#ifdef PUGIXML_WCHAR_MODE - xml_encoding wchar_encoding = get_wchar_encoding(); - - if (encoding == wchar_encoding || - need_endian_swap_utf(encoding, wchar_encoding)) { - size_t length = size / sizeof(char_t); - - static_cast(buffer)[length] = 0; - return (length + 1) * sizeof(char_t); - } -#else - if (encoding == encoding_utf8) { - static_cast(buffer)[size] = 0; - return size + 1; - } -#endif - - return size; -} - -PUGI__FN xml_parse_result load_file_impl(xml_document_struct *doc, FILE *file, - unsigned int options, - xml_encoding encoding, - char_t **out_buffer) { - if (!file) - return make_parse_result(status_file_not_found); - - // get file size (can result in I/O errors) - size_t size = 0; - xml_parse_status size_status = get_file_size(file, size); - if (size_status != status_ok) - return make_parse_result(size_status); - - size_t max_suffix_size = sizeof(char_t); - - // allocate buffer for the whole file - char *contents = - static_cast(xml_memory::allocate(size + max_suffix_size)); - if (!contents) - return make_parse_result(status_out_of_memory); - - // read file in memory - size_t read_size = fread(contents, 1, size, file); - - if (read_size != size) { - xml_memory::deallocate(contents); - return make_parse_result(status_io_error); - } - - xml_encoding real_encoding = get_buffer_encoding(encoding, contents, size); - - return load_buffer_impl(doc, doc, contents, - zero_terminate_buffer(contents, size, real_encoding), - options, real_encoding, true, true, out_buffer); -} - -#ifndef PUGIXML_NO_STL -template struct xml_stream_chunk { - static xml_stream_chunk *create() { - void *memory = xml_memory::allocate(sizeof(xml_stream_chunk)); - if (!memory) - return 0; - - return new (memory) xml_stream_chunk(); - } - - static void destroy(xml_stream_chunk *chunk) { - // free chunk chain - while (chunk) { - xml_stream_chunk *next_ = chunk->next; - - xml_memory::deallocate(chunk); - - chunk = next_; - } - } - - xml_stream_chunk() : next(0), size(0) {} - - xml_stream_chunk *next; - size_t size; - - T data[xml_memory_page_size / sizeof(T)]; -}; - -template -PUGI__FN xml_parse_status load_stream_data_noseek(std::basic_istream &stream, - void **out_buffer, - size_t *out_size) { - auto_deleter> chunks(0, xml_stream_chunk::destroy); - - // read file to a chunk list - size_t total = 0; - xml_stream_chunk *last = 0; - - while (!stream.eof()) { - // allocate new chunk - xml_stream_chunk *chunk = xml_stream_chunk::create(); - if (!chunk) - return status_out_of_memory; - - // append chunk to list - if (last) - last = last->next = chunk; - else - chunks.data = last = chunk; - - // read data to chunk - stream.read(chunk->data, - static_cast(sizeof(chunk->data) / sizeof(T))); - chunk->size = static_cast(stream.gcount()) * sizeof(T); - - // read may set failbit | eofbit in case gcount() is less than read length, - // so check for other I/O errors - if (stream.bad() || (!stream.eof() && stream.fail())) - return status_io_error; - - // guard against huge files (chunk size is small enough to make this - // overflow check work) - if (total + chunk->size < total) - return status_out_of_memory; - total += chunk->size; - } - - size_t max_suffix_size = sizeof(char_t); - - // copy chunk list to a contiguous buffer - char *buffer = - static_cast(xml_memory::allocate(total + max_suffix_size)); - if (!buffer) - return status_out_of_memory; - - char *write = buffer; - - for (xml_stream_chunk *chunk = chunks.data; chunk; chunk = chunk->next) { - assert(write + chunk->size <= buffer + total); - memcpy(write, chunk->data, chunk->size); - write += chunk->size; - } - - assert(write == buffer + total); - - // return buffer - *out_buffer = buffer; - *out_size = total; - - return status_ok; -} - -template -PUGI__FN xml_parse_status load_stream_data_seek(std::basic_istream &stream, - void **out_buffer, - size_t *out_size) { - // get length of remaining data in stream - typename std::basic_istream::pos_type pos = stream.tellg(); - stream.seekg(0, std::ios::end); - std::streamoff length = stream.tellg() - pos; - stream.seekg(pos); - - if (stream.fail() || pos < 0) - return status_io_error; - - // guard against huge files - size_t read_length = static_cast(length); - - if (static_cast(read_length) != length || length < 0) - return status_out_of_memory; - - size_t max_suffix_size = sizeof(char_t); - - // read stream data into memory (guard against stream exceptions with buffer - // holder) - auto_deleter buffer( - xml_memory::allocate(read_length * sizeof(T) + max_suffix_size), - xml_memory::deallocate); - if (!buffer.data) - return status_out_of_memory; - - stream.read(static_cast(buffer.data), - static_cast(read_length)); - - // read may set failbit | eofbit in case gcount() is less than read_length - // (i.e. line ending conversion), so check for other I/O errors - if (stream.bad() || (!stream.eof() && stream.fail())) - return status_io_error; - - // return buffer - size_t actual_length = static_cast(stream.gcount()); - assert(actual_length <= read_length); - - *out_buffer = buffer.release(); - *out_size = actual_length * sizeof(T); - - return status_ok; -} - -template -PUGI__FN xml_parse_result load_stream_impl(xml_document_struct *doc, - std::basic_istream &stream, - unsigned int options, - xml_encoding encoding, - char_t **out_buffer) { - void *buffer = 0; - size_t size = 0; - xml_parse_status status = status_ok; - - // if stream has an error bit set, bail out (otherwise tellg() can fail and - // we'll clear error bits) - if (stream.fail()) - return make_parse_result(status_io_error); - - // load stream to memory (using seek-based implementation if possible, since - // it's faster and takes less memory) - if (stream.tellg() < 0) { - stream.clear(); // clear error flags that could be set by a failing tellg - status = load_stream_data_noseek(stream, &buffer, &size); - } else - status = load_stream_data_seek(stream, &buffer, &size); - - if (status != status_ok) - return make_parse_result(status); - - xml_encoding real_encoding = get_buffer_encoding(encoding, buffer, size); - - return load_buffer_impl(doc, doc, buffer, - zero_terminate_buffer(buffer, size, real_encoding), - options, real_encoding, true, true, out_buffer); -} -#endif - -#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) || \ - (defined(__MINGW32__) && \ - (!defined(__STRICT_ANSI__) || defined(__MINGW64_VERSION_MAJOR))) -PUGI__FN FILE *open_file_wide(const wchar_t *path, const wchar_t *mode) { - return _wfopen(path, mode); -} -#else -PUGI__FN char *convert_path_heap(const wchar_t *str) { - assert(str); - - // first pass: get length in utf8 characters - size_t length = strlength_wide(str); - size_t size = as_utf8_begin(str, length); - - // allocate resulting string - char *result = static_cast(xml_memory::allocate(size + 1)); - if (!result) - return 0; - - // second pass: convert to utf8 - as_utf8_end(result, size, str, length); - - // zero-terminate - result[size] = 0; - - return result; -} - -PUGI__FN FILE *open_file_wide(const wchar_t *path, const wchar_t *mode) { - // there is no standard function to open wide paths, so our best bet is to try - // utf8 path - char *path_utf8 = convert_path_heap(path); - if (!path_utf8) - return 0; - - // convert mode to ASCII (we mirror _wfopen interface) - char mode_ascii[4] = {0}; - for (size_t i = 0; mode[i]; ++i) - mode_ascii[i] = static_cast(mode[i]); - - // try to open the utf8 path - FILE *result = fopen(path_utf8, mode_ascii); - - // free dummy buffer - xml_memory::deallocate(path_utf8); - - return result; -} -#endif - -PUGI__FN bool save_file_impl(const xml_document &doc, FILE *file, - const char_t *indent, unsigned int flags, - xml_encoding encoding) { - if (!file) - return false; - - xml_writer_file writer(file); - doc.save(writer, indent, flags, encoding); - - return ferror(file) == 0; -} - -struct name_null_sentry { - xml_node_struct *node; - char_t *name; - - name_null_sentry(xml_node_struct *node_) : node(node_), name(node_->name) { - node->name = 0; - } - - ~name_null_sentry() { node->name = name; } -}; -PUGI__NS_END - -namespace pugi { -PUGI__FN xml_writer_file::xml_writer_file(void *file_) : file(file_) {} - -PUGI__FN void xml_writer_file::write(const void *data, size_t size) { - size_t result = fwrite(data, 1, size, static_cast(file)); - (void)!result; // unfortunately we can't do proper error handling here -} - -#ifndef PUGIXML_NO_STL -PUGI__FN xml_writer_stream::xml_writer_stream( - std::basic_ostream> &stream) - : narrow_stream(&stream), wide_stream(0) {} - -PUGI__FN xml_writer_stream::xml_writer_stream( - std::basic_ostream> &stream) - : narrow_stream(0), wide_stream(&stream) {} - -PUGI__FN void xml_writer_stream::write(const void *data, size_t size) { - if (narrow_stream) { - assert(!wide_stream); - narrow_stream->write(reinterpret_cast(data), - static_cast(size)); - } else { - assert(wide_stream); - assert(size % sizeof(wchar_t) == 0); - - wide_stream->write(reinterpret_cast(data), - static_cast(size / sizeof(wchar_t))); - } -} -#endif - -PUGI__FN xml_tree_walker::xml_tree_walker() : _depth(0) {} - -PUGI__FN xml_tree_walker::~xml_tree_walker() {} - -PUGI__FN int xml_tree_walker::depth() const { return _depth; } - -PUGI__FN bool xml_tree_walker::begin(xml_node &) { return true; } - -PUGI__FN bool xml_tree_walker::end(xml_node &) { return true; } - -PUGI__FN xml_attribute::xml_attribute() : _attr(0) {} - -PUGI__FN xml_attribute::xml_attribute(xml_attribute_struct *attr) - : _attr(attr) {} - -PUGI__FN static void unspecified_bool_xml_attribute(xml_attribute ***) {} - -PUGI__FN xml_attribute::operator xml_attribute::unspecified_bool_type() const { - return _attr ? unspecified_bool_xml_attribute : 0; -} - -PUGI__FN bool xml_attribute::operator!() const { return !_attr; } - -PUGI__FN bool xml_attribute::operator==(const xml_attribute &r) const { - return (_attr == r._attr); -} - -PUGI__FN bool xml_attribute::operator!=(const xml_attribute &r) const { - return (_attr != r._attr); -} - -PUGI__FN bool xml_attribute::operator<(const xml_attribute &r) const { - return (_attr < r._attr); -} - -PUGI__FN bool xml_attribute::operator>(const xml_attribute &r) const { - return (_attr > r._attr); -} - -PUGI__FN bool xml_attribute::operator<=(const xml_attribute &r) const { - return (_attr <= r._attr); -} - -PUGI__FN bool xml_attribute::operator>=(const xml_attribute &r) const { - return (_attr >= r._attr); -} - -PUGI__FN xml_attribute xml_attribute::next_attribute() const { - return _attr ? xml_attribute(_attr->next_attribute) : xml_attribute(); -} - -PUGI__FN xml_attribute xml_attribute::previous_attribute() const { - return _attr && _attr->prev_attribute_c->next_attribute - ? xml_attribute(_attr->prev_attribute_c) - : xml_attribute(); -} - -PUGI__FN const char_t *xml_attribute::as_string(const char_t *def) const { - return (_attr && _attr->value) ? _attr->value + 0 : def; -} - -PUGI__FN int xml_attribute::as_int(int def) const { - return (_attr && _attr->value) ? impl::get_value_int(_attr->value) : def; -} - -PUGI__FN unsigned int xml_attribute::as_uint(unsigned int def) const { - return (_attr && _attr->value) ? impl::get_value_uint(_attr->value) : def; -} - -PUGI__FN double xml_attribute::as_double(double def) const { - return (_attr && _attr->value) ? impl::get_value_double(_attr->value) : def; -} - -PUGI__FN float xml_attribute::as_float(float def) const { - return (_attr && _attr->value) ? impl::get_value_float(_attr->value) : def; -} - -PUGI__FN bool xml_attribute::as_bool(bool def) const { - return (_attr && _attr->value) ? impl::get_value_bool(_attr->value) : def; -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN long long xml_attribute::as_llong(long long def) const { - return (_attr && _attr->value) ? impl::get_value_llong(_attr->value) : def; -} - -PUGI__FN unsigned long long -xml_attribute::as_ullong(unsigned long long def) const { - return (_attr && _attr->value) ? impl::get_value_ullong(_attr->value) : def; -} -#endif - -PUGI__FN bool xml_attribute::empty() const { return !_attr; } - -PUGI__FN const char_t *xml_attribute::name() const { - return (_attr && _attr->name) ? _attr->name + 0 : PUGIXML_TEXT(""); -} - -PUGI__FN const char_t *xml_attribute::value() const { - return (_attr && _attr->value) ? _attr->value + 0 : PUGIXML_TEXT(""); -} - -PUGI__FN size_t xml_attribute::hash_value() const { - return static_cast(reinterpret_cast(_attr) / - sizeof(xml_attribute_struct)); -} - -PUGI__FN xml_attribute_struct *xml_attribute::internal_object() const { - return _attr; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(const char_t *rhs) { - set_value(rhs); - return *this; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(int rhs) { - set_value(rhs); - return *this; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(unsigned int rhs) { - set_value(rhs); - return *this; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(double rhs) { - set_value(rhs); - return *this; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(float rhs) { - set_value(rhs); - return *this; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(bool rhs) { - set_value(rhs); - return *this; -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN xml_attribute &xml_attribute::operator=(long long rhs) { - set_value(rhs); - return *this; -} - -PUGI__FN xml_attribute &xml_attribute::operator=(unsigned long long rhs) { - set_value(rhs); - return *this; -} -#endif - -PUGI__FN bool xml_attribute::set_name(const char_t *rhs) { - if (!_attr) - return false; - - return impl::strcpy_insitu(_attr->name, _attr->header, - impl::xml_memory_page_name_allocated_mask, rhs, - impl::strlength(rhs)); -} - -PUGI__FN bool xml_attribute::set_value(const char_t *rhs) { - if (!_attr) - return false; - - return impl::strcpy_insitu(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, rhs, - impl::strlength(rhs)); -} - -PUGI__FN bool xml_attribute::set_value(int rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} - -PUGI__FN bool xml_attribute::set_value(unsigned int rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} - -PUGI__FN bool xml_attribute::set_value(double rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} - -PUGI__FN bool xml_attribute::set_value(float rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} - -PUGI__FN bool xml_attribute::set_value(bool rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN bool xml_attribute::set_value(long long rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} - -PUGI__FN bool xml_attribute::set_value(unsigned long long rhs) { - if (!_attr) - return false; - - return impl::set_value_convert(_attr->value, _attr->header, - impl::xml_memory_page_value_allocated_mask, - rhs); -} -#endif - -#ifdef __BORLANDC__ -PUGI__FN bool operator&&(const xml_attribute &lhs, bool rhs) { - return (bool)lhs && rhs; -} - -PUGI__FN bool operator||(const xml_attribute &lhs, bool rhs) { - return (bool)lhs || rhs; -} -#endif - -PUGI__FN xml_node::xml_node() : _root(0) {} - -PUGI__FN xml_node::xml_node(xml_node_struct *p) : _root(p) {} - -PUGI__FN static void unspecified_bool_xml_node(xml_node ***) {} - -PUGI__FN xml_node::operator xml_node::unspecified_bool_type() const { - return _root ? unspecified_bool_xml_node : 0; -} - -PUGI__FN bool xml_node::operator!() const { return !_root; } - -PUGI__FN xml_node::iterator xml_node::begin() const { - return iterator(_root ? _root->first_child + 0 : 0, _root); -} - -PUGI__FN xml_node::iterator xml_node::end() const { return iterator(0, _root); } - -PUGI__FN xml_node::attribute_iterator xml_node::attributes_begin() const { - return attribute_iterator(_root ? _root->first_attribute + 0 : 0, _root); -} - -PUGI__FN xml_node::attribute_iterator xml_node::attributes_end() const { - return attribute_iterator(0, _root); -} - -PUGI__FN xml_object_range xml_node::children() const { - return xml_object_range(begin(), end()); -} - -PUGI__FN xml_object_range -xml_node::children(const char_t *name_) const { - return xml_object_range( - xml_named_node_iterator(child(name_)._root, _root, name_), - xml_named_node_iterator(0, _root, name_)); -} - -PUGI__FN xml_object_range xml_node::attributes() const { - return xml_object_range(attributes_begin(), - attributes_end()); -} - -PUGI__FN bool xml_node::operator==(const xml_node &r) const { - return (_root == r._root); -} - -PUGI__FN bool xml_node::operator!=(const xml_node &r) const { - return (_root != r._root); -} - -PUGI__FN bool xml_node::operator<(const xml_node &r) const { - return (_root < r._root); -} - -PUGI__FN bool xml_node::operator>(const xml_node &r) const { - return (_root > r._root); -} - -PUGI__FN bool xml_node::operator<=(const xml_node &r) const { - return (_root <= r._root); -} - -PUGI__FN bool xml_node::operator>=(const xml_node &r) const { - return (_root >= r._root); -} - -PUGI__FN bool xml_node::empty() const { return !_root; } - -PUGI__FN const char_t *xml_node::name() const { - return (_root && _root->name) ? _root->name + 0 : PUGIXML_TEXT(""); -} - -PUGI__FN xml_node_type xml_node::type() const { - return _root ? PUGI__NODETYPE(_root) : node_null; -} - -PUGI__FN const char_t *xml_node::value() const { - return (_root && _root->value) ? _root->value + 0 : PUGIXML_TEXT(""); -} - -PUGI__FN xml_node xml_node::child(const char_t *name_) const { - if (!_root) - return xml_node(); - - for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) - if (i->name && impl::strequal(name_, i->name)) - return xml_node(i); - - return xml_node(); -} - -PUGI__FN xml_attribute xml_node::attribute(const char_t *name_) const { - if (!_root) - return xml_attribute(); - - for (xml_attribute_struct *i = _root->first_attribute; i; - i = i->next_attribute) - if (i->name && impl::strequal(name_, i->name)) - return xml_attribute(i); - - return xml_attribute(); -} - -PUGI__FN xml_node xml_node::next_sibling(const char_t *name_) const { - if (!_root) - return xml_node(); - - for (xml_node_struct *i = _root->next_sibling; i; i = i->next_sibling) - if (i->name && impl::strequal(name_, i->name)) - return xml_node(i); - - return xml_node(); -} - -PUGI__FN xml_node xml_node::next_sibling() const { - return _root ? xml_node(_root->next_sibling) : xml_node(); -} - -PUGI__FN xml_node xml_node::previous_sibling(const char_t *name_) const { - if (!_root) - return xml_node(); - - for (xml_node_struct *i = _root->prev_sibling_c; i->next_sibling; - i = i->prev_sibling_c) - if (i->name && impl::strequal(name_, i->name)) - return xml_node(i); - - return xml_node(); -} - -PUGI__FN xml_attribute xml_node::attribute(const char_t *name_, - xml_attribute &hint_) const { - xml_attribute_struct *hint = hint_._attr; - - // if hint is not an attribute of node, behavior is not defined - assert(!hint || (_root && impl::is_attribute_of(hint, _root))); - - if (!_root) - return xml_attribute(); - - // optimistically search from hint up until the end - for (xml_attribute_struct *i = hint; i; i = i->next_attribute) - if (i->name && impl::strequal(name_, i->name)) { - // update hint to maximize efficiency of searching for consecutive - // attributes - hint_._attr = i->next_attribute; - - return xml_attribute(i); - } - - // wrap around and search from the first attribute until the hint - // 'j' null pointer check is technically redundant, but it prevents a crash in - // case the assertion above fails - for (xml_attribute_struct *j = _root->first_attribute; j && j != hint; - j = j->next_attribute) - if (j->name && impl::strequal(name_, j->name)) { - // update hint to maximize efficiency of searching for consecutive - // attributes - hint_._attr = j->next_attribute; - - return xml_attribute(j); - } - - return xml_attribute(); -} - -PUGI__FN xml_node xml_node::previous_sibling() const { - if (!_root) - return xml_node(); - - if (_root->prev_sibling_c->next_sibling) - return xml_node(_root->prev_sibling_c); - else - return xml_node(); -} - -PUGI__FN xml_node xml_node::parent() const { - return _root ? xml_node(_root->parent) : xml_node(); -} - -PUGI__FN xml_node xml_node::root() const { - return _root ? xml_node(&impl::get_document(_root)) : xml_node(); -} - -PUGI__FN xml_text xml_node::text() const { return xml_text(_root); } - -PUGI__FN const char_t *xml_node::child_value() const { - if (!_root) - return PUGIXML_TEXT(""); - - for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) - if (impl::is_text_node(i) && i->value) - return i->value; - - return PUGIXML_TEXT(""); -} - -PUGI__FN const char_t *xml_node::child_value(const char_t *name_) const { - return child(name_).child_value(); -} - -PUGI__FN xml_attribute xml_node::first_attribute() const { - return _root ? xml_attribute(_root->first_attribute) : xml_attribute(); -} - -PUGI__FN xml_attribute xml_node::last_attribute() const { - return _root && _root->first_attribute - ? xml_attribute(_root->first_attribute->prev_attribute_c) - : xml_attribute(); -} - -PUGI__FN xml_node xml_node::first_child() const { - return _root ? xml_node(_root->first_child) : xml_node(); -} - -PUGI__FN xml_node xml_node::last_child() const { - return _root && _root->first_child - ? xml_node(_root->first_child->prev_sibling_c) - : xml_node(); -} - -PUGI__FN bool xml_node::set_name(const char_t *rhs) { - xml_node_type type_ = _root ? PUGI__NODETYPE(_root) : node_null; - - if (type_ != node_element && type_ != node_pi && type_ != node_declaration) - return false; - - return impl::strcpy_insitu(_root->name, _root->header, - impl::xml_memory_page_name_allocated_mask, rhs, - impl::strlength(rhs)); -} - -PUGI__FN bool xml_node::set_value(const char_t *rhs) { - xml_node_type type_ = _root ? PUGI__NODETYPE(_root) : node_null; - - if (type_ != node_pcdata && type_ != node_cdata && type_ != node_comment && - type_ != node_pi && type_ != node_doctype) - return false; - - return impl::strcpy_insitu(_root->value, _root->header, - impl::xml_memory_page_value_allocated_mask, rhs, - impl::strlength(rhs)); -} - -PUGI__FN xml_attribute xml_node::append_attribute(const char_t *name_) { - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::append_attribute(a._attr, _root); - - a.set_name(name_); - - return a; -} - -PUGI__FN xml_attribute xml_node::prepend_attribute(const char_t *name_) { - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::prepend_attribute(a._attr, _root); - - a.set_name(name_); - - return a; -} - -PUGI__FN xml_attribute xml_node::insert_attribute_after( - const char_t *name_, const xml_attribute &attr) { - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - if (!attr || !impl::is_attribute_of(attr._attr, _root)) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::insert_attribute_after(a._attr, attr._attr, _root); - - a.set_name(name_); - - return a; -} - -PUGI__FN xml_attribute xml_node::insert_attribute_before( - const char_t *name_, const xml_attribute &attr) { - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - if (!attr || !impl::is_attribute_of(attr._attr, _root)) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::insert_attribute_before(a._attr, attr._attr, _root); - - a.set_name(name_); - - return a; -} - -PUGI__FN xml_attribute xml_node::append_copy(const xml_attribute &proto) { - if (!proto) - return xml_attribute(); - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::append_attribute(a._attr, _root); - impl::node_copy_attribute(a._attr, proto._attr); - - return a; -} - -PUGI__FN xml_attribute xml_node::prepend_copy(const xml_attribute &proto) { - if (!proto) - return xml_attribute(); - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::prepend_attribute(a._attr, _root); - impl::node_copy_attribute(a._attr, proto._attr); - - return a; -} - -PUGI__FN xml_attribute xml_node::insert_copy_after(const xml_attribute &proto, - const xml_attribute &attr) { - if (!proto) - return xml_attribute(); - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - if (!attr || !impl::is_attribute_of(attr._attr, _root)) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::insert_attribute_after(a._attr, attr._attr, _root); - impl::node_copy_attribute(a._attr, proto._attr); - - return a; -} - -PUGI__FN xml_attribute xml_node::insert_copy_before(const xml_attribute &proto, - const xml_attribute &attr) { - if (!proto) - return xml_attribute(); - if (!impl::allow_insert_attribute(type())) - return xml_attribute(); - if (!attr || !impl::is_attribute_of(attr._attr, _root)) - return xml_attribute(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_attribute(); - - xml_attribute a(impl::allocate_attribute(alloc)); - if (!a) - return xml_attribute(); - - impl::insert_attribute_before(a._attr, attr._attr, _root); - impl::node_copy_attribute(a._attr, proto._attr); - - return a; -} - -PUGI__FN xml_node xml_node::append_child(xml_node_type type_) { - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::append_node(n._root, _root); - - if (type_ == node_declaration) - n.set_name(PUGIXML_TEXT("xml")); - - return n; -} - -PUGI__FN xml_node xml_node::prepend_child(xml_node_type type_) { - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::prepend_node(n._root, _root); - - if (type_ == node_declaration) - n.set_name(PUGIXML_TEXT("xml")); - - return n; -} - -PUGI__FN xml_node xml_node::insert_child_before(xml_node_type type_, - const xml_node &node) { - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - if (!node._root || node._root->parent != _root) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::insert_node_before(n._root, node._root); - - if (type_ == node_declaration) - n.set_name(PUGIXML_TEXT("xml")); - - return n; -} - -PUGI__FN xml_node xml_node::insert_child_after(xml_node_type type_, - const xml_node &node) { - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - if (!node._root || node._root->parent != _root) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::insert_node_after(n._root, node._root); - - if (type_ == node_declaration) - n.set_name(PUGIXML_TEXT("xml")); - - return n; -} - -PUGI__FN xml_node xml_node::append_child(const char_t *name_) { - xml_node result = append_child(node_element); - - result.set_name(name_); - - return result; -} - -PUGI__FN xml_node xml_node::prepend_child(const char_t *name_) { - xml_node result = prepend_child(node_element); - - result.set_name(name_); - - return result; -} - -PUGI__FN xml_node xml_node::insert_child_after(const char_t *name_, - const xml_node &node) { - xml_node result = insert_child_after(node_element, node); - - result.set_name(name_); - - return result; -} - -PUGI__FN xml_node xml_node::insert_child_before(const char_t *name_, - const xml_node &node) { - xml_node result = insert_child_before(node_element, node); - - result.set_name(name_); - - return result; -} - -PUGI__FN xml_node xml_node::append_copy(const xml_node &proto) { - xml_node_type type_ = proto.type(); - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::append_node(n._root, _root); - impl::node_copy_tree(n._root, proto._root); - - return n; -} - -PUGI__FN xml_node xml_node::prepend_copy(const xml_node &proto) { - xml_node_type type_ = proto.type(); - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::prepend_node(n._root, _root); - impl::node_copy_tree(n._root, proto._root); - - return n; -} - -PUGI__FN xml_node xml_node::insert_copy_after(const xml_node &proto, - const xml_node &node) { - xml_node_type type_ = proto.type(); - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - if (!node._root || node._root->parent != _root) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::insert_node_after(n._root, node._root); - impl::node_copy_tree(n._root, proto._root); - - return n; -} - -PUGI__FN xml_node xml_node::insert_copy_before(const xml_node &proto, - const xml_node &node) { - xml_node_type type_ = proto.type(); - if (!impl::allow_insert_child(type(), type_)) - return xml_node(); - if (!node._root || node._root->parent != _root) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - xml_node n(impl::allocate_node(alloc, type_)); - if (!n) - return xml_node(); - - impl::insert_node_before(n._root, node._root); - impl::node_copy_tree(n._root, proto._root); - - return n; -} - -PUGI__FN xml_node xml_node::append_move(const xml_node &moved) { - if (!impl::allow_move(*this, moved)) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - // disable document_buffer_order optimization since moving nodes around - // changes document order without changing buffer pointers - impl::get_document(_root).header |= - impl::xml_memory_page_contents_shared_mask; - - impl::remove_node(moved._root); - impl::append_node(moved._root, _root); - - return moved; -} - -PUGI__FN xml_node xml_node::prepend_move(const xml_node &moved) { - if (!impl::allow_move(*this, moved)) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - // disable document_buffer_order optimization since moving nodes around - // changes document order without changing buffer pointers - impl::get_document(_root).header |= - impl::xml_memory_page_contents_shared_mask; - - impl::remove_node(moved._root); - impl::prepend_node(moved._root, _root); - - return moved; -} - -PUGI__FN xml_node xml_node::insert_move_after(const xml_node &moved, - const xml_node &node) { - if (!impl::allow_move(*this, moved)) - return xml_node(); - if (!node._root || node._root->parent != _root) - return xml_node(); - if (moved._root == node._root) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - // disable document_buffer_order optimization since moving nodes around - // changes document order without changing buffer pointers - impl::get_document(_root).header |= - impl::xml_memory_page_contents_shared_mask; - - impl::remove_node(moved._root); - impl::insert_node_after(moved._root, node._root); - - return moved; -} - -PUGI__FN xml_node xml_node::insert_move_before(const xml_node &moved, - const xml_node &node) { - if (!impl::allow_move(*this, moved)) - return xml_node(); - if (!node._root || node._root->parent != _root) - return xml_node(); - if (moved._root == node._root) - return xml_node(); - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return xml_node(); - - // disable document_buffer_order optimization since moving nodes around - // changes document order without changing buffer pointers - impl::get_document(_root).header |= - impl::xml_memory_page_contents_shared_mask; - - impl::remove_node(moved._root); - impl::insert_node_before(moved._root, node._root); - - return moved; -} - -PUGI__FN bool xml_node::remove_attribute(const char_t *name_) { - return remove_attribute(attribute(name_)); -} - -PUGI__FN bool xml_node::remove_attribute(const xml_attribute &a) { - if (!_root || !a._attr) - return false; - if (!impl::is_attribute_of(a._attr, _root)) - return false; - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return false; - - impl::remove_attribute(a._attr, _root); - impl::destroy_attribute(a._attr, alloc); - - return true; -} - -PUGI__FN bool xml_node::remove_child(const char_t *name_) { - return remove_child(child(name_)); -} - -PUGI__FN bool xml_node::remove_child(const xml_node &n) { - if (!_root || !n._root || n._root->parent != _root) - return false; - - impl::xml_allocator &alloc = impl::get_allocator(_root); - if (!alloc.reserve()) - return false; - - impl::remove_node(n._root); - impl::destroy_node(n._root, alloc); - - return true; -} - -PUGI__FN xml_parse_result xml_node::append_buffer(const void *contents, - size_t size, - unsigned int options, - xml_encoding encoding) { - // append_buffer is only valid for elements/documents - if (!impl::allow_insert_child(type(), node_element)) - return impl::make_parse_result(status_append_invalid_root); - - // get document node - impl::xml_document_struct *doc = &impl::get_document(_root); - - // disable document_buffer_order optimization since in a document with - // multiple buffers comparing buffer pointers does not make sense - doc->header |= impl::xml_memory_page_contents_shared_mask; - - // get extra buffer element (we'll store the document fragment buffer there so - // that we can deallocate it later) - impl::xml_memory_page *page = 0; - impl::xml_extra_buffer *extra = static_cast( - doc->allocate_memory(sizeof(impl::xml_extra_buffer), page)); - (void)page; - - if (!extra) - return impl::make_parse_result(status_out_of_memory); - - // add extra buffer to the list - extra->buffer = 0; - extra->next = doc->extra_buffers; - doc->extra_buffers = extra; - - // name of the root has to be NULL before parsing - otherwise closing node - // mismatches will not be detected at the top level - impl::name_null_sentry sentry(_root); - - return impl::load_buffer_impl(doc, _root, const_cast(contents), size, - options, encoding, false, false, - &extra->buffer); -} - -PUGI__FN xml_node -xml_node::find_child_by_attribute(const char_t *name_, const char_t *attr_name, - const char_t *attr_value) const { - if (!_root) - return xml_node(); - - for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) - if (i->name && impl::strequal(name_, i->name)) { - for (xml_attribute_struct *a = i->first_attribute; a; - a = a->next_attribute) - if (a->name && impl::strequal(attr_name, a->name) && - impl::strequal(attr_value, - a->value ? a->value + 0 : PUGIXML_TEXT(""))) - return xml_node(i); - } - - return xml_node(); -} - -PUGI__FN xml_node xml_node::find_child_by_attribute( - const char_t *attr_name, const char_t *attr_value) const { - if (!_root) - return xml_node(); - - for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) - for (xml_attribute_struct *a = i->first_attribute; a; a = a->next_attribute) - if (a->name && impl::strequal(attr_name, a->name) && - impl::strequal(attr_value, - a->value ? a->value + 0 : PUGIXML_TEXT(""))) - return xml_node(i); - - return xml_node(); -} - -#ifndef PUGIXML_NO_STL -PUGI__FN string_t xml_node::path(char_t delimiter) const { - if (!_root) - return string_t(); - - size_t offset = 0; - - for (xml_node_struct *i = _root; i; i = i->parent) { - offset += (i != _root); - offset += i->name ? impl::strlength(i->name) : 0; - } - - string_t result; - result.resize(offset); - - for (xml_node_struct *j = _root; j; j = j->parent) { - if (j != _root) - result[--offset] = delimiter; - - if (j->name && *j->name) { - size_t length = impl::strlength(j->name); - - offset -= length; - memcpy(&result[offset], j->name, length * sizeof(char_t)); - } - } - - assert(offset == 0); - - return result; -} -#endif - -PUGI__FN xml_node xml_node::first_element_by_path(const char_t *path_, - char_t delimiter) const { - xml_node found = *this; // Current search context. - - if (!_root || !path_ || !path_[0]) - return found; - - if (path_[0] == delimiter) { - // Absolute path; e.g. '/foo/bar' - found = found.root(); - ++path_; - } - - const char_t *path_segment = path_; - - while (*path_segment == delimiter) - ++path_segment; - - const char_t *path_segment_end = path_segment; - - while (*path_segment_end && *path_segment_end != delimiter) - ++path_segment_end; - - if (path_segment == path_segment_end) - return found; - - const char_t *next_segment = path_segment_end; - - while (*next_segment == delimiter) - ++next_segment; - - if (*path_segment == '.' && path_segment + 1 == path_segment_end) - return found.first_element_by_path(next_segment, delimiter); - else if (*path_segment == '.' && *(path_segment + 1) == '.' && - path_segment + 2 == path_segment_end) - return found.parent().first_element_by_path(next_segment, delimiter); - else { - for (xml_node_struct *j = found._root->first_child; j; - j = j->next_sibling) { - if (j->name && impl::strequalrange(j->name, path_segment, - static_cast(path_segment_end - - path_segment))) { - xml_node subsearch = - xml_node(j).first_element_by_path(next_segment, delimiter); - - if (subsearch) - return subsearch; - } - } - - return xml_node(); - } -} - -PUGI__FN bool xml_node::traverse(xml_tree_walker &walker) { - walker._depth = -1; - - xml_node arg_begin = *this; - if (!walker.begin(arg_begin)) - return false; - - xml_node cur = first_child(); - - if (cur) { - ++walker._depth; - - do { - xml_node arg_for_each = cur; - if (!walker.for_each(arg_for_each)) - return false; - - if (cur.first_child()) { - ++walker._depth; - cur = cur.first_child(); - } else if (cur.next_sibling()) - cur = cur.next_sibling(); - else { - // Borland C++ workaround - while (!cur.next_sibling() && cur != *this && !cur.parent().empty()) { - --walker._depth; - cur = cur.parent(); - } - - if (cur != *this) - cur = cur.next_sibling(); - } - } while (cur && cur != *this); - } - - assert(walker._depth == -1); - - xml_node arg_end = *this; - return walker.end(arg_end); -} - -PUGI__FN size_t xml_node::hash_value() const { - return static_cast(reinterpret_cast(_root) / - sizeof(xml_node_struct)); -} - -PUGI__FN xml_node_struct *xml_node::internal_object() const { return _root; } - -PUGI__FN void xml_node::print(xml_writer &writer, const char_t *indent, - unsigned int flags, xml_encoding encoding, - unsigned int depth) const { - if (!_root) - return; - - impl::xml_buffered_writer buffered_writer(writer, encoding); - - impl::node_output(buffered_writer, _root, indent, flags, depth); - - buffered_writer.flush(); -} - -#ifndef PUGIXML_NO_STL -PUGI__FN void -xml_node::print(std::basic_ostream> &stream, - const char_t *indent, unsigned int flags, xml_encoding encoding, - unsigned int depth) const { - xml_writer_stream writer(stream); - - print(writer, indent, flags, encoding, depth); -} - -PUGI__FN void -xml_node::print(std::basic_ostream> &stream, - const char_t *indent, unsigned int flags, - unsigned int depth) const { - xml_writer_stream writer(stream); - - print(writer, indent, flags, encoding_wchar, depth); -} -#endif - -PUGI__FN ptrdiff_t xml_node::offset_debug() const { - if (!_root) - return -1; - - impl::xml_document_struct &doc = impl::get_document(_root); - - // we can determine the offset reliably only if there is exactly once parse - // buffer - if (!doc.buffer || doc.extra_buffers) - return -1; - - switch (type()) { - case node_document: - return 0; - - case node_element: - case node_declaration: - case node_pi: - return _root->name && - (_root->header & - impl::xml_memory_page_name_allocated_or_shared_mask) == 0 - ? _root->name - doc.buffer - : -1; - - case node_pcdata: - case node_cdata: - case node_comment: - case node_doctype: - return _root->value && - (_root->header & - impl::xml_memory_page_value_allocated_or_shared_mask) == 0 - ? _root->value - doc.buffer - : -1; - - default: - return -1; - } -} - -#ifdef __BORLANDC__ -PUGI__FN bool operator&&(const xml_node &lhs, bool rhs) { - return (bool)lhs && rhs; -} - -PUGI__FN bool operator||(const xml_node &lhs, bool rhs) { - return (bool)lhs || rhs; -} -#endif - -PUGI__FN xml_text::xml_text(xml_node_struct *root) : _root(root) {} - -PUGI__FN xml_node_struct *xml_text::_data() const { - if (!_root || impl::is_text_node(_root)) - return _root; - - for (xml_node_struct *node = _root->first_child; node; - node = node->next_sibling) - if (impl::is_text_node(node)) - return node; - - return 0; -} - -PUGI__FN xml_node_struct *xml_text::_data_new() { - xml_node_struct *d = _data(); - if (d) - return d; - - return xml_node(_root).append_child(node_pcdata).internal_object(); -} - -PUGI__FN xml_text::xml_text() : _root(0) {} - -PUGI__FN static void unspecified_bool_xml_text(xml_text ***) {} - -PUGI__FN xml_text::operator xml_text::unspecified_bool_type() const { - return _data() ? unspecified_bool_xml_text : 0; -} - -PUGI__FN bool xml_text::operator!() const { return !_data(); } - -PUGI__FN bool xml_text::empty() const { return _data() == 0; } - -PUGI__FN const char_t *xml_text::get() const { - xml_node_struct *d = _data(); - - return (d && d->value) ? d->value + 0 : PUGIXML_TEXT(""); -} - -PUGI__FN const char_t *xml_text::as_string(const char_t *def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? d->value + 0 : def; -} - -PUGI__FN int xml_text::as_int(int def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_int(d->value) : def; -} - -PUGI__FN unsigned int xml_text::as_uint(unsigned int def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_uint(d->value) : def; -} - -PUGI__FN double xml_text::as_double(double def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_double(d->value) : def; -} - -PUGI__FN float xml_text::as_float(float def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_float(d->value) : def; -} - -PUGI__FN bool xml_text::as_bool(bool def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_bool(d->value) : def; -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN long long xml_text::as_llong(long long def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_llong(d->value) : def; -} - -PUGI__FN unsigned long long xml_text::as_ullong(unsigned long long def) const { - xml_node_struct *d = _data(); - - return (d && d->value) ? impl::get_value_ullong(d->value) : def; -} -#endif - -PUGI__FN bool xml_text::set(const char_t *rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::strcpy_insitu(dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, - rhs, impl::strlength(rhs)) - : false; -} - -PUGI__FN bool xml_text::set(int rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} - -PUGI__FN bool xml_text::set(unsigned int rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} - -PUGI__FN bool xml_text::set(float rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} - -PUGI__FN bool xml_text::set(double rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} - -PUGI__FN bool xml_text::set(bool rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN bool xml_text::set(long long rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} - -PUGI__FN bool xml_text::set(unsigned long long rhs) { - xml_node_struct *dn = _data_new(); - - return dn ? impl::set_value_convert( - dn->value, dn->header, - impl::xml_memory_page_value_allocated_mask, rhs) - : false; -} -#endif - -PUGI__FN xml_text &xml_text::operator=(const char_t *rhs) { - set(rhs); - return *this; -} - -PUGI__FN xml_text &xml_text::operator=(int rhs) { - set(rhs); - return *this; -} - -PUGI__FN xml_text &xml_text::operator=(unsigned int rhs) { - set(rhs); - return *this; -} - -PUGI__FN xml_text &xml_text::operator=(double rhs) { - set(rhs); - return *this; -} - -PUGI__FN xml_text &xml_text::operator=(float rhs) { - set(rhs); - return *this; -} - -PUGI__FN xml_text &xml_text::operator=(bool rhs) { - set(rhs); - return *this; -} - -#ifdef PUGIXML_HAS_LONG_LONG -PUGI__FN xml_text &xml_text::operator=(long long rhs) { - set(rhs); - return *this; -} - -PUGI__FN xml_text &xml_text::operator=(unsigned long long rhs) { - set(rhs); - return *this; -} -#endif - -PUGI__FN xml_node xml_text::data() const { return xml_node(_data()); } - -#ifdef __BORLANDC__ -PUGI__FN bool operator&&(const xml_text &lhs, bool rhs) { - return (bool)lhs && rhs; -} - -PUGI__FN bool operator||(const xml_text &lhs, bool rhs) { - return (bool)lhs || rhs; -} -#endif - -PUGI__FN xml_node_iterator::xml_node_iterator() {} - -PUGI__FN xml_node_iterator::xml_node_iterator(const xml_node &node) - : _wrap(node), _parent(node.parent()) {} - -PUGI__FN xml_node_iterator::xml_node_iterator(xml_node_struct *ref, - xml_node_struct *parent) - : _wrap(ref), _parent(parent) {} - -PUGI__FN bool -xml_node_iterator::operator==(const xml_node_iterator &rhs) const { - return _wrap._root == rhs._wrap._root && _parent._root == rhs._parent._root; -} - -PUGI__FN bool -xml_node_iterator::operator!=(const xml_node_iterator &rhs) const { - return _wrap._root != rhs._wrap._root || _parent._root != rhs._parent._root; -} - -PUGI__FN xml_node &xml_node_iterator::operator*() const { - assert(_wrap._root); - return _wrap; -} - -PUGI__FN xml_node *xml_node_iterator::operator->() const { - assert(_wrap._root); - return const_cast(&_wrap); // BCC32 workaround -} - -PUGI__FN const xml_node_iterator &xml_node_iterator::operator++() { - assert(_wrap._root); - _wrap._root = _wrap._root->next_sibling; - return *this; -} - -PUGI__FN xml_node_iterator xml_node_iterator::operator++(int) { - xml_node_iterator temp = *this; - ++*this; - return temp; -} - -PUGI__FN const xml_node_iterator &xml_node_iterator::operator--() { - _wrap = _wrap._root ? _wrap.previous_sibling() : _parent.last_child(); - return *this; -} - -PUGI__FN xml_node_iterator xml_node_iterator::operator--(int) { - xml_node_iterator temp = *this; - --*this; - return temp; -} - -PUGI__FN xml_attribute_iterator::xml_attribute_iterator() {} - -PUGI__FN -xml_attribute_iterator::xml_attribute_iterator(const xml_attribute &attr, - const xml_node &parent) - : _wrap(attr), _parent(parent) {} - -PUGI__FN -xml_attribute_iterator::xml_attribute_iterator(xml_attribute_struct *ref, - xml_node_struct *parent) - : _wrap(ref), _parent(parent) {} - -PUGI__FN bool -xml_attribute_iterator::operator==(const xml_attribute_iterator &rhs) const { - return _wrap._attr == rhs._wrap._attr && _parent._root == rhs._parent._root; -} - -PUGI__FN bool -xml_attribute_iterator::operator!=(const xml_attribute_iterator &rhs) const { - return _wrap._attr != rhs._wrap._attr || _parent._root != rhs._parent._root; -} - -PUGI__FN xml_attribute &xml_attribute_iterator::operator*() const { - assert(_wrap._attr); - return _wrap; -} - -PUGI__FN xml_attribute *xml_attribute_iterator::operator->() const { - assert(_wrap._attr); - return const_cast(&_wrap); // BCC32 workaround -} - -PUGI__FN const xml_attribute_iterator &xml_attribute_iterator::operator++() { - assert(_wrap._attr); - _wrap._attr = _wrap._attr->next_attribute; - return *this; -} - -PUGI__FN xml_attribute_iterator xml_attribute_iterator::operator++(int) { - xml_attribute_iterator temp = *this; - ++*this; - return temp; -} - -PUGI__FN const xml_attribute_iterator &xml_attribute_iterator::operator--() { - _wrap = _wrap._attr ? _wrap.previous_attribute() : _parent.last_attribute(); - return *this; -} - -PUGI__FN xml_attribute_iterator xml_attribute_iterator::operator--(int) { - xml_attribute_iterator temp = *this; - --*this; - return temp; -} - -PUGI__FN xml_named_node_iterator::xml_named_node_iterator() : _name(0) {} - -PUGI__FN xml_named_node_iterator::xml_named_node_iterator(const xml_node &node, - const char_t *name) - : _wrap(node), _parent(node.parent()), _name(name) {} - -PUGI__FN xml_named_node_iterator::xml_named_node_iterator( - xml_node_struct *ref, xml_node_struct *parent, const char_t *name) - : _wrap(ref), _parent(parent), _name(name) {} - -PUGI__FN bool -xml_named_node_iterator::operator==(const xml_named_node_iterator &rhs) const { - return _wrap._root == rhs._wrap._root && _parent._root == rhs._parent._root; -} - -PUGI__FN bool -xml_named_node_iterator::operator!=(const xml_named_node_iterator &rhs) const { - return _wrap._root != rhs._wrap._root || _parent._root != rhs._parent._root; -} - -PUGI__FN xml_node &xml_named_node_iterator::operator*() const { - assert(_wrap._root); - return _wrap; -} - -PUGI__FN xml_node *xml_named_node_iterator::operator->() const { - assert(_wrap._root); - return const_cast(&_wrap); // BCC32 workaround -} - -PUGI__FN const xml_named_node_iterator &xml_named_node_iterator::operator++() { - assert(_wrap._root); - _wrap = _wrap.next_sibling(_name); - return *this; -} - -PUGI__FN xml_named_node_iterator xml_named_node_iterator::operator++(int) { - xml_named_node_iterator temp = *this; - ++*this; - return temp; -} - -PUGI__FN const xml_named_node_iterator &xml_named_node_iterator::operator--() { - if (_wrap._root) - _wrap = _wrap.previous_sibling(_name); - else { - _wrap = _parent.last_child(); - - if (!impl::strequal(_wrap.name(), _name)) - _wrap = _wrap.previous_sibling(_name); - } - - return *this; -} - -PUGI__FN xml_named_node_iterator xml_named_node_iterator::operator--(int) { - xml_named_node_iterator temp = *this; - --*this; - return temp; -} - -PUGI__FN xml_parse_result::xml_parse_result() - : status(status_internal_error), offset(0), encoding(encoding_auto) {} - -PUGI__FN xml_parse_result::operator bool() const { return status == status_ok; } - -PUGI__FN const char *xml_parse_result::description() const { - switch (status) { - case status_ok: - return "No error"; - - case status_file_not_found: - return "File was not found"; - case status_io_error: - return "Error reading from file/stream"; - case status_out_of_memory: - return "Could not allocate memory"; - case status_internal_error: - return "Internal error occurred"; - - case status_unrecognized_tag: - return "Could not determine tag type"; - - case status_bad_pi: - return "Error parsing document declaration/processing instruction"; - case status_bad_comment: - return "Error parsing comment"; - case status_bad_cdata: - return "Error parsing CDATA section"; - case status_bad_doctype: - return "Error parsing document type declaration"; - case status_bad_pcdata: - return "Error parsing PCDATA section"; - case status_bad_start_element: - return "Error parsing start element tag"; - case status_bad_attribute: - return "Error parsing element attribute"; - case status_bad_end_element: - return "Error parsing end element tag"; - case status_end_element_mismatch: - return "Start-end tags mismatch"; - - case status_append_invalid_root: - return "Unable to append nodes: root is not an element or document"; - - case status_no_document_element: - return "No document element found"; - - default: - return "Unknown error"; - } -} - -PUGI__FN xml_document::xml_document() : _buffer(0) { create(); } - -PUGI__FN xml_document::~xml_document() { destroy(); } - -PUGI__FN void xml_document::reset() { - destroy(); - create(); -} - -PUGI__FN void xml_document::reset(const xml_document &proto) { - reset(); - - for (xml_node cur = proto.first_child(); cur; cur = cur.next_sibling()) - append_copy(cur); -} - -PUGI__FN void xml_document::create() { - assert(!_root); - -#ifdef PUGIXML_COMPACT - const size_t page_offset = sizeof(uint32_t); -#else - const size_t page_offset = 0; -#endif - - // initialize sentinel page - PUGI__STATIC_ASSERT( - sizeof(impl::xml_memory_page) + sizeof(impl::xml_document_struct) + - impl::xml_memory_page_alignment - sizeof(void *) + page_offset <= - sizeof(_memory)); - - // align upwards to page boundary - void *page_memory = - reinterpret_cast((reinterpret_cast(_memory) + - (impl::xml_memory_page_alignment - 1)) & - ~(impl::xml_memory_page_alignment - 1)); - - // prepare page structure - impl::xml_memory_page *page = impl::xml_memory_page::construct(page_memory); - assert(page); - - page->busy_size = impl::xml_memory_page_size; - - // setup first page marker -#ifdef PUGIXML_COMPACT - // round-trip through void* to avoid 'cast increases required alignment of - // target type' warning - page->compact_page_marker = reinterpret_cast(static_cast( - reinterpret_cast(page) + sizeof(impl::xml_memory_page))); - *page->compact_page_marker = sizeof(impl::xml_memory_page); -#endif - - // allocate new root - _root = new (reinterpret_cast(page) + sizeof(impl::xml_memory_page) + - page_offset) impl::xml_document_struct(page); - _root->prev_sibling_c = _root; - - // setup sentinel page - page->allocator = static_cast(_root); - - // verify the document allocation - assert(reinterpret_cast(_root) + sizeof(impl::xml_document_struct) <= - _memory + sizeof(_memory)); -} - -PUGI__FN void xml_document::destroy() { - assert(_root); - - // destroy static storage - if (_buffer) { - impl::xml_memory::deallocate(_buffer); - _buffer = 0; - } - - // destroy extra buffers (note: no need to destroy linked list nodes, they're - // allocated using document allocator) - for (impl::xml_extra_buffer *extra = - static_cast(_root)->extra_buffers; - extra; extra = extra->next) { - if (extra->buffer) - impl::xml_memory::deallocate(extra->buffer); - } - - // destroy dynamic storage, leave sentinel page (it's in static memory) - impl::xml_memory_page *root_page = PUGI__GETPAGE(_root); - assert(root_page && !root_page->prev); - assert(reinterpret_cast(root_page) >= _memory && - reinterpret_cast(root_page) < _memory + sizeof(_memory)); - - for (impl::xml_memory_page *page = root_page->next; page;) { - impl::xml_memory_page *next = page->next; - - impl::xml_allocator::deallocate_page(page); - - page = next; - } - -#ifdef PUGIXML_COMPACT - // destroy hash table - static_cast(_root)->hash.clear(); -#endif - - _root = 0; -} - -#ifndef PUGIXML_NO_STL -PUGI__FN xml_parse_result -xml_document::load(std::basic_istream> &stream, - unsigned int options, xml_encoding encoding) { - reset(); - - return impl::load_stream_impl(static_cast(_root), - stream, options, encoding, &_buffer); -} - -PUGI__FN xml_parse_result xml_document::load( - std::basic_istream> &stream, - unsigned int options) { - reset(); - - return impl::load_stream_impl(static_cast(_root), - stream, options, encoding_wchar, &_buffer); -} -#endif - -PUGI__FN xml_parse_result xml_document::load_string(const char_t *contents, - unsigned int options) { - // Force native encoding (skip autodetection) -#ifdef PUGIXML_WCHAR_MODE - xml_encoding encoding = encoding_wchar; -#else - xml_encoding encoding = encoding_utf8; -#endif - - return load_buffer(contents, impl::strlength(contents) * sizeof(char_t), - options, encoding); -} - -PUGI__FN xml_parse_result xml_document::load(const char_t *contents, - unsigned int options) { - return load_string(contents, options); -} - -PUGI__FN xml_parse_result xml_document::load_file(const char *path_, - unsigned int options, - xml_encoding encoding) { - reset(); - - using impl::auto_deleter; // MSVC7 workaround - auto_deleter file(fopen(path_, "rb"), fclose); - - return impl::load_file_impl(static_cast(_root), - file.data, options, encoding, &_buffer); -} - -PUGI__FN xml_parse_result xml_document::load_file(const wchar_t *path_, - unsigned int options, - xml_encoding encoding) { - reset(); - - using impl::auto_deleter; // MSVC7 workaround - auto_deleter file(impl::open_file_wide(path_, L"rb"), - fclose); - - return impl::load_file_impl(static_cast(_root), - file.data, options, encoding, &_buffer); -} - -PUGI__FN xml_parse_result xml_document::load_buffer(const void *contents, - size_t size, - unsigned int options, - xml_encoding encoding) { - reset(); - - return impl::load_buffer_impl(static_cast(_root), - _root, const_cast(contents), size, - options, encoding, false, false, &_buffer); -} - -PUGI__FN xml_parse_result xml_document::load_buffer_inplace( - void *contents, size_t size, unsigned int options, xml_encoding encoding) { - reset(); - - return impl::load_buffer_impl(static_cast(_root), - _root, contents, size, options, encoding, true, - false, &_buffer); -} - -PUGI__FN xml_parse_result xml_document::load_buffer_inplace_own( - void *contents, size_t size, unsigned int options, xml_encoding encoding) { - reset(); - - return impl::load_buffer_impl(static_cast(_root), - _root, contents, size, options, encoding, true, - true, &_buffer); -} - -PUGI__FN void xml_document::save(xml_writer &writer, const char_t *indent, - unsigned int flags, - xml_encoding encoding) const { - impl::xml_buffered_writer buffered_writer(writer, encoding); - - if ((flags & format_write_bom) && encoding != encoding_latin1) { - // BOM always represents the codepoint U+FEFF, so just write it in native - // encoding -#ifdef PUGIXML_WCHAR_MODE - unsigned int bom = 0xfeff; - buffered_writer.write(static_cast(bom)); -#else - buffered_writer.write('\xef', '\xbb', '\xbf'); -#endif - } - - if (!(flags & format_no_declaration) && !impl::has_declaration(_root)) { - buffered_writer.write_string(PUGIXML_TEXT("'); - if (!(flags & format_raw)) - buffered_writer.write('\n'); - } - - impl::node_output(buffered_writer, _root, indent, flags, 0); - - buffered_writer.flush(); -} - -#ifndef PUGIXML_NO_STL -PUGI__FN void -xml_document::save(std::basic_ostream> &stream, - const char_t *indent, unsigned int flags, - xml_encoding encoding) const { - xml_writer_stream writer(stream); - - save(writer, indent, flags, encoding); -} - -PUGI__FN void xml_document::save( - std::basic_ostream> &stream, - const char_t *indent, unsigned int flags) const { - xml_writer_stream writer(stream); - - save(writer, indent, flags, encoding_wchar); -} -#endif - -PUGI__FN bool xml_document::save_file(const char *path_, const char_t *indent, - unsigned int flags, - xml_encoding encoding) const { - using impl::auto_deleter; // MSVC7 workaround - auto_deleter file( - fopen(path_, (flags & format_save_file_text) ? "w" : "wb"), fclose); - - return impl::save_file_impl(*this, file.data, indent, flags, encoding); -} - -PUGI__FN bool xml_document::save_file(const wchar_t *path_, - const char_t *indent, unsigned int flags, - xml_encoding encoding) const { - using impl::auto_deleter; // MSVC7 workaround - auto_deleter file( - impl::open_file_wide(path_, - (flags & format_save_file_text) ? L"w" : L"wb"), - fclose); - - return impl::save_file_impl(*this, file.data, indent, flags, encoding); -} - -PUGI__FN xml_node xml_document::document_element() const { - assert(_root); - - for (xml_node_struct *i = _root->first_child; i; i = i->next_sibling) - if (PUGI__NODETYPE(i) == node_element) - return xml_node(i); - - return xml_node(); -} - -#ifndef PUGIXML_NO_STL -PUGI__FN std::string PUGIXML_FUNCTION as_utf8(const wchar_t *str) { - assert(str); - - return impl::as_utf8_impl(str, impl::strlength_wide(str)); -} - -PUGI__FN std::string PUGIXML_FUNCTION -as_utf8(const std::basic_string &str) { - return impl::as_utf8_impl(str.c_str(), str.size()); -} - -PUGI__FN std::basic_string PUGIXML_FUNCTION as_wide(const char *str) { - assert(str); - - return impl::as_wide_impl(str, strlen(str)); -} - -PUGI__FN std::basic_string - PUGIXML_FUNCTION as_wide(const std::string &str) { - return impl::as_wide_impl(str.c_str(), str.size()); -} -#endif - -PUGI__FN void PUGIXML_FUNCTION set_memory_management_functions( - allocation_function allocate, deallocation_function deallocate) { - impl::xml_memory::allocate = allocate; - impl::xml_memory::deallocate = deallocate; -} - -PUGI__FN allocation_function PUGIXML_FUNCTION get_memory_allocation_function() { - return impl::xml_memory::allocate; -} - -PUGI__FN deallocation_function PUGIXML_FUNCTION -get_memory_deallocation_function() { - return impl::xml_memory::deallocate; -} -} // namespace pugi - -#if !defined(PUGIXML_NO_STL) && (defined(_MSC_VER) || defined(__ICC)) -namespace std { -// Workarounds for (non-standard) iterator category detection for older versions -// (MSVC7/IC8 and earlier) -PUGI__FN std::bidirectional_iterator_tag -_Iter_cat(const pugi::xml_node_iterator &) { - return std::bidirectional_iterator_tag(); -} - -PUGI__FN std::bidirectional_iterator_tag -_Iter_cat(const pugi::xml_attribute_iterator &) { - return std::bidirectional_iterator_tag(); -} - -PUGI__FN std::bidirectional_iterator_tag -_Iter_cat(const pugi::xml_named_node_iterator &) { - return std::bidirectional_iterator_tag(); -} -} // namespace std -#endif - -#if !defined(PUGIXML_NO_STL) && defined(__SUNPRO_CC) -namespace std { -// Workarounds for (non-standard) iterator category detection -PUGI__FN std::bidirectional_iterator_tag -__iterator_category(const pugi::xml_node_iterator &) { - return std::bidirectional_iterator_tag(); -} - -PUGI__FN std::bidirectional_iterator_tag -__iterator_category(const pugi::xml_attribute_iterator &) { - return std::bidirectional_iterator_tag(); -} - -PUGI__FN std::bidirectional_iterator_tag -__iterator_category(const pugi::xml_named_node_iterator &) { - return std::bidirectional_iterator_tag(); -} -} // namespace std -#endif - -#ifndef PUGIXML_NO_XPATH -// STL replacements -PUGI__NS_BEGIN -struct equal_to { - template bool operator()(const T &lhs, const T &rhs) const { - return lhs == rhs; - } -}; - -struct not_equal_to { - template bool operator()(const T &lhs, const T &rhs) const { - return lhs != rhs; - } -}; - -struct less { - template bool operator()(const T &lhs, const T &rhs) const { - return lhs < rhs; - } -}; - -struct less_equal { - template bool operator()(const T &lhs, const T &rhs) const { - return lhs <= rhs; - } -}; - -template void swap(T &lhs, T &rhs) { - T temp = lhs; - lhs = rhs; - rhs = temp; -} - -template -I min_element(I begin, I end, const Pred &pred) { - I result = begin; - - for (I it = begin + 1; it != end; ++it) - if (pred(*it, *result)) - result = it; - - return result; -} - -template void reverse(I begin, I end) { - while (end - begin > 1) - swap(*begin++, *--end); -} - -template I unique(I begin, I end) { - // fast skip head - while (end - begin > 1 && *begin != *(begin + 1)) - begin++; - - if (begin == end) - return begin; - - // last written element - I write = begin++; - - // merge unique elements - while (begin != end) { - if (*begin != *write) - *++write = *begin++; - else - begin++; - } - - // past-the-end (write points to live element) - return write + 1; -} - -template void copy_backwards(I begin, I end, I target) { - while (begin != end) - *--target = *--end; -} - -template -void insertion_sort(I begin, I end, const Pred &pred, T *) { - assert(begin != end); - - for (I it = begin + 1; it != end; ++it) { - T val = *it; - - if (pred(val, *begin)) { - // move to front - copy_backwards(begin, it, it + 1); - *begin = val; - } else { - I hole = it; - - // move hole backwards - while (pred(val, *(hole - 1))) { - *hole = *(hole - 1); - hole--; - } - - // fill hole with element - *hole = val; - } - } -} - -// std variant for elements with == -template -void partition(I begin, I middle, I end, const Pred &pred, I *out_eqbeg, - I *out_eqend) { - I eqbeg = middle, eqend = middle + 1; - - // expand equal range - while (eqbeg != begin && *(eqbeg - 1) == *eqbeg) - --eqbeg; - while (eqend != end && *eqend == *eqbeg) - ++eqend; - - // process outer elements - I ltend = eqbeg, gtbeg = eqend; - - for (;;) { - // find the element from the right side that belongs to the left one - for (; gtbeg != end; ++gtbeg) - if (!pred(*eqbeg, *gtbeg)) { - if (*gtbeg == *eqbeg) - swap(*gtbeg, *eqend++); - else - break; - } - - // find the element from the left side that belongs to the right one - for (; ltend != begin; --ltend) - if (!pred(*(ltend - 1), *eqbeg)) { - if (*eqbeg == *(ltend - 1)) - swap(*(ltend - 1), *--eqbeg); - else - break; - } - - // scanned all elements - if (gtbeg == end && ltend == begin) { - *out_eqbeg = eqbeg; - *out_eqend = eqend; - return; - } - - // make room for elements by moving equal area - if (gtbeg == end) { - if (--ltend != --eqbeg) - swap(*ltend, *eqbeg); - swap(*eqbeg, *--eqend); - } else if (ltend == begin) { - if (eqend != gtbeg) - swap(*eqbeg, *eqend); - ++eqend; - swap(*gtbeg++, *eqbeg++); - } else - swap(*gtbeg++, *--ltend); - } -} - -template -void median3(I first, I middle, I last, const Pred &pred) { - if (pred(*middle, *first)) - swap(*middle, *first); - if (pred(*last, *middle)) - swap(*last, *middle); - if (pred(*middle, *first)) - swap(*middle, *first); -} - -template -void median(I first, I middle, I last, const Pred &pred) { - if (last - first <= 40) { - // median of three for small chunks - median3(first, middle, last, pred); - } else { - // median of nine - size_t step = (last - first + 1) / 8; - - median3(first, first + step, first + 2 * step, pred); - median3(middle - step, middle, middle + step, pred); - median3(last - 2 * step, last - step, last, pred); - median3(first + step, middle, last - step, pred); - } -} - -template -void sort(I begin, I end, const Pred &pred) { - // sort large chunks - while (end - begin > 32) { - // find median element - I middle = begin + (end - begin) / 2; - median(begin, middle, end - 1, pred); - - // partition in three chunks (< = >) - I eqbeg, eqend; - partition(begin, middle, end, pred, &eqbeg, &eqend); - - // loop on larger half - if (eqbeg - begin > end - eqend) { - sort(eqend, end, pred); - end = eqbeg; - } else { - sort(begin, eqbeg, pred); - begin = eqend; - } - } - - // insertion sort small chunk - if (begin != end) - insertion_sort(begin, end, pred, &*begin); -} -PUGI__NS_END - -// Allocator used for AST and evaluation stacks -PUGI__NS_BEGIN -static const size_t xpath_memory_page_size = -#ifdef PUGIXML_MEMORY_XPATH_PAGE_SIZE - PUGIXML_MEMORY_XPATH_PAGE_SIZE -#else - 4096 -#endif - ; - -static const uintptr_t xpath_memory_block_alignment = sizeof(double) > - sizeof(void *) - ? sizeof(double) - : sizeof(void *); - -struct xpath_memory_block { - xpath_memory_block *next; - size_t capacity; - - union { - char data[xpath_memory_page_size]; - double alignment; - }; -}; - -class xpath_allocator { - xpath_memory_block *_root; - size_t _root_size; - -public: -#ifdef PUGIXML_NO_EXCEPTIONS - jmp_buf *error_handler; -#endif - - xpath_allocator(xpath_memory_block *root, size_t root_size = 0) - : _root(root), _root_size(root_size) { -#ifdef PUGIXML_NO_EXCEPTIONS - error_handler = 0; -#endif - } - - void *allocate_nothrow(size_t size) { - // round size up to block alignment boundary - size = (size + xpath_memory_block_alignment - 1) & - ~(xpath_memory_block_alignment - 1); - - if (_root_size + size <= _root->capacity) { - void *buf = &_root->data[0] + _root_size; - _root_size += size; - return buf; - } else { - // make sure we have at least 1/4th of the page free after allocation to - // satisfy subsequent allocation requests - size_t block_capacity_base = sizeof(_root->data); - size_t block_capacity_req = size + block_capacity_base / 4; - size_t block_capacity = (block_capacity_base > block_capacity_req) - ? block_capacity_base - : block_capacity_req; - - size_t block_size = block_capacity + offsetof(xpath_memory_block, data); - - xpath_memory_block *block = - static_cast(xml_memory::allocate(block_size)); - if (!block) - return 0; - - block->next = _root; - block->capacity = block_capacity; - - _root = block; - _root_size = size; - - return block->data; - } - } - - void *allocate(size_t size) { - void *result = allocate_nothrow(size); - - if (!result) { -#ifdef PUGIXML_NO_EXCEPTIONS - assert(error_handler); - longjmp(*error_handler, 1); -#else - throw std::bad_alloc(); -#endif - } - - return result; - } - - void *reallocate(void *ptr, size_t old_size, size_t new_size) { - // round size up to block alignment boundary - old_size = (old_size + xpath_memory_block_alignment - 1) & - ~(xpath_memory_block_alignment - 1); - new_size = (new_size + xpath_memory_block_alignment - 1) & - ~(xpath_memory_block_alignment - 1); - - // we can only reallocate the last object - assert(ptr == 0 || - static_cast(ptr) + old_size == &_root->data[0] + _root_size); - - // adjust root size so that we have not allocated the object at all - bool only_object = (_root_size == old_size); - - if (ptr) - _root_size -= old_size; - - // allocate a new version (this will obviously reuse the memory if possible) - void *result = allocate(new_size); - assert(result); - - // we have a new block - if (result != ptr && ptr) { - // copy old data - assert(new_size >= old_size); - memcpy(result, ptr, old_size); - - // free the previous page if it had no other objects - if (only_object) { - assert(_root->data == result); - assert(_root->next); - - xpath_memory_block *next = _root->next->next; - - if (next) { - // deallocate the whole page, unless it was the first one - xml_memory::deallocate(_root->next); - _root->next = next; - } - } - } - - return result; - } - - void revert(const xpath_allocator &state) { - // free all new pages - xpath_memory_block *cur = _root; - - while (cur != state._root) { - xpath_memory_block *next = cur->next; - - xml_memory::deallocate(cur); - - cur = next; - } - - // restore state - _root = state._root; - _root_size = state._root_size; - } - - void release() { - xpath_memory_block *cur = _root; - assert(cur); - - while (cur->next) { - xpath_memory_block *next = cur->next; - - xml_memory::deallocate(cur); - - cur = next; - } - } -}; - -struct xpath_allocator_capture { - xpath_allocator_capture(xpath_allocator *alloc) - : _target(alloc), _state(*alloc) {} - - ~xpath_allocator_capture() { _target->revert(_state); } - - xpath_allocator *_target; - xpath_allocator _state; -}; - -struct xpath_stack { - xpath_allocator *result; - xpath_allocator *temp; -}; - -struct xpath_stack_data { - xpath_memory_block blocks[2]; - xpath_allocator result; - xpath_allocator temp; - xpath_stack stack; - -#ifdef PUGIXML_NO_EXCEPTIONS - jmp_buf error_handler; -#endif - - xpath_stack_data() : result(blocks + 0), temp(blocks + 1) { - blocks[0].next = blocks[1].next = 0; - blocks[0].capacity = blocks[1].capacity = sizeof(blocks[0].data); - - stack.result = &result; - stack.temp = &temp; - -#ifdef PUGIXML_NO_EXCEPTIONS - result.error_handler = temp.error_handler = &error_handler; -#endif - } - - ~xpath_stack_data() { - result.release(); - temp.release(); - } -}; -PUGI__NS_END - -// String class -PUGI__NS_BEGIN -class xpath_string { - const char_t *_buffer; - bool _uses_heap; - size_t _length_heap; - - static char_t *duplicate_string(const char_t *string, size_t length, - xpath_allocator *alloc) { - char_t *result = - static_cast(alloc->allocate((length + 1) * sizeof(char_t))); - assert(result); - - memcpy(result, string, length * sizeof(char_t)); - result[length] = 0; - - return result; - } - - xpath_string(const char_t *buffer, bool uses_heap_, size_t length_heap) - : _buffer(buffer), _uses_heap(uses_heap_), _length_heap(length_heap) {} - -public: - static xpath_string from_const(const char_t *str) { - return xpath_string(str, false, 0); - } - - static xpath_string from_heap_preallocated(const char_t *begin, - const char_t *end) { - assert(begin <= end && *end == 0); - - return xpath_string(begin, true, static_cast(end - begin)); - } - - static xpath_string from_heap(const char_t *begin, const char_t *end, - xpath_allocator *alloc) { - assert(begin <= end); - - size_t length = static_cast(end - begin); - - return length == 0 ? xpath_string() - : xpath_string(duplicate_string(begin, length, alloc), - true, length); - } - - xpath_string() - : _buffer(PUGIXML_TEXT("")), _uses_heap(false), _length_heap(0) {} - - void append(const xpath_string &o, xpath_allocator *alloc) { - // skip empty sources - if (!*o._buffer) - return; - - // fast append for constant empty target and constant source - if (!*_buffer && !_uses_heap && !o._uses_heap) { - _buffer = o._buffer; - } else { - // need to make heap copy - size_t target_length = length(); - size_t source_length = o.length(); - size_t result_length = target_length + source_length; - - // allocate new buffer - char_t *result = static_cast( - alloc->reallocate(_uses_heap ? const_cast(_buffer) : 0, - (target_length + 1) * sizeof(char_t), - (result_length + 1) * sizeof(char_t))); - assert(result); - - // append first string to the new buffer in case there was no reallocation - if (!_uses_heap) - memcpy(result, _buffer, target_length * sizeof(char_t)); - - // append second string to the new buffer - memcpy(result + target_length, o._buffer, source_length * sizeof(char_t)); - result[result_length] = 0; - - // finalize - _buffer = result; - _uses_heap = true; - _length_heap = result_length; - } - } - - const char_t *c_str() const { return _buffer; } - - size_t length() const { - return _uses_heap ? _length_heap : strlength(_buffer); - } - - char_t *data(xpath_allocator *alloc) { - // make private heap copy - if (!_uses_heap) { - size_t length_ = strlength(_buffer); - - _buffer = duplicate_string(_buffer, length_, alloc); - _uses_heap = true; - _length_heap = length_; - } - - return const_cast(_buffer); - } - - bool empty() const { return *_buffer == 0; } - - bool operator==(const xpath_string &o) const { - return strequal(_buffer, o._buffer); - } - - bool operator!=(const xpath_string &o) const { - return !strequal(_buffer, o._buffer); - } - - bool uses_heap() const { return _uses_heap; } -}; -PUGI__NS_END - -PUGI__NS_BEGIN -PUGI__FN bool starts_with(const char_t *string, const char_t *pattern) { - while (*pattern && *string == *pattern) { - string++; - pattern++; - } - - return *pattern == 0; -} - -PUGI__FN const char_t *find_char(const char_t *s, char_t c) { -#ifdef PUGIXML_WCHAR_MODE - return wcschr(s, c); -#else - return strchr(s, c); -#endif -} - -PUGI__FN const char_t *find_substring(const char_t *s, const char_t *p) { -#ifdef PUGIXML_WCHAR_MODE - // MSVC6 wcsstr bug workaround (if s is empty it always returns 0) - return (*p == 0) ? s : wcsstr(s, p); -#else - return strstr(s, p); -#endif -} - -// Converts symbol to lower case, if it is an ASCII one -PUGI__FN char_t tolower_ascii(char_t ch) { - return static_cast(ch - 'A') < 26 - ? static_cast(ch | ' ') - : ch; -} - -PUGI__FN xpath_string string_value(const xpath_node &na, - xpath_allocator *alloc) { - if (na.attribute()) - return xpath_string::from_const(na.attribute().value()); - else { - xml_node n = na.node(); - - switch (n.type()) { - case node_pcdata: - case node_cdata: - case node_comment: - case node_pi: - return xpath_string::from_const(n.value()); - - case node_document: - case node_element: { - xpath_string result; - - xml_node cur = n.first_child(); - - while (cur && cur != n) { - if (cur.type() == node_pcdata || cur.type() == node_cdata) - result.append(xpath_string::from_const(cur.value()), alloc); - - if (cur.first_child()) - cur = cur.first_child(); - else if (cur.next_sibling()) - cur = cur.next_sibling(); - else { - while (!cur.next_sibling() && cur != n) - cur = cur.parent(); - - if (cur != n) - cur = cur.next_sibling(); - } - } - - return result; - } - - default: - return xpath_string(); - } - } -} - -PUGI__FN bool node_is_before_sibling(xml_node_struct *ln, xml_node_struct *rn) { - assert(ln->parent == rn->parent); - - // there is no common ancestor (the shared parent is null), nodes are from - // different documents - if (!ln->parent) - return ln < rn; - - // determine sibling order - xml_node_struct *ls = ln; - xml_node_struct *rs = rn; - - while (ls && rs) { - if (ls == rn) - return true; - if (rs == ln) - return false; - - ls = ls->next_sibling; - rs = rs->next_sibling; - } - - // if rn sibling chain ended ln must be before rn - return !rs; -} - -PUGI__FN bool node_is_before(xml_node_struct *ln, xml_node_struct *rn) { - // find common ancestor at the same depth, if any - xml_node_struct *lp = ln; - xml_node_struct *rp = rn; - - while (lp && rp && lp->parent != rp->parent) { - lp = lp->parent; - rp = rp->parent; - } - - // parents are the same! - if (lp && rp) - return node_is_before_sibling(lp, rp); - - // nodes are at different depths, need to normalize heights - bool left_higher = !lp; - - while (lp) { - lp = lp->parent; - ln = ln->parent; - } - - while (rp) { - rp = rp->parent; - rn = rn->parent; - } - - // one node is the ancestor of the other - if (ln == rn) - return left_higher; - - // find common ancestor... again - while (ln->parent != rn->parent) { - ln = ln->parent; - rn = rn->parent; - } - - return node_is_before_sibling(ln, rn); -} - -PUGI__FN bool node_is_ancestor(xml_node_struct *parent, xml_node_struct *node) { - while (node && node != parent) - node = node->parent; - - return parent && node == parent; -} - -PUGI__FN const void *document_buffer_order(const xpath_node &xnode) { - xml_node_struct *node = xnode.node().internal_object(); - - if (node) { - if ((get_document(node).header & xml_memory_page_contents_shared_mask) == - 0) { - if (node->name && - (node->header & - impl::xml_memory_page_name_allocated_or_shared_mask) == 0) - return node->name; - if (node->value && - (node->header & - impl::xml_memory_page_value_allocated_or_shared_mask) == 0) - return node->value; - } - - return 0; - } - - xml_attribute_struct *attr = xnode.attribute().internal_object(); - - if (attr) { - if ((get_document(attr).header & xml_memory_page_contents_shared_mask) == - 0) { - if ((attr->header & - impl::xml_memory_page_name_allocated_or_shared_mask) == 0) - return attr->name; - if ((attr->header & - impl::xml_memory_page_value_allocated_or_shared_mask) == 0) - return attr->value; - } - - return 0; - } - - return 0; -} - -struct document_order_comparator { - bool operator()(const xpath_node &lhs, const xpath_node &rhs) const { - // optimized document order based check - const void *lo = document_buffer_order(lhs); - const void *ro = document_buffer_order(rhs); - - if (lo && ro) - return lo < ro; - - // slow comparison - xml_node ln = lhs.node(), rn = rhs.node(); - - // compare attributes - if (lhs.attribute() && rhs.attribute()) { - // shared parent - if (lhs.parent() == rhs.parent()) { - // determine sibling order - for (xml_attribute a = lhs.attribute(); a; a = a.next_attribute()) - if (a == rhs.attribute()) - return true; - - return false; - } - - // compare attribute parents - ln = lhs.parent(); - rn = rhs.parent(); - } else if (lhs.attribute()) { - // attributes go after the parent element - if (lhs.parent() == rhs.node()) - return false; - - ln = lhs.parent(); - } else if (rhs.attribute()) { - // attributes go after the parent element - if (rhs.parent() == lhs.node()) - return true; - - rn = rhs.parent(); - } - - if (ln == rn) - return false; - - if (!ln || !rn) - return ln < rn; - - return node_is_before(ln.internal_object(), rn.internal_object()); - } -}; - -struct duplicate_comparator { - bool operator()(const xpath_node &lhs, const xpath_node &rhs) const { - if (lhs.attribute()) - return rhs.attribute() ? lhs.attribute() < rhs.attribute() : true; - else - return rhs.attribute() ? false : lhs.node() < rhs.node(); - } -}; - -PUGI__FN double gen_nan() { -#if defined(__STDC_IEC_559__) || \ - ((FLT_RADIX - 0 == 2) && (FLT_MAX_EXP - 0 == 128) && \ - (FLT_MANT_DIG - 0 == 24)) - union { - float f; - uint32_t i; - } u[sizeof(float) == sizeof(uint32_t) ? 1 : -1]; - u[0].i = 0x7fc00000; - return u[0].f; -#else - // fallback - const volatile double zero = 0.0; - return zero / zero; -#endif -} - -PUGI__FN bool is_nan(double value) { -#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) - return !!_isnan(value); -#elif defined(fpclassify) && defined(FP_NAN) - return fpclassify(value) == FP_NAN; -#else - // fallback - const volatile double v = value; - return v != v; -#endif -} - -PUGI__FN const char_t *convert_number_to_string_special(double value) { -#if defined(PUGI__MSVC_CRT_VERSION) || defined(__BORLANDC__) - if (_finite(value)) - return (value == 0) ? PUGIXML_TEXT("0") : 0; - if (_isnan(value)) - return PUGIXML_TEXT("NaN"); - return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity"); -#elif defined(fpclassify) && defined(FP_NAN) && defined(FP_INFINITE) && \ - defined(FP_ZERO) - switch (fpclassify(value)) { - case FP_NAN: - return PUGIXML_TEXT("NaN"); - - case FP_INFINITE: - return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity"); - - case FP_ZERO: - return PUGIXML_TEXT("0"); - - default: - return 0; - } -#else - // fallback - const volatile double v = value; - - if (v == 0) - return PUGIXML_TEXT("0"); - if (v != v) - return PUGIXML_TEXT("NaN"); - if (v * 2 == v) - return value > 0 ? PUGIXML_TEXT("Infinity") : PUGIXML_TEXT("-Infinity"); - return 0; -#endif -} - -PUGI__FN bool convert_number_to_boolean(double value) { - return (value != 0 && !is_nan(value)); -} - -PUGI__FN void truncate_zeros(char *begin, char *end) { - while (begin != end && end[-1] == '0') - end--; - - *end = 0; -} - -// gets mantissa digits in the form of 0.xxxxx with 0. implied and the exponent -#if defined(PUGI__MSVC_CRT_VERSION) && PUGI__MSVC_CRT_VERSION >= 1400 && \ - !defined(_WIN32_WCE) -PUGI__FN void convert_number_to_mantissa_exponent(double value, char *buffer, - size_t buffer_size, - char **out_mantissa, - int *out_exponent) { - // get base values - int sign, exponent; - _ecvt_s(buffer, buffer_size, value, DBL_DIG + 1, &exponent, &sign); - - // truncate redundant zeros - truncate_zeros(buffer, buffer + strlen(buffer)); - - // fill results - *out_mantissa = buffer; - *out_exponent = exponent; -} -#else -PUGI__FN void convert_number_to_mantissa_exponent(double value, char *buffer, - size_t buffer_size, - char **out_mantissa, - int *out_exponent) { - // get a scientific notation value with IEEE DBL_DIG decimals - sprintf(buffer, "%.*e", DBL_DIG, value); - assert(strlen(buffer) < buffer_size); - (void)!buffer_size; - - // get the exponent (possibly negative) - char *exponent_string = strchr(buffer, 'e'); - assert(exponent_string); - - int exponent = atoi(exponent_string + 1); - - // extract mantissa string: skip sign - char *mantissa = buffer[0] == '-' ? buffer + 1 : buffer; - assert(mantissa[0] != '0' && mantissa[1] == '.'); - - // divide mantissa by 10 to eliminate integer part - mantissa[1] = mantissa[0]; - mantissa++; - exponent++; - - // remove extra mantissa digits and zero-terminate mantissa - truncate_zeros(mantissa, exponent_string); - - // fill results - *out_mantissa = mantissa; - *out_exponent = exponent; -} -#endif - -PUGI__FN xpath_string convert_number_to_string(double value, - xpath_allocator *alloc) { - // try special number conversion - const char_t *special = convert_number_to_string_special(value); - if (special) - return xpath_string::from_const(special); - - // get mantissa + exponent form - char mantissa_buffer[32]; - - char *mantissa; - int exponent; - convert_number_to_mantissa_exponent( - value, mantissa_buffer, sizeof(mantissa_buffer), &mantissa, &exponent); - - // allocate a buffer of suitable length for the number - size_t result_size = - strlen(mantissa_buffer) + (exponent > 0 ? exponent : -exponent) + 4; - char_t *result = - static_cast(alloc->allocate(sizeof(char_t) * result_size)); - assert(result); - - // make the number! - char_t *s = result; - - // sign - if (value < 0) - *s++ = '-'; - - // integer part - if (exponent <= 0) { - *s++ = '0'; - } else { - while (exponent > 0) { - assert(*mantissa == 0 || - static_cast(static_cast(*mantissa) - - '0') <= 9); - *s++ = *mantissa ? *mantissa++ : '0'; - exponent--; - } - } - - // fractional part - if (*mantissa) { - // decimal point - *s++ = '.'; - - // extra zeroes from negative exponent - while (exponent < 0) { - *s++ = '0'; - exponent++; - } - - // extra mantissa digits - while (*mantissa) { - assert(static_cast(*mantissa - '0') <= 9); - *s++ = *mantissa++; - } - } - - // zero-terminate - assert(s < result + result_size); - *s = 0; - - return xpath_string::from_heap_preallocated(result, s); -} - -PUGI__FN bool check_string_to_number_format(const char_t *string) { - // parse leading whitespace - while (PUGI__IS_CHARTYPE(*string, ct_space)) - ++string; - - // parse sign - if (*string == '-') - ++string; - - if (!*string) - return false; - - // if there is no integer part, there should be a decimal part with at least - // one digit - if (!PUGI__IS_CHARTYPEX(string[0], ctx_digit) && - (string[0] != '.' || !PUGI__IS_CHARTYPEX(string[1], ctx_digit))) - return false; - - // parse integer part - while (PUGI__IS_CHARTYPEX(*string, ctx_digit)) - ++string; - - // parse decimal part - if (*string == '.') { - ++string; - - while (PUGI__IS_CHARTYPEX(*string, ctx_digit)) - ++string; - } - - // parse trailing whitespace - while (PUGI__IS_CHARTYPE(*string, ct_space)) - ++string; - - return *string == 0; -} - -PUGI__FN double convert_string_to_number(const char_t *string) { - // check string format - if (!check_string_to_number_format(string)) - return gen_nan(); - - // parse string -#ifdef PUGIXML_WCHAR_MODE - return wcstod(string, 0); -#else - return strtod(string, 0); -#endif -} - -PUGI__FN bool convert_string_to_number_scratch(char_t (&buffer)[32], - const char_t *begin, - const char_t *end, - double *out_result) { - size_t length = static_cast(end - begin); - char_t *scratch = buffer; - - if (length >= sizeof(buffer) / sizeof(buffer[0])) { - // need to make dummy on-heap copy - scratch = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!scratch) - return false; - } - - // copy string to zero-terminated buffer and perform conversion - memcpy(scratch, begin, length * sizeof(char_t)); - scratch[length] = 0; - - *out_result = convert_string_to_number(scratch); - - // free dummy buffer - if (scratch != buffer) - xml_memory::deallocate(scratch); - - return true; -} - -PUGI__FN double round_nearest(double value) { return floor(value + 0.5); } - -PUGI__FN double round_nearest_nzero(double value) { - // same as round_nearest, but returns -0 for [-0.5, -0] - // ceil is used to differentiate between +0 and -0 (we return -0 for [-0.5, - // -0] and +0 for +0) - return (value >= -0.5 && value <= 0) ? ceil(value) : floor(value + 0.5); -} - -PUGI__FN const char_t *qualified_name(const xpath_node &node) { - return node.attribute() ? node.attribute().name() : node.node().name(); -} - -PUGI__FN const char_t *local_name(const xpath_node &node) { - const char_t *name = qualified_name(node); - const char_t *p = find_char(name, ':'); - - return p ? p + 1 : name; -} - -struct namespace_uri_predicate { - const char_t *prefix; - size_t prefix_length; - - namespace_uri_predicate(const char_t *name) { - const char_t *pos = find_char(name, ':'); - - prefix = pos ? name : 0; - prefix_length = pos ? static_cast(pos - name) : 0; - } - - bool operator()(xml_attribute a) const { - const char_t *name = a.name(); - - if (!starts_with(name, PUGIXML_TEXT("xmlns"))) - return false; - - return prefix ? name[5] == ':' && - strequalrange(name + 6, prefix, prefix_length) - : name[5] == 0; - } -}; - -PUGI__FN const char_t *namespace_uri(xml_node node) { - namespace_uri_predicate pred = node.name(); - - xml_node p = node; - - while (p) { - xml_attribute a = p.find_attribute(pred); - - if (a) - return a.value(); - - p = p.parent(); - } - - return PUGIXML_TEXT(""); -} - -PUGI__FN const char_t *namespace_uri(xml_attribute attr, xml_node parent) { - namespace_uri_predicate pred = attr.name(); - - // Default namespace does not apply to attributes - if (!pred.prefix) - return PUGIXML_TEXT(""); - - xml_node p = parent; - - while (p) { - xml_attribute a = p.find_attribute(pred); - - if (a) - return a.value(); - - p = p.parent(); - } - - return PUGIXML_TEXT(""); -} - -PUGI__FN const char_t *namespace_uri(const xpath_node &node) { - return node.attribute() ? namespace_uri(node.attribute(), node.parent()) - : namespace_uri(node.node()); -} - -PUGI__FN char_t *normalize_space(char_t *buffer) { - char_t *write = buffer; - - for (char_t *it = buffer; *it;) { - char_t ch = *it++; - - if (PUGI__IS_CHARTYPE(ch, ct_space)) { - // replace whitespace sequence with single space - while (PUGI__IS_CHARTYPE(*it, ct_space)) - it++; - - // avoid leading spaces - if (write != buffer) - *write++ = ' '; - } else - *write++ = ch; - } - - // remove trailing space - if (write != buffer && PUGI__IS_CHARTYPE(write[-1], ct_space)) - write--; - - // zero-terminate - *write = 0; - - return write; -} - -PUGI__FN char_t *translate(char_t *buffer, const char_t *from, const char_t *to, - size_t to_length) { - char_t *write = buffer; - - while (*buffer) { - PUGI__DMC_VOLATILE char_t ch = *buffer++; - - const char_t *pos = find_char(from, ch); - - if (!pos) - *write++ = ch; // do not process - else if (static_cast(pos - from) < to_length) - *write++ = to[pos - from]; // replace - } - - // zero-terminate - *write = 0; - - return write; -} - -PUGI__FN unsigned char *translate_table_generate(xpath_allocator *alloc, - const char_t *from, - const char_t *to) { - unsigned char table[128] = {0}; - - while (*from) { - unsigned int fc = static_cast(*from); - unsigned int tc = static_cast(*to); - - if (fc >= 128 || tc >= 128) - return 0; - - // code=128 means "skip character" - if (!table[fc]) - table[fc] = static_cast(tc ? tc : 128); - - from++; - if (tc) - to++; - } - - for (int i = 0; i < 128; ++i) - if (!table[i]) - table[i] = static_cast(i); - - void *result = alloc->allocate_nothrow(sizeof(table)); - - if (result) { - memcpy(result, table, sizeof(table)); - } - - return static_cast(result); -} - -PUGI__FN char_t *translate_table(char_t *buffer, const unsigned char *table) { - char_t *write = buffer; - - while (*buffer) { - char_t ch = *buffer++; - unsigned int index = static_cast(ch); - - if (index < 128) { - unsigned char code = table[index]; - - // code=128 means "skip character" (table size is 128 so 128 can be a - // special value) this code skips these characters without extra branches - *write = static_cast(code); - write += 1 - (code >> 7); - } else { - *write++ = ch; - } - } - - // zero-terminate - *write = 0; - - return write; -} - -inline bool is_xpath_attribute(const char_t *name) { - return !(starts_with(name, PUGIXML_TEXT("xmlns")) && - (name[5] == 0 || name[5] == ':')); -} - -struct xpath_variable_boolean : xpath_variable { - xpath_variable_boolean() : xpath_variable(xpath_type_boolean), value(false) {} - - bool value; - char_t name[1]; -}; - -struct xpath_variable_number : xpath_variable { - xpath_variable_number() : xpath_variable(xpath_type_number), value(0) {} - - double value; - char_t name[1]; -}; - -struct xpath_variable_string : xpath_variable { - xpath_variable_string() : xpath_variable(xpath_type_string), value(0) {} - - ~xpath_variable_string() { - if (value) - xml_memory::deallocate(value); - } - - char_t *value; - char_t name[1]; -}; - -struct xpath_variable_node_set : xpath_variable { - xpath_variable_node_set() : xpath_variable(xpath_type_node_set) {} - - xpath_node_set value; - char_t name[1]; -}; - -static const xpath_node_set dummy_node_set; - -PUGI__FN unsigned int hash_string(const char_t *str) { - // Jenkins one-at-a-time hash - // (http://en.wikipedia.org/wiki/Jenkins_hash_function#one-at-a-time) - unsigned int result = 0; - - while (*str) { - result += static_cast(*str++); - result += result << 10; - result ^= result >> 6; - } - - result += result << 3; - result ^= result >> 11; - result += result << 15; - - return result; -} - -template PUGI__FN T *new_xpath_variable(const char_t *name) { - size_t length = strlength(name); - if (length == 0) - return 0; // empty variable names are invalid - - // $$ we can't use offsetof(T, name) because T is non-POD, so we just allocate - // additional length characters - void *memory = xml_memory::allocate(sizeof(T) + length * sizeof(char_t)); - if (!memory) - return 0; - - T *result = new (memory) T(); - - memcpy(result->name, name, (length + 1) * sizeof(char_t)); - - return result; -} - -PUGI__FN xpath_variable *new_xpath_variable(xpath_value_type type, - const char_t *name) { - switch (type) { - case xpath_type_node_set: - return new_xpath_variable(name); - - case xpath_type_number: - return new_xpath_variable(name); - - case xpath_type_string: - return new_xpath_variable(name); - - case xpath_type_boolean: - return new_xpath_variable(name); - - default: - return 0; - } -} - -template PUGI__FN void delete_xpath_variable(T *var) { - var->~T(); - xml_memory::deallocate(var); -} - -PUGI__FN void delete_xpath_variable(xpath_value_type type, - xpath_variable *var) { - switch (type) { - case xpath_type_node_set: - delete_xpath_variable(static_cast(var)); - break; - - case xpath_type_number: - delete_xpath_variable(static_cast(var)); - break; - - case xpath_type_string: - delete_xpath_variable(static_cast(var)); - break; - - case xpath_type_boolean: - delete_xpath_variable(static_cast(var)); - break; - - default: - assert(!"Invalid variable type"); - } -} - -PUGI__FN bool copy_xpath_variable(xpath_variable *lhs, - const xpath_variable *rhs) { - switch (rhs->type()) { - case xpath_type_node_set: - return lhs->set(static_cast(rhs)->value); - - case xpath_type_number: - return lhs->set(static_cast(rhs)->value); - - case xpath_type_string: - return lhs->set(static_cast(rhs)->value); - - case xpath_type_boolean: - return lhs->set(static_cast(rhs)->value); - - default: - assert(!"Invalid variable type"); - return false; - } -} - -PUGI__FN bool get_variable_scratch(char_t (&buffer)[32], - xpath_variable_set *set, const char_t *begin, - const char_t *end, - xpath_variable **out_result) { - size_t length = static_cast(end - begin); - char_t *scratch = buffer; - - if (length >= sizeof(buffer) / sizeof(buffer[0])) { - // need to make dummy on-heap copy - scratch = static_cast( - xml_memory::allocate((length + 1) * sizeof(char_t))); - if (!scratch) - return false; - } - - // copy string to zero-terminated buffer and perform lookup - memcpy(scratch, begin, length * sizeof(char_t)); - scratch[length] = 0; - - *out_result = set->get(scratch); - - // free dummy buffer - if (scratch != buffer) - xml_memory::deallocate(scratch); - - return true; -} -PUGI__NS_END - -// Internal node set class -PUGI__NS_BEGIN -PUGI__FN xpath_node_set::type_t xpath_get_order(const xpath_node *begin, - const xpath_node *end) { - if (end - begin < 2) - return xpath_node_set::type_sorted; - - document_order_comparator cmp; - - bool first = cmp(begin[0], begin[1]); - - for (const xpath_node *it = begin + 1; it + 1 < end; ++it) - if (cmp(it[0], it[1]) != first) - return xpath_node_set::type_unsorted; - - return first ? xpath_node_set::type_sorted - : xpath_node_set::type_sorted_reverse; -} - -PUGI__FN xpath_node_set::type_t xpath_sort(xpath_node *begin, xpath_node *end, - xpath_node_set::type_t type, - bool rev) { - xpath_node_set::type_t order = - rev ? xpath_node_set::type_sorted_reverse : xpath_node_set::type_sorted; - - if (type == xpath_node_set::type_unsorted) { - xpath_node_set::type_t sorted = xpath_get_order(begin, end); - - if (sorted == xpath_node_set::type_unsorted) { - sort(begin, end, document_order_comparator()); - - type = xpath_node_set::type_sorted; - } else - type = sorted; - } - - if (type != order) - reverse(begin, end); - - return order; -} - -PUGI__FN xpath_node xpath_first(const xpath_node *begin, const xpath_node *end, - xpath_node_set::type_t type) { - if (begin == end) - return xpath_node(); - - switch (type) { - case xpath_node_set::type_sorted: - return *begin; - - case xpath_node_set::type_sorted_reverse: - return *(end - 1); - - case xpath_node_set::type_unsorted: - return *min_element(begin, end, document_order_comparator()); - - default: - assert(!"Invalid node set type"); - return xpath_node(); - } -} - -class xpath_node_set_raw { - xpath_node_set::type_t _type; - - xpath_node *_begin; - xpath_node *_end; - xpath_node *_eos; - -public: - xpath_node_set_raw() - : _type(xpath_node_set::type_unsorted), _begin(0), _end(0), _eos(0) {} - - xpath_node *begin() const { return _begin; } - - xpath_node *end() const { return _end; } - - bool empty() const { return _begin == _end; } - - size_t size() const { return static_cast(_end - _begin); } - - xpath_node first() const { return xpath_first(_begin, _end, _type); } - - void push_back_grow(const xpath_node &node, xpath_allocator *alloc); - - void push_back(const xpath_node &node, xpath_allocator *alloc) { - if (_end != _eos) - *_end++ = node; - else - push_back_grow(node, alloc); - } - - void append(const xpath_node *begin_, const xpath_node *end_, - xpath_allocator *alloc) { - if (begin_ == end_) - return; - - size_t size_ = static_cast(_end - _begin); - size_t capacity = static_cast(_eos - _begin); - size_t count = static_cast(end_ - begin_); - - if (size_ + count > capacity) { - // reallocate the old array or allocate a new one - xpath_node *data = static_cast( - alloc->reallocate(_begin, capacity * sizeof(xpath_node), - (size_ + count) * sizeof(xpath_node))); - assert(data); - - // finalize - _begin = data; - _end = data + size_; - _eos = data + size_ + count; - } - - memcpy(_end, begin_, count * sizeof(xpath_node)); - _end += count; - } - - void sort_do() { _type = xpath_sort(_begin, _end, _type, false); } - - void truncate(xpath_node *pos) { - assert(_begin <= pos && pos <= _end); - - _end = pos; - } - - void remove_duplicates() { - if (_type == xpath_node_set::type_unsorted) - sort(_begin, _end, duplicate_comparator()); - - _end = unique(_begin, _end); - } - - xpath_node_set::type_t type() const { return _type; } - - void set_type(xpath_node_set::type_t value) { _type = value; } -}; - -PUGI__FN_NO_INLINE void -xpath_node_set_raw::push_back_grow(const xpath_node &node, - xpath_allocator *alloc) { - size_t capacity = static_cast(_eos - _begin); - - // get new capacity (1.5x rule) - size_t new_capacity = capacity + capacity / 2 + 1; - - // reallocate the old array or allocate a new one - xpath_node *data = static_cast( - alloc->reallocate(_begin, capacity * sizeof(xpath_node), - new_capacity * sizeof(xpath_node))); - assert(data); - - // finalize - _begin = data; - _end = data + capacity; - _eos = data + new_capacity; - - // push - *_end++ = node; -} -PUGI__NS_END - -PUGI__NS_BEGIN -struct xpath_context { - xpath_node n; - size_t position, size; - - xpath_context(const xpath_node &n_, size_t position_, size_t size_) - : n(n_), position(position_), size(size_) {} -}; - -enum lexeme_t { - lex_none = 0, - lex_equal, - lex_not_equal, - lex_less, - lex_greater, - lex_less_or_equal, - lex_greater_or_equal, - lex_plus, - lex_minus, - lex_multiply, - lex_union, - lex_var_ref, - lex_open_brace, - lex_close_brace, - lex_quoted_string, - lex_number, - lex_slash, - lex_double_slash, - lex_open_square_brace, - lex_close_square_brace, - lex_string, - lex_comma, - lex_axis_attribute, - lex_dot, - lex_double_dot, - lex_double_colon, - lex_eof -}; - -struct xpath_lexer_string { - const char_t *begin; - const char_t *end; - - xpath_lexer_string() : begin(0), end(0) {} - - bool operator==(const char_t *other) const { - size_t length = static_cast(end - begin); - - return strequalrange(other, begin, length); - } -}; - -class xpath_lexer { - const char_t *_cur; - const char_t *_cur_lexeme_pos; - xpath_lexer_string _cur_lexeme_contents; - - lexeme_t _cur_lexeme; - -public: - explicit xpath_lexer(const char_t *query) : _cur(query) { next(); } - - const char_t *state() const { return _cur; } - - void next() { - const char_t *cur = _cur; - - while (PUGI__IS_CHARTYPE(*cur, ct_space)) - ++cur; - - // save lexeme position for error reporting - _cur_lexeme_pos = cur; - - switch (*cur) { - case 0: - _cur_lexeme = lex_eof; - break; - - case '>': - if (*(cur + 1) == '=') { - cur += 2; - _cur_lexeme = lex_greater_or_equal; - } else { - cur += 1; - _cur_lexeme = lex_greater; - } - break; - - case '<': - if (*(cur + 1) == '=') { - cur += 2; - _cur_lexeme = lex_less_or_equal; - } else { - cur += 1; - _cur_lexeme = lex_less; - } - break; - - case '!': - if (*(cur + 1) == '=') { - cur += 2; - _cur_lexeme = lex_not_equal; - } else { - _cur_lexeme = lex_none; - } - break; - - case '=': - cur += 1; - _cur_lexeme = lex_equal; - - break; - - case '+': - cur += 1; - _cur_lexeme = lex_plus; - - break; - - case '-': - cur += 1; - _cur_lexeme = lex_minus; - - break; - - case '*': - cur += 1; - _cur_lexeme = lex_multiply; - - break; - - case '|': - cur += 1; - _cur_lexeme = lex_union; - - break; - - case '$': - cur += 1; - - if (PUGI__IS_CHARTYPEX(*cur, ctx_start_symbol)) { - _cur_lexeme_contents.begin = cur; - - while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) - cur++; - - if (cur[0] == ':' && PUGI__IS_CHARTYPEX(cur[1], ctx_symbol)) // qname - { - cur++; // : - - while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) - cur++; - } - - _cur_lexeme_contents.end = cur; - - _cur_lexeme = lex_var_ref; - } else { - _cur_lexeme = lex_none; - } - - break; - - case '(': - cur += 1; - _cur_lexeme = lex_open_brace; - - break; - - case ')': - cur += 1; - _cur_lexeme = lex_close_brace; - - break; - - case '[': - cur += 1; - _cur_lexeme = lex_open_square_brace; - - break; - - case ']': - cur += 1; - _cur_lexeme = lex_close_square_brace; - - break; - - case ',': - cur += 1; - _cur_lexeme = lex_comma; - - break; - - case '/': - if (*(cur + 1) == '/') { - cur += 2; - _cur_lexeme = lex_double_slash; - } else { - cur += 1; - _cur_lexeme = lex_slash; - } - break; - - case '.': - if (*(cur + 1) == '.') { - cur += 2; - _cur_lexeme = lex_double_dot; - } else if (PUGI__IS_CHARTYPEX(*(cur + 1), ctx_digit)) { - _cur_lexeme_contents.begin = cur; // . - - ++cur; - - while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) - cur++; - - _cur_lexeme_contents.end = cur; - - _cur_lexeme = lex_number; - } else { - cur += 1; - _cur_lexeme = lex_dot; - } - break; - - case '@': - cur += 1; - _cur_lexeme = lex_axis_attribute; - - break; - - case '"': - case '\'': { - char_t terminator = *cur; - - ++cur; - - _cur_lexeme_contents.begin = cur; - while (*cur && *cur != terminator) - cur++; - _cur_lexeme_contents.end = cur; - - if (!*cur) - _cur_lexeme = lex_none; - else { - cur += 1; - _cur_lexeme = lex_quoted_string; - } - - break; - } - - case ':': - if (*(cur + 1) == ':') { - cur += 2; - _cur_lexeme = lex_double_colon; - } else { - _cur_lexeme = lex_none; - } - break; - - default: - if (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) { - _cur_lexeme_contents.begin = cur; - - while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) - cur++; - - if (*cur == '.') { - cur++; - - while (PUGI__IS_CHARTYPEX(*cur, ctx_digit)) - cur++; - } - - _cur_lexeme_contents.end = cur; - - _cur_lexeme = lex_number; - } else if (PUGI__IS_CHARTYPEX(*cur, ctx_start_symbol)) { - _cur_lexeme_contents.begin = cur; - - while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) - cur++; - - if (cur[0] == ':') { - if (cur[1] == '*') // namespace test ncname:* - { - cur += 2; // :* - } else if (PUGI__IS_CHARTYPEX(cur[1], - ctx_symbol)) // namespace test qname - { - cur++; // : - - while (PUGI__IS_CHARTYPEX(*cur, ctx_symbol)) - cur++; - } - } - - _cur_lexeme_contents.end = cur; - - _cur_lexeme = lex_string; - } else { - _cur_lexeme = lex_none; - } - } - - _cur = cur; - } - - lexeme_t current() const { return _cur_lexeme; } - - const char_t *current_pos() const { return _cur_lexeme_pos; } - - const xpath_lexer_string &contents() const { - assert(_cur_lexeme == lex_var_ref || _cur_lexeme == lex_number || - _cur_lexeme == lex_string || _cur_lexeme == lex_quoted_string); - - return _cur_lexeme_contents; - } -}; - -enum ast_type_t { - ast_unknown, - ast_op_or, // left or right - ast_op_and, // left and right - ast_op_equal, // left = right - ast_op_not_equal, // left != right - ast_op_less, // left < right - ast_op_greater, // left > right - ast_op_less_or_equal, // left <= right - ast_op_greater_or_equal, // left >= right - ast_op_add, // left + right - ast_op_subtract, // left - right - ast_op_multiply, // left * right - ast_op_divide, // left / right - ast_op_mod, // left % right - ast_op_negate, // left - right - ast_op_union, // left | right - ast_predicate, // apply predicate to set; next points to next predicate - ast_filter, // select * from left where right - ast_string_constant, // string constant - ast_number_constant, // number constant - ast_variable, // variable - ast_func_last, // last() - ast_func_position, // position() - ast_func_count, // count(left) - ast_func_id, // id(left) - ast_func_local_name_0, // local-name() - ast_func_local_name_1, // local-name(left) - ast_func_namespace_uri_0, // namespace-uri() - ast_func_namespace_uri_1, // namespace-uri(left) - ast_func_name_0, // name() - ast_func_name_1, // name(left) - ast_func_string_0, // string() - ast_func_string_1, // string(left) - ast_func_concat, // concat(left, right, siblings) - ast_func_starts_with, // starts_with(left, right) - ast_func_contains, // contains(left, right) - ast_func_substring_before, // substring-before(left, right) - ast_func_substring_after, // substring-after(left, right) - ast_func_substring_2, // substring(left, right) - ast_func_substring_3, // substring(left, right, third) - ast_func_string_length_0, // string-length() - ast_func_string_length_1, // string-length(left) - ast_func_normalize_space_0, // normalize-space() - ast_func_normalize_space_1, // normalize-space(left) - ast_func_translate, // translate(left, right, third) - ast_func_boolean, // boolean(left) - ast_func_not, // not(left) - ast_func_true, // true() - ast_func_false, // false() - ast_func_lang, // lang(left) - ast_func_number_0, // number() - ast_func_number_1, // number(left) - ast_func_sum, // sum(left) - ast_func_floor, // floor(left) - ast_func_ceiling, // ceiling(left) - ast_func_round, // round(left) - ast_step, // process set left with step - ast_step_root, // select root node - - ast_opt_translate_table, // translate(left, right, third) where right/third - // are constants - ast_opt_compare_attribute // @name = 'string' -}; - -enum axis_t { - axis_ancestor, - axis_ancestor_or_self, - axis_attribute, - axis_child, - axis_descendant, - axis_descendant_or_self, - axis_following, - axis_following_sibling, - axis_namespace, - axis_parent, - axis_preceding, - axis_preceding_sibling, - axis_self -}; - -enum nodetest_t { - nodetest_none, - nodetest_name, - nodetest_type_node, - nodetest_type_comment, - nodetest_type_pi, - nodetest_type_text, - nodetest_pi, - nodetest_all, - nodetest_all_in_namespace -}; - -enum predicate_t { - predicate_default, - predicate_posinv, - predicate_constant, - predicate_constant_one -}; - -enum nodeset_eval_t { nodeset_eval_all, nodeset_eval_any, nodeset_eval_first }; - -template struct axis_to_type { static const axis_t axis; }; - -template const axis_t axis_to_type::axis = N; - -class xpath_ast_node { -private: - // node type - char _type; - char _rettype; - - // for ast_step - char _axis; - - // for ast_step/ast_predicate/ast_filter - char _test; - - // tree node structure - xpath_ast_node *_left; - xpath_ast_node *_right; - xpath_ast_node *_next; - - union { - // value for ast_string_constant - const char_t *string; - // value for ast_number_constant - double number; - // variable for ast_variable - xpath_variable *variable; - // node test for ast_step (node name/namespace/node type/pi target) - const char_t *nodetest; - // table for ast_opt_translate_table - const unsigned char *table; - } _data; - - xpath_ast_node(const xpath_ast_node &); - xpath_ast_node &operator=(const xpath_ast_node &); - - template - static bool compare_eq(xpath_ast_node *lhs, xpath_ast_node *rhs, - const xpath_context &c, const xpath_stack &stack, - const Comp &comp) { - xpath_value_type lt = lhs->rettype(), rt = rhs->rettype(); - - if (lt != xpath_type_node_set && rt != xpath_type_node_set) { - if (lt == xpath_type_boolean || rt == xpath_type_boolean) - return comp(lhs->eval_boolean(c, stack), rhs->eval_boolean(c, stack)); - else if (lt == xpath_type_number || rt == xpath_type_number) - return comp(lhs->eval_number(c, stack), rhs->eval_number(c, stack)); - else if (lt == xpath_type_string || rt == xpath_type_string) { - xpath_allocator_capture cr(stack.result); - - xpath_string ls = lhs->eval_string(c, stack); - xpath_string rs = rhs->eval_string(c, stack); - - return comp(ls, rs); - } - } else if (lt == xpath_type_node_set && rt == xpath_type_node_set) { - xpath_allocator_capture cr(stack.result); - - xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all); - xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); - - for (const xpath_node *li = ls.begin(); li != ls.end(); ++li) - for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { - xpath_allocator_capture cri(stack.result); - - if (comp(string_value(*li, stack.result), - string_value(*ri, stack.result))) - return true; - } - - return false; - } else { - if (lt == xpath_type_node_set) { - swap(lhs, rhs); - swap(lt, rt); - } - - if (lt == xpath_type_boolean) - return comp(lhs->eval_boolean(c, stack), rhs->eval_boolean(c, stack)); - else if (lt == xpath_type_number) { - xpath_allocator_capture cr(stack.result); - - double l = lhs->eval_number(c, stack); - xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); - - for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { - xpath_allocator_capture cri(stack.result); - - if (comp(l, convert_string_to_number( - string_value(*ri, stack.result).c_str()))) - return true; - } - - return false; - } else if (lt == xpath_type_string) { - xpath_allocator_capture cr(stack.result); - - xpath_string l = lhs->eval_string(c, stack); - xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); - - for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { - xpath_allocator_capture cri(stack.result); - - if (comp(l, string_value(*ri, stack.result))) - return true; - } - - return false; - } - } - - assert(!"Wrong types"); - return false; - } - - static bool eval_once(xpath_node_set::type_t type, nodeset_eval_t eval) { - return type == xpath_node_set::type_sorted ? eval != nodeset_eval_all - : eval == nodeset_eval_any; - } - - template - static bool compare_rel(xpath_ast_node *lhs, xpath_ast_node *rhs, - const xpath_context &c, const xpath_stack &stack, - const Comp &comp) { - xpath_value_type lt = lhs->rettype(), rt = rhs->rettype(); - - if (lt != xpath_type_node_set && rt != xpath_type_node_set) - return comp(lhs->eval_number(c, stack), rhs->eval_number(c, stack)); - else if (lt == xpath_type_node_set && rt == xpath_type_node_set) { - xpath_allocator_capture cr(stack.result); - - xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all); - xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); - - for (const xpath_node *li = ls.begin(); li != ls.end(); ++li) { - xpath_allocator_capture cri(stack.result); - - double l = - convert_string_to_number(string_value(*li, stack.result).c_str()); - - for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { - xpath_allocator_capture crii(stack.result); - - if (comp(l, convert_string_to_number( - string_value(*ri, stack.result).c_str()))) - return true; - } - } - - return false; - } else if (lt != xpath_type_node_set && rt == xpath_type_node_set) { - xpath_allocator_capture cr(stack.result); - - double l = lhs->eval_number(c, stack); - xpath_node_set_raw rs = rhs->eval_node_set(c, stack, nodeset_eval_all); - - for (const xpath_node *ri = rs.begin(); ri != rs.end(); ++ri) { - xpath_allocator_capture cri(stack.result); - - if (comp(l, convert_string_to_number( - string_value(*ri, stack.result).c_str()))) - return true; - } - - return false; - } else if (lt == xpath_type_node_set && rt != xpath_type_node_set) { - xpath_allocator_capture cr(stack.result); - - xpath_node_set_raw ls = lhs->eval_node_set(c, stack, nodeset_eval_all); - double r = rhs->eval_number(c, stack); - - for (const xpath_node *li = ls.begin(); li != ls.end(); ++li) { - xpath_allocator_capture cri(stack.result); - - if (comp(convert_string_to_number( - string_value(*li, stack.result).c_str()), - r)) - return true; - } - - return false; - } else { - assert(!"Wrong types"); - return false; - } - } - - static void apply_predicate_boolean(xpath_node_set_raw &ns, size_t first, - xpath_ast_node *expr, - const xpath_stack &stack, bool once) { - assert(ns.size() >= first); - assert(expr->rettype() != xpath_type_number); - - size_t i = 1; - size_t size = ns.size() - first; - - xpath_node *last = ns.begin() + first; - - // remove_if... or well, sort of - for (xpath_node *it = last; it != ns.end(); ++it, ++i) { - xpath_context c(*it, i, size); - - if (expr->eval_boolean(c, stack)) { - *last++ = *it; - - if (once) - break; - } - } - - ns.truncate(last); - } - - static void apply_predicate_number(xpath_node_set_raw &ns, size_t first, - xpath_ast_node *expr, - const xpath_stack &stack, bool once) { - assert(ns.size() >= first); - assert(expr->rettype() == xpath_type_number); - - size_t i = 1; - size_t size = ns.size() - first; - - xpath_node *last = ns.begin() + first; - - // remove_if... or well, sort of - for (xpath_node *it = last; it != ns.end(); ++it, ++i) { - xpath_context c(*it, i, size); - - if (expr->eval_number(c, stack) == i) { - *last++ = *it; - - if (once) - break; - } - } - - ns.truncate(last); - } - - static void apply_predicate_number_const(xpath_node_set_raw &ns, size_t first, - xpath_ast_node *expr, - const xpath_stack &stack) { - assert(ns.size() >= first); - assert(expr->rettype() == xpath_type_number); - - size_t size = ns.size() - first; - - xpath_node *last = ns.begin() + first; - - xpath_context c(xpath_node(), 1, size); - - double er = expr->eval_number(c, stack); - - if (er >= 1.0 && er <= size) { - size_t eri = static_cast(er); - - if (er == eri) { - xpath_node r = last[eri - 1]; - - *last++ = r; - } - } - - ns.truncate(last); - } - - void apply_predicate(xpath_node_set_raw &ns, size_t first, - const xpath_stack &stack, bool once) { - if (ns.size() == first) - return; - - assert(_type == ast_filter || _type == ast_predicate); - - if (_test == predicate_constant || _test == predicate_constant_one) - apply_predicate_number_const(ns, first, _right, stack); - else if (_right->rettype() == xpath_type_number) - apply_predicate_number(ns, first, _right, stack, once); - else - apply_predicate_boolean(ns, first, _right, stack, once); - } - - void apply_predicates(xpath_node_set_raw &ns, size_t first, - const xpath_stack &stack, nodeset_eval_t eval) { - if (ns.size() == first) - return; - - bool last_once = eval_once(ns.type(), eval); - - for (xpath_ast_node *pred = _right; pred; pred = pred->_next) - pred->apply_predicate(ns, first, stack, !pred->_next && last_once); - } - - bool step_push(xpath_node_set_raw &ns, xml_attribute_struct *a, - xml_node_struct *parent, xpath_allocator *alloc) { - assert(a); - - const char_t *name = a->name ? a->name + 0 : PUGIXML_TEXT(""); - - switch (_test) { - case nodetest_name: - if (strequal(name, _data.nodetest) && is_xpath_attribute(name)) { - ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc); - return true; - } - break; - - case nodetest_type_node: - case nodetest_all: - if (is_xpath_attribute(name)) { - ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc); - return true; - } - break; - - case nodetest_all_in_namespace: - if (starts_with(name, _data.nodetest) && is_xpath_attribute(name)) { - ns.push_back(xpath_node(xml_attribute(a), xml_node(parent)), alloc); - return true; - } - break; - - default:; - } - - return false; - } - - bool step_push(xpath_node_set_raw &ns, xml_node_struct *n, - xpath_allocator *alloc) { - assert(n); - - xml_node_type type = PUGI__NODETYPE(n); - - switch (_test) { - case nodetest_name: - if (type == node_element && n->name && - strequal(n->name, _data.nodetest)) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - case nodetest_type_node: - ns.push_back(xml_node(n), alloc); - return true; - - case nodetest_type_comment: - if (type == node_comment) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - case nodetest_type_text: - if (type == node_pcdata || type == node_cdata) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - case nodetest_type_pi: - if (type == node_pi) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - case nodetest_pi: - if (type == node_pi && n->name && strequal(n->name, _data.nodetest)) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - case nodetest_all: - if (type == node_element) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - case nodetest_all_in_namespace: - if (type == node_element && n->name && - starts_with(n->name, _data.nodetest)) { - ns.push_back(xml_node(n), alloc); - return true; - } - break; - - default: - assert(!"Unknown axis"); - } - - return false; - } - - template - void step_fill(xpath_node_set_raw &ns, xml_node_struct *n, - xpath_allocator *alloc, bool once, T) { - const axis_t axis = T::axis; - - switch (axis) { - case axis_attribute: { - for (xml_attribute_struct *a = n->first_attribute; a; - a = a->next_attribute) - if (step_push(ns, a, n, alloc) & once) - return; - - break; - } - - case axis_child: { - for (xml_node_struct *c = n->first_child; c; c = c->next_sibling) - if (step_push(ns, c, alloc) & once) - return; - - break; - } - - case axis_descendant: - case axis_descendant_or_self: { - if (axis == axis_descendant_or_self) - if (step_push(ns, n, alloc) & once) - return; - - xml_node_struct *cur = n->first_child; - - while (cur) { - if (step_push(ns, cur, alloc) & once) - return; - - if (cur->first_child) - cur = cur->first_child; - else { - while (!cur->next_sibling) { - cur = cur->parent; - - if (cur == n) - return; - } - - cur = cur->next_sibling; - } - } - - break; - } - - case axis_following_sibling: { - for (xml_node_struct *c = n->next_sibling; c; c = c->next_sibling) - if (step_push(ns, c, alloc) & once) - return; - - break; - } - - case axis_preceding_sibling: { - for (xml_node_struct *c = n->prev_sibling_c; c->next_sibling; - c = c->prev_sibling_c) - if (step_push(ns, c, alloc) & once) - return; - - break; - } - - case axis_following: { - xml_node_struct *cur = n; - - // exit from this node so that we don't include descendants - while (!cur->next_sibling) { - cur = cur->parent; - - if (!cur) - return; - } - - cur = cur->next_sibling; - - while (cur) { - if (step_push(ns, cur, alloc) & once) - return; - - if (cur->first_child) - cur = cur->first_child; - else { - while (!cur->next_sibling) { - cur = cur->parent; - - if (!cur) - return; - } - - cur = cur->next_sibling; - } - } - - break; - } - - case axis_preceding: { - xml_node_struct *cur = n; - - // exit from this node so that we don't include descendants - while (!cur->prev_sibling_c->next_sibling) { - cur = cur->parent; - - if (!cur) - return; - } - - cur = cur->prev_sibling_c; - - while (cur) { - if (cur->first_child) - cur = cur->first_child->prev_sibling_c; - else { - // leaf node, can't be ancestor - if (step_push(ns, cur, alloc) & once) - return; - - while (!cur->prev_sibling_c->next_sibling) { - cur = cur->parent; - - if (!cur) - return; - - if (!node_is_ancestor(cur, n)) - if (step_push(ns, cur, alloc) & once) - return; - } - - cur = cur->prev_sibling_c; - } - } - - break; - } - - case axis_ancestor: - case axis_ancestor_or_self: { - if (axis == axis_ancestor_or_self) - if (step_push(ns, n, alloc) & once) - return; - - xml_node_struct *cur = n->parent; - - while (cur) { - if (step_push(ns, cur, alloc) & once) - return; - - cur = cur->parent; - } - - break; - } - - case axis_self: { - step_push(ns, n, alloc); - - break; - } - - case axis_parent: { - if (n->parent) - step_push(ns, n->parent, alloc); - - break; - } - - default: - assert(!"Unimplemented axis"); - } - } - - template - void step_fill(xpath_node_set_raw &ns, xml_attribute_struct *a, - xml_node_struct *p, xpath_allocator *alloc, bool once, T v) { - const axis_t axis = T::axis; - - switch (axis) { - case axis_ancestor: - case axis_ancestor_or_self: { - if (axis == axis_ancestor_or_self && - _test == nodetest_type_node) // reject attributes based on principal - // node type test - if (step_push(ns, a, p, alloc) & once) - return; - - xml_node_struct *cur = p; - - while (cur) { - if (step_push(ns, cur, alloc) & once) - return; - - cur = cur->parent; - } - - break; - } - - case axis_descendant_or_self: - case axis_self: { - if (_test == nodetest_type_node) // reject attributes based on principal - // node type test - step_push(ns, a, p, alloc); - - break; - } - - case axis_following: { - xml_node_struct *cur = p; - - while (cur) { - if (cur->first_child) - cur = cur->first_child; - else { - while (!cur->next_sibling) { - cur = cur->parent; - - if (!cur) - return; - } - - cur = cur->next_sibling; - } - - if (step_push(ns, cur, alloc) & once) - return; - } - - break; - } - - case axis_parent: { - step_push(ns, p, alloc); - - break; - } - - case axis_preceding: { - // preceding:: axis does not include attribute nodes and attribute - // ancestors (they are the same as parent's ancestors), so we can reuse - // node preceding - step_fill(ns, p, alloc, once, v); - break; - } - - default: - assert(!"Unimplemented axis"); - } - } - - template - void step_fill(xpath_node_set_raw &ns, const xpath_node &xn, - xpath_allocator *alloc, bool once, T v) { - const axis_t axis = T::axis; - const bool axis_has_attributes = - (axis == axis_ancestor || axis == axis_ancestor_or_self || - axis == axis_descendant_or_self || axis == axis_following || - axis == axis_parent || axis == axis_preceding || axis == axis_self); - - if (xn.node()) - step_fill(ns, xn.node().internal_object(), alloc, once, v); - else if (axis_has_attributes && xn.attribute() && xn.parent()) - step_fill(ns, xn.attribute().internal_object(), - xn.parent().internal_object(), alloc, once, v); - } - - template - xpath_node_set_raw step_do(const xpath_context &c, const xpath_stack &stack, - nodeset_eval_t eval, T v) { - const axis_t axis = T::axis; - const bool axis_reverse = - (axis == axis_ancestor || axis == axis_ancestor_or_self || - axis == axis_preceding || axis == axis_preceding_sibling); - const xpath_node_set::type_t axis_type = - axis_reverse ? xpath_node_set::type_sorted_reverse - : xpath_node_set::type_sorted; - - bool once = - (axis == axis_attribute && _test == nodetest_name) || - (!_right && eval_once(axis_type, eval)) || - (_right && !_right->_next && _right->_test == predicate_constant_one); - - xpath_node_set_raw ns; - ns.set_type(axis_type); - - if (_left) { - xpath_node_set_raw s = _left->eval_node_set(c, stack, nodeset_eval_all); - - // self axis preserves the original order - if (axis == axis_self) - ns.set_type(s.type()); - - for (const xpath_node *it = s.begin(); it != s.end(); ++it) { - size_t size = ns.size(); - - // in general, all axes generate elements in a particular order, but - // there is no order guarantee if axis is applied to two nodes - if (axis != axis_self && size != 0) - ns.set_type(xpath_node_set::type_unsorted); - - step_fill(ns, *it, stack.result, once, v); - if (_right) - apply_predicates(ns, size, stack, eval); - } - } else { - step_fill(ns, c.n, stack.result, once, v); - if (_right) - apply_predicates(ns, 0, stack, eval); - } - - // child, attribute and self axes always generate unique set of nodes - // for other axis, if the set stayed sorted, it stayed unique because the - // traversal algorithms do not visit the same node twice - if (axis != axis_child && axis != axis_attribute && axis != axis_self && - ns.type() == xpath_node_set::type_unsorted) - ns.remove_duplicates(); - - return ns; - } - -public: - xpath_ast_node(ast_type_t type, xpath_value_type rettype_, - const char_t *value) - : _type(static_cast(type)), _rettype(static_cast(rettype_)), - _axis(0), _test(0), _left(0), _right(0), _next(0) { - assert(type == ast_string_constant); - _data.string = value; - } - - xpath_ast_node(ast_type_t type, xpath_value_type rettype_, double value) - : _type(static_cast(type)), _rettype(static_cast(rettype_)), - _axis(0), _test(0), _left(0), _right(0), _next(0) { - assert(type == ast_number_constant); - _data.number = value; - } - - xpath_ast_node(ast_type_t type, xpath_value_type rettype_, - xpath_variable *value) - : _type(static_cast(type)), _rettype(static_cast(rettype_)), - _axis(0), _test(0), _left(0), _right(0), _next(0) { - assert(type == ast_variable); - _data.variable = value; - } - - xpath_ast_node(ast_type_t type, xpath_value_type rettype_, - xpath_ast_node *left = 0, xpath_ast_node *right = 0) - : _type(static_cast(type)), _rettype(static_cast(rettype_)), - _axis(0), _test(0), _left(left), _right(right), _next(0) {} - - xpath_ast_node(ast_type_t type, xpath_ast_node *left, axis_t axis, - nodetest_t test, const char_t *contents) - : _type(static_cast(type)), _rettype(xpath_type_node_set), - _axis(static_cast(axis)), _test(static_cast(test)), - _left(left), _right(0), _next(0) { - assert(type == ast_step); - _data.nodetest = contents; - } - - xpath_ast_node(ast_type_t type, xpath_ast_node *left, xpath_ast_node *right, - predicate_t test) - : _type(static_cast(type)), _rettype(xpath_type_node_set), _axis(0), - _test(static_cast(test)), _left(left), _right(right), _next(0) { - assert(type == ast_filter || type == ast_predicate); - } - - void set_next(xpath_ast_node *value) { _next = value; } - - void set_right(xpath_ast_node *value) { _right = value; } - - bool eval_boolean(const xpath_context &c, const xpath_stack &stack) { - switch (_type) { - case ast_op_or: - return _left->eval_boolean(c, stack) || _right->eval_boolean(c, stack); - - case ast_op_and: - return _left->eval_boolean(c, stack) && _right->eval_boolean(c, stack); - - case ast_op_equal: - return compare_eq(_left, _right, c, stack, equal_to()); - - case ast_op_not_equal: - return compare_eq(_left, _right, c, stack, not_equal_to()); - - case ast_op_less: - return compare_rel(_left, _right, c, stack, less()); - - case ast_op_greater: - return compare_rel(_right, _left, c, stack, less()); - - case ast_op_less_or_equal: - return compare_rel(_left, _right, c, stack, less_equal()); - - case ast_op_greater_or_equal: - return compare_rel(_right, _left, c, stack, less_equal()); - - case ast_func_starts_with: { - xpath_allocator_capture cr(stack.result); - - xpath_string lr = _left->eval_string(c, stack); - xpath_string rr = _right->eval_string(c, stack); - - return starts_with(lr.c_str(), rr.c_str()); - } - - case ast_func_contains: { - xpath_allocator_capture cr(stack.result); - - xpath_string lr = _left->eval_string(c, stack); - xpath_string rr = _right->eval_string(c, stack); - - return find_substring(lr.c_str(), rr.c_str()) != 0; - } - - case ast_func_boolean: - return _left->eval_boolean(c, stack); - - case ast_func_not: - return !_left->eval_boolean(c, stack); - - case ast_func_true: - return true; - - case ast_func_false: - return false; - - case ast_func_lang: { - if (c.n.attribute()) - return false; - - xpath_allocator_capture cr(stack.result); - - xpath_string lang = _left->eval_string(c, stack); - - for (xml_node n = c.n.node(); n; n = n.parent()) { - xml_attribute a = n.attribute(PUGIXML_TEXT("xml:lang")); - - if (a) { - const char_t *value = a.value(); - - // strnicmp / strncasecmp is not portable - for (const char_t *lit = lang.c_str(); *lit; ++lit) { - if (tolower_ascii(*lit) != tolower_ascii(*value)) - return false; - ++value; - } - - return *value == 0 || *value == '-'; - } - } - - return false; - } - - case ast_opt_compare_attribute: { - const char_t *value = (_right->_type == ast_string_constant) - ? _right->_data.string - : _right->_data.variable->get_string(); - - xml_attribute attr = c.n.node().attribute(_left->_data.nodetest); - - return attr && strequal(attr.value(), value) && - is_xpath_attribute(attr.name()); - } - - case ast_variable: { - assert(_rettype == _data.variable->type()); - - if (_rettype == xpath_type_boolean) - return _data.variable->get_boolean(); - - // fallthrough to type conversion - } - - default: { - switch (_rettype) { - case xpath_type_number: - return convert_number_to_boolean(eval_number(c, stack)); - - case xpath_type_string: { - xpath_allocator_capture cr(stack.result); - - return !eval_string(c, stack).empty(); - } - - case xpath_type_node_set: { - xpath_allocator_capture cr(stack.result); - - return !eval_node_set(c, stack, nodeset_eval_any).empty(); - } - - default: - assert(!"Wrong expression for return type boolean"); - return false; - } - } - } - } - - double eval_number(const xpath_context &c, const xpath_stack &stack) { - switch (_type) { - case ast_op_add: - return _left->eval_number(c, stack) + _right->eval_number(c, stack); - - case ast_op_subtract: - return _left->eval_number(c, stack) - _right->eval_number(c, stack); - - case ast_op_multiply: - return _left->eval_number(c, stack) * _right->eval_number(c, stack); - - case ast_op_divide: - return _left->eval_number(c, stack) / _right->eval_number(c, stack); - - case ast_op_mod: - return fmod(_left->eval_number(c, stack), _right->eval_number(c, stack)); - - case ast_op_negate: - return -_left->eval_number(c, stack); - - case ast_number_constant: - return _data.number; - - case ast_func_last: - return static_cast(c.size); - - case ast_func_position: - return static_cast(c.position); - - case ast_func_count: { - xpath_allocator_capture cr(stack.result); - - return static_cast( - _left->eval_node_set(c, stack, nodeset_eval_all).size()); - } - - case ast_func_string_length_0: { - xpath_allocator_capture cr(stack.result); - - return static_cast(string_value(c.n, stack.result).length()); - } - - case ast_func_string_length_1: { - xpath_allocator_capture cr(stack.result); - - return static_cast(_left->eval_string(c, stack).length()); - } - - case ast_func_number_0: { - xpath_allocator_capture cr(stack.result); - - return convert_string_to_number(string_value(c.n, stack.result).c_str()); - } - - case ast_func_number_1: - return _left->eval_number(c, stack); - - case ast_func_sum: { - xpath_allocator_capture cr(stack.result); - - double r = 0; - - xpath_node_set_raw ns = _left->eval_node_set(c, stack, nodeset_eval_all); - - for (const xpath_node *it = ns.begin(); it != ns.end(); ++it) { - xpath_allocator_capture cri(stack.result); - - r += convert_string_to_number(string_value(*it, stack.result).c_str()); - } - - return r; - } - - case ast_func_floor: { - double r = _left->eval_number(c, stack); - - return r == r ? floor(r) : r; - } - - case ast_func_ceiling: { - double r = _left->eval_number(c, stack); - - return r == r ? ceil(r) : r; - } - - case ast_func_round: - return round_nearest_nzero(_left->eval_number(c, stack)); - - case ast_variable: { - assert(_rettype == _data.variable->type()); - - if (_rettype == xpath_type_number) - return _data.variable->get_number(); - - // fallthrough to type conversion - } - - default: { - switch (_rettype) { - case xpath_type_boolean: - return eval_boolean(c, stack) ? 1 : 0; - - case xpath_type_string: { - xpath_allocator_capture cr(stack.result); - - return convert_string_to_number(eval_string(c, stack).c_str()); - } - - case xpath_type_node_set: { - xpath_allocator_capture cr(stack.result); - - return convert_string_to_number(eval_string(c, stack).c_str()); - } - - default: - assert(!"Wrong expression for return type number"); - return 0; - } - } - } - } - - xpath_string eval_string_concat(const xpath_context &c, - const xpath_stack &stack) { - assert(_type == ast_func_concat); - - xpath_allocator_capture ct(stack.temp); - - // count the string number - size_t count = 1; - for (xpath_ast_node *nc = _right; nc; nc = nc->_next) - count++; - - // gather all strings - xpath_string static_buffer[4]; - xpath_string *buffer = static_buffer; - - // allocate on-heap for large concats - if (count > sizeof(static_buffer) / sizeof(static_buffer[0])) { - buffer = static_cast( - stack.temp->allocate(count * sizeof(xpath_string))); - assert(buffer); - } - - // evaluate all strings to temporary stack - xpath_stack swapped_stack = {stack.temp, stack.result}; - - buffer[0] = _left->eval_string(c, swapped_stack); - - size_t pos = 1; - for (xpath_ast_node *n = _right; n; n = n->_next, ++pos) - buffer[pos] = n->eval_string(c, swapped_stack); - assert(pos == count); - - // get total length - size_t length = 0; - for (size_t i = 0; i < count; ++i) - length += buffer[i].length(); - - // create final string - char_t *result = static_cast( - stack.result->allocate((length + 1) * sizeof(char_t))); - assert(result); - - char_t *ri = result; - - for (size_t j = 0; j < count; ++j) - for (const char_t *bi = buffer[j].c_str(); *bi; ++bi) - *ri++ = *bi; - - *ri = 0; - - return xpath_string::from_heap_preallocated(result, ri); - } - - xpath_string eval_string(const xpath_context &c, const xpath_stack &stack) { - switch (_type) { - case ast_string_constant: - return xpath_string::from_const(_data.string); - - case ast_func_local_name_0: { - xpath_node na = c.n; - - return xpath_string::from_const(local_name(na)); - } - - case ast_func_local_name_1: { - xpath_allocator_capture cr(stack.result); - - xpath_node_set_raw ns = - _left->eval_node_set(c, stack, nodeset_eval_first); - xpath_node na = ns.first(); - - return xpath_string::from_const(local_name(na)); - } - - case ast_func_name_0: { - xpath_node na = c.n; - - return xpath_string::from_const(qualified_name(na)); - } - - case ast_func_name_1: { - xpath_allocator_capture cr(stack.result); - - xpath_node_set_raw ns = - _left->eval_node_set(c, stack, nodeset_eval_first); - xpath_node na = ns.first(); - - return xpath_string::from_const(qualified_name(na)); - } - - case ast_func_namespace_uri_0: { - xpath_node na = c.n; - - return xpath_string::from_const(namespace_uri(na)); - } - - case ast_func_namespace_uri_1: { - xpath_allocator_capture cr(stack.result); - - xpath_node_set_raw ns = - _left->eval_node_set(c, stack, nodeset_eval_first); - xpath_node na = ns.first(); - - return xpath_string::from_const(namespace_uri(na)); - } - - case ast_func_string_0: - return string_value(c.n, stack.result); - - case ast_func_string_1: - return _left->eval_string(c, stack); - - case ast_func_concat: - return eval_string_concat(c, stack); - - case ast_func_substring_before: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_string s = _left->eval_string(c, swapped_stack); - xpath_string p = _right->eval_string(c, swapped_stack); - - const char_t *pos = find_substring(s.c_str(), p.c_str()); - - return pos ? xpath_string::from_heap(s.c_str(), pos, stack.result) - : xpath_string(); - } - - case ast_func_substring_after: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_string s = _left->eval_string(c, swapped_stack); - xpath_string p = _right->eval_string(c, swapped_stack); - - const char_t *pos = find_substring(s.c_str(), p.c_str()); - if (!pos) - return xpath_string(); - - const char_t *rbegin = pos + p.length(); - const char_t *rend = s.c_str() + s.length(); - - return s.uses_heap() ? xpath_string::from_heap(rbegin, rend, stack.result) - : xpath_string::from_const(rbegin); - } - - case ast_func_substring_2: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_string s = _left->eval_string(c, swapped_stack); - size_t s_length = s.length(); - - double first = round_nearest(_right->eval_number(c, stack)); - - if (is_nan(first)) - return xpath_string(); // NaN - else if (first >= s_length + 1) - return xpath_string(); - - size_t pos = first < 1 ? 1 : static_cast(first); - assert(1 <= pos && pos <= s_length + 1); - - const char_t *rbegin = s.c_str() + (pos - 1); - const char_t *rend = s.c_str() + s.length(); - - return s.uses_heap() ? xpath_string::from_heap(rbegin, rend, stack.result) - : xpath_string::from_const(rbegin); - } - - case ast_func_substring_3: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_string s = _left->eval_string(c, swapped_stack); - size_t s_length = s.length(); - - double first = round_nearest(_right->eval_number(c, stack)); - double last = first + round_nearest(_right->_next->eval_number(c, stack)); - - if (is_nan(first) || is_nan(last)) - return xpath_string(); - else if (first >= s_length + 1) - return xpath_string(); - else if (first >= last) - return xpath_string(); - else if (last < 1) - return xpath_string(); - - size_t pos = first < 1 ? 1 : static_cast(first); - size_t end = - last >= s_length + 1 ? s_length + 1 : static_cast(last); - - assert(1 <= pos && pos <= end && end <= s_length + 1); - const char_t *rbegin = s.c_str() + (pos - 1); - const char_t *rend = s.c_str() + (end - 1); - - return (end == s_length + 1 && !s.uses_heap()) - ? xpath_string::from_const(rbegin) - : xpath_string::from_heap(rbegin, rend, stack.result); - } - - case ast_func_normalize_space_0: { - xpath_string s = string_value(c.n, stack.result); - - char_t *begin = s.data(stack.result); - char_t *end = normalize_space(begin); - - return xpath_string::from_heap_preallocated(begin, end); - } - - case ast_func_normalize_space_1: { - xpath_string s = _left->eval_string(c, stack); - - char_t *begin = s.data(stack.result); - char_t *end = normalize_space(begin); - - return xpath_string::from_heap_preallocated(begin, end); - } - - case ast_func_translate: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_string s = _left->eval_string(c, stack); - xpath_string from = _right->eval_string(c, swapped_stack); - xpath_string to = _right->_next->eval_string(c, swapped_stack); - - char_t *begin = s.data(stack.result); - char_t *end = translate(begin, from.c_str(), to.c_str(), to.length()); - - return xpath_string::from_heap_preallocated(begin, end); - } - - case ast_opt_translate_table: { - xpath_string s = _left->eval_string(c, stack); - - char_t *begin = s.data(stack.result); - char_t *end = translate_table(begin, _data.table); - - return xpath_string::from_heap_preallocated(begin, end); - } - - case ast_variable: { - assert(_rettype == _data.variable->type()); - - if (_rettype == xpath_type_string) - return xpath_string::from_const(_data.variable->get_string()); - - // fallthrough to type conversion - } - - default: { - switch (_rettype) { - case xpath_type_boolean: - return xpath_string::from_const(eval_boolean(c, stack) - ? PUGIXML_TEXT("true") - : PUGIXML_TEXT("false")); - - case xpath_type_number: - return convert_number_to_string(eval_number(c, stack), stack.result); - - case xpath_type_node_set: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_node_set_raw ns = - eval_node_set(c, swapped_stack, nodeset_eval_first); - return ns.empty() ? xpath_string() - : string_value(ns.first(), stack.result); - } - - default: - assert(!"Wrong expression for return type string"); - return xpath_string(); - } - } - } - } - - xpath_node_set_raw eval_node_set(const xpath_context &c, - const xpath_stack &stack, - nodeset_eval_t eval) { - switch (_type) { - case ast_op_union: { - xpath_allocator_capture cr(stack.temp); - - xpath_stack swapped_stack = {stack.temp, stack.result}; - - xpath_node_set_raw ls = _left->eval_node_set(c, swapped_stack, eval); - xpath_node_set_raw rs = _right->eval_node_set(c, stack, eval); - - // we can optimize merging two sorted sets, but this is a very rare - // operation, so don't bother - rs.set_type(xpath_node_set::type_unsorted); - - rs.append(ls.begin(), ls.end(), stack.result); - rs.remove_duplicates(); - - return rs; - } - - case ast_filter: { - xpath_node_set_raw set = _left->eval_node_set( - c, stack, - _test == predicate_constant_one ? nodeset_eval_first - : nodeset_eval_all); - - // either expression is a number or it contains position() call; sort by - // document order - if (_test != predicate_posinv) - set.sort_do(); - - bool once = eval_once(set.type(), eval); - - apply_predicate(set, 0, stack, once); - - return set; - } - - case ast_func_id: - return xpath_node_set_raw(); - - case ast_step: { - switch (_axis) { - case axis_ancestor: - return step_do(c, stack, eval, axis_to_type()); - - case axis_ancestor_or_self: - return step_do(c, stack, eval, axis_to_type()); - - case axis_attribute: - return step_do(c, stack, eval, axis_to_type()); - - case axis_child: - return step_do(c, stack, eval, axis_to_type()); - - case axis_descendant: - return step_do(c, stack, eval, axis_to_type()); - - case axis_descendant_or_self: - return step_do(c, stack, eval, axis_to_type()); - - case axis_following: - return step_do(c, stack, eval, axis_to_type()); - - case axis_following_sibling: - return step_do(c, stack, eval, axis_to_type()); - - case axis_namespace: - // namespaced axis is not supported - return xpath_node_set_raw(); - - case axis_parent: - return step_do(c, stack, eval, axis_to_type()); - - case axis_preceding: - return step_do(c, stack, eval, axis_to_type()); - - case axis_preceding_sibling: - return step_do(c, stack, eval, axis_to_type()); - - case axis_self: - return step_do(c, stack, eval, axis_to_type()); - - default: - assert(!"Unknown axis"); - return xpath_node_set_raw(); - } - } - - case ast_step_root: { - assert(!_right); // root step can't have any predicates - - xpath_node_set_raw ns; - - ns.set_type(xpath_node_set::type_sorted); - - if (c.n.node()) - ns.push_back(c.n.node().root(), stack.result); - else if (c.n.attribute()) - ns.push_back(c.n.parent().root(), stack.result); - - return ns; - } - - case ast_variable: { - assert(_rettype == _data.variable->type()); - - if (_rettype == xpath_type_node_set) { - const xpath_node_set &s = _data.variable->get_node_set(); - - xpath_node_set_raw ns; - - ns.set_type(s.type()); - ns.append(s.begin(), s.end(), stack.result); - - return ns; - } - - // fallthrough to type conversion - } - - default: - assert(!"Wrong expression for return type node set"); - return xpath_node_set_raw(); - } - } - - void optimize(xpath_allocator *alloc) { - if (_left) - _left->optimize(alloc); - if (_right) - _right->optimize(alloc); - if (_next) - _next->optimize(alloc); - - optimize_self(alloc); - } - - void optimize_self(xpath_allocator *alloc) { - // Rewrite [position()=expr] with [expr] - // Note that this step has to go before classification to recognize - // [position()=1] - if ((_type == ast_filter || _type == ast_predicate) && - _right->_type == ast_op_equal && - _right->_left->_type == ast_func_position && - _right->_right->_rettype == xpath_type_number) { - _right = _right->_right; - } - - // Classify filter/predicate ops to perform various optimizations during - // evaluation - if (_type == ast_filter || _type == ast_predicate) { - assert(_test == predicate_default); - - if (_right->_type == ast_number_constant && _right->_data.number == 1.0) - _test = predicate_constant_one; - else if (_right->_rettype == xpath_type_number && - (_right->_type == ast_number_constant || - _right->_type == ast_variable || - _right->_type == ast_func_last)) - _test = predicate_constant; - else if (_right->_rettype != xpath_type_number && - _right->is_posinv_expr()) - _test = predicate_posinv; - } - - // Rewrite descendant-or-self::node()/child::foo with descendant::foo - // The former is a full form of //foo, the latter is much faster since it - // executes the node test immediately Do a similar kind of rewrite for - // self/descendant/descendant-or-self axes Note that we only rewrite - // positionally invariant steps (//foo[1] != /descendant::foo[1]) - if (_type == ast_step && - (_axis == axis_child || _axis == axis_self || - _axis == axis_descendant || _axis == axis_descendant_or_self) && - _left && _left->_type == ast_step && - _left->_axis == axis_descendant_or_self && - _left->_test == nodetest_type_node && !_left->_right && - is_posinv_step()) { - if (_axis == axis_child || _axis == axis_descendant) - _axis = axis_descendant; - else - _axis = axis_descendant_or_self; - - _left = _left->_left; - } - - // Use optimized lookup table implementation for translate() with constant - // arguments - if (_type == ast_func_translate && _right->_type == ast_string_constant && - _right->_next->_type == ast_string_constant) { - unsigned char *table = translate_table_generate( - alloc, _right->_data.string, _right->_next->_data.string); - - if (table) { - _type = ast_opt_translate_table; - _data.table = table; - } - } - - // Use optimized path for @attr = 'value' or @attr = $value - if (_type == ast_op_equal && _left->_type == ast_step && - _left->_axis == axis_attribute && _left->_test == nodetest_name && - !_left->_left && !_left->_right && - (_right->_type == ast_string_constant || - (_right->_type == ast_variable && - _right->_rettype == xpath_type_string))) { - _type = ast_opt_compare_attribute; - } - } - - bool is_posinv_expr() const { - switch (_type) { - case ast_func_position: - case ast_func_last: - return false; - - case ast_string_constant: - case ast_number_constant: - case ast_variable: - return true; - - case ast_step: - case ast_step_root: - return true; - - case ast_predicate: - case ast_filter: - return true; - - default: - if (_left && !_left->is_posinv_expr()) - return false; - - for (xpath_ast_node *n = _right; n; n = n->_next) - if (!n->is_posinv_expr()) - return false; - - return true; - } - } - - bool is_posinv_step() const { - assert(_type == ast_step); - - for (xpath_ast_node *n = _right; n; n = n->_next) { - assert(n->_type == ast_predicate); - - if (n->_test != predicate_posinv) - return false; - } - - return true; - } - - xpath_value_type rettype() const { - return static_cast(_rettype); - } -}; - -struct xpath_parser { - xpath_allocator *_alloc; - xpath_lexer _lexer; - - const char_t *_query; - xpath_variable_set *_variables; - - xpath_parse_result *_result; - - char_t _scratch[32]; - -#ifdef PUGIXML_NO_EXCEPTIONS - jmp_buf _error_handler; -#endif - - void throw_error(const char *message) { - _result->error = message; - _result->offset = _lexer.current_pos() - _query; - -#ifdef PUGIXML_NO_EXCEPTIONS - longjmp(_error_handler, 1); -#else - throw xpath_exception(*_result); -#endif - } - - void throw_error_oom() { -#ifdef PUGIXML_NO_EXCEPTIONS - throw_error("Out of memory"); -#else - throw std::bad_alloc(); -#endif - } - - void *alloc_node() { - void *result = _alloc->allocate_nothrow(sizeof(xpath_ast_node)); - - if (!result) - throw_error_oom(); - - return result; - } - - const char_t *alloc_string(const xpath_lexer_string &value) { - if (value.begin) { - size_t length = static_cast(value.end - value.begin); - - char_t *c = static_cast( - _alloc->allocate_nothrow((length + 1) * sizeof(char_t))); - if (!c) - throw_error_oom(); - assert(c); // workaround for clang static analysis - - memcpy(c, value.begin, length * sizeof(char_t)); - c[length] = 0; - - return c; - } else - return 0; - } - - xpath_ast_node *parse_function_helper(ast_type_t type0, ast_type_t type1, - size_t argc, xpath_ast_node *args[2]) { - assert(argc <= 1); - - if (argc == 1 && args[0]->rettype() != xpath_type_node_set) - throw_error("Function has to be applied to node set"); - - return new (alloc_node()) - xpath_ast_node(argc == 0 ? type0 : type1, xpath_type_string, args[0]); - } - - xpath_ast_node *parse_function(const xpath_lexer_string &name, size_t argc, - xpath_ast_node *args[2]) { - switch (name.begin[0]) { - case 'b': - if (name == PUGIXML_TEXT("boolean") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_boolean, xpath_type_boolean, args[0]); - - break; - - case 'c': - if (name == PUGIXML_TEXT("count") && argc == 1) { - if (args[0]->rettype() != xpath_type_node_set) - throw_error("Function has to be applied to node set"); - return new (alloc_node()) - xpath_ast_node(ast_func_count, xpath_type_number, args[0]); - } else if (name == PUGIXML_TEXT("contains") && argc == 2) - return new (alloc_node()) xpath_ast_node( - ast_func_contains, xpath_type_boolean, args[0], args[1]); - else if (name == PUGIXML_TEXT("concat") && argc >= 2) - return new (alloc_node()) xpath_ast_node( - ast_func_concat, xpath_type_string, args[0], args[1]); - else if (name == PUGIXML_TEXT("ceiling") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_ceiling, xpath_type_number, args[0]); - - break; - - case 'f': - if (name == PUGIXML_TEXT("false") && argc == 0) - return new (alloc_node()) - xpath_ast_node(ast_func_false, xpath_type_boolean); - else if (name == PUGIXML_TEXT("floor") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_floor, xpath_type_number, args[0]); - - break; - - case 'i': - if (name == PUGIXML_TEXT("id") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_id, xpath_type_node_set, args[0]); - - break; - - case 'l': - if (name == PUGIXML_TEXT("last") && argc == 0) - return new (alloc_node()) - xpath_ast_node(ast_func_last, xpath_type_number); - else if (name == PUGIXML_TEXT("lang") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_lang, xpath_type_boolean, args[0]); - else if (name == PUGIXML_TEXT("local-name") && argc <= 1) - return parse_function_helper(ast_func_local_name_0, - ast_func_local_name_1, argc, args); - - break; - - case 'n': - if (name == PUGIXML_TEXT("name") && argc <= 1) - return parse_function_helper(ast_func_name_0, ast_func_name_1, argc, - args); - else if (name == PUGIXML_TEXT("namespace-uri") && argc <= 1) - return parse_function_helper(ast_func_namespace_uri_0, - ast_func_namespace_uri_1, argc, args); - else if (name == PUGIXML_TEXT("normalize-space") && argc <= 1) - return new (alloc_node()) xpath_ast_node( - argc == 0 ? ast_func_normalize_space_0 : ast_func_normalize_space_1, - xpath_type_string, args[0], args[1]); - else if (name == PUGIXML_TEXT("not") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_not, xpath_type_boolean, args[0]); - else if (name == PUGIXML_TEXT("number") && argc <= 1) - return new (alloc_node()) - xpath_ast_node(argc == 0 ? ast_func_number_0 : ast_func_number_1, - xpath_type_number, args[0]); - - break; - - case 'p': - if (name == PUGIXML_TEXT("position") && argc == 0) - return new (alloc_node()) - xpath_ast_node(ast_func_position, xpath_type_number); - - break; - - case 'r': - if (name == PUGIXML_TEXT("round") && argc == 1) - return new (alloc_node()) - xpath_ast_node(ast_func_round, xpath_type_number, args[0]); - - break; - - case 's': - if (name == PUGIXML_TEXT("string") && argc <= 1) - return new (alloc_node()) - xpath_ast_node(argc == 0 ? ast_func_string_0 : ast_func_string_1, - xpath_type_string, args[0]); - else if (name == PUGIXML_TEXT("string-length") && argc <= 1) - return new (alloc_node()) xpath_ast_node( - argc == 0 ? ast_func_string_length_0 : ast_func_string_length_1, - xpath_type_number, args[0]); - else if (name == PUGIXML_TEXT("starts-with") && argc == 2) - return new (alloc_node()) xpath_ast_node( - ast_func_starts_with, xpath_type_boolean, args[0], args[1]); - else if (name == PUGIXML_TEXT("substring-before") && argc == 2) - return new (alloc_node()) xpath_ast_node( - ast_func_substring_before, xpath_type_string, args[0], args[1]); - else if (name == PUGIXML_TEXT("substring-after") && argc == 2) - return new (alloc_node()) xpath_ast_node( - ast_func_substring_after, xpath_type_string, args[0], args[1]); - else if (name == PUGIXML_TEXT("substring") && (argc == 2 || argc == 3)) - return new (alloc_node()) xpath_ast_node( - argc == 2 ? ast_func_substring_2 : ast_func_substring_3, - xpath_type_string, args[0], args[1]); - else if (name == PUGIXML_TEXT("sum") && argc == 1) { - if (args[0]->rettype() != xpath_type_node_set) - throw_error("Function has to be applied to node set"); - return new (alloc_node()) - xpath_ast_node(ast_func_sum, xpath_type_number, args[0]); - } - - break; - - case 't': - if (name == PUGIXML_TEXT("translate") && argc == 3) - return new (alloc_node()) xpath_ast_node( - ast_func_translate, xpath_type_string, args[0], args[1]); - else if (name == PUGIXML_TEXT("true") && argc == 0) - return new (alloc_node()) - xpath_ast_node(ast_func_true, xpath_type_boolean); - - break; - - default: - break; - } - - throw_error("Unrecognized function or wrong parameter count"); - - return 0; - } - - axis_t parse_axis_name(const xpath_lexer_string &name, bool &specified) { - specified = true; - - switch (name.begin[0]) { - case 'a': - if (name == PUGIXML_TEXT("ancestor")) - return axis_ancestor; - else if (name == PUGIXML_TEXT("ancestor-or-self")) - return axis_ancestor_or_self; - else if (name == PUGIXML_TEXT("attribute")) - return axis_attribute; - - break; - - case 'c': - if (name == PUGIXML_TEXT("child")) - return axis_child; - - break; - - case 'd': - if (name == PUGIXML_TEXT("descendant")) - return axis_descendant; - else if (name == PUGIXML_TEXT("descendant-or-self")) - return axis_descendant_or_self; - - break; - - case 'f': - if (name == PUGIXML_TEXT("following")) - return axis_following; - else if (name == PUGIXML_TEXT("following-sibling")) - return axis_following_sibling; - - break; - - case 'n': - if (name == PUGIXML_TEXT("namespace")) - return axis_namespace; - - break; - - case 'p': - if (name == PUGIXML_TEXT("parent")) - return axis_parent; - else if (name == PUGIXML_TEXT("preceding")) - return axis_preceding; - else if (name == PUGIXML_TEXT("preceding-sibling")) - return axis_preceding_sibling; - - break; - - case 's': - if (name == PUGIXML_TEXT("self")) - return axis_self; - - break; - - default: - break; - } - - specified = false; - return axis_child; - } - - nodetest_t parse_node_test_type(const xpath_lexer_string &name) { - switch (name.begin[0]) { - case 'c': - if (name == PUGIXML_TEXT("comment")) - return nodetest_type_comment; - - break; - - case 'n': - if (name == PUGIXML_TEXT("node")) - return nodetest_type_node; - - break; - - case 'p': - if (name == PUGIXML_TEXT("processing-instruction")) - return nodetest_type_pi; - - break; - - case 't': - if (name == PUGIXML_TEXT("text")) - return nodetest_type_text; - - break; - - default: - break; - } - - return nodetest_none; - } - - // PrimaryExpr ::= VariableReference | '(' Expr ')' | Literal | Number | - // FunctionCall - xpath_ast_node *parse_primary_expression() { - switch (_lexer.current()) { - case lex_var_ref: { - xpath_lexer_string name = _lexer.contents(); - - if (!_variables) - throw_error("Unknown variable: variable set is not provided"); - - xpath_variable *var = 0; - if (!get_variable_scratch(_scratch, _variables, name.begin, name.end, - &var)) - throw_error_oom(); - - if (!var) - throw_error( - "Unknown variable: variable set does not contain the given name"); - - _lexer.next(); - - return new (alloc_node()) xpath_ast_node(ast_variable, var->type(), var); - } - - case lex_open_brace: { - _lexer.next(); - - xpath_ast_node *n = parse_expression(); - - if (_lexer.current() != lex_close_brace) - throw_error("Unmatched braces"); - - _lexer.next(); - - return n; - } - - case lex_quoted_string: { - const char_t *value = alloc_string(_lexer.contents()); - - xpath_ast_node *n = new (alloc_node()) - xpath_ast_node(ast_string_constant, xpath_type_string, value); - _lexer.next(); - - return n; - } - - case lex_number: { - double value = 0; - - if (!convert_string_to_number_scratch(_scratch, _lexer.contents().begin, - _lexer.contents().end, &value)) - throw_error_oom(); - - xpath_ast_node *n = new (alloc_node()) - xpath_ast_node(ast_number_constant, xpath_type_number, value); - _lexer.next(); - - return n; - } - - case lex_string: { - xpath_ast_node *args[2] = {0}; - size_t argc = 0; - - xpath_lexer_string function = _lexer.contents(); - _lexer.next(); - - xpath_ast_node *last_arg = 0; - - if (_lexer.current() != lex_open_brace) - throw_error("Unrecognized function call"); - _lexer.next(); - - if (_lexer.current() != lex_close_brace) - args[argc++] = parse_expression(); - - while (_lexer.current() != lex_close_brace) { - if (_lexer.current() != lex_comma) - throw_error("No comma between function arguments"); - _lexer.next(); - - xpath_ast_node *n = parse_expression(); - - if (argc < 2) - args[argc] = n; - else - last_arg->set_next(n); - - argc++; - last_arg = n; - } - - _lexer.next(); - - return parse_function(function, argc, args); - } - - default: - throw_error("Unrecognizable primary expression"); - - return 0; - } - } - - // FilterExpr ::= PrimaryExpr | FilterExpr Predicate - // Predicate ::= '[' PredicateExpr ']' - // PredicateExpr ::= Expr - xpath_ast_node *parse_filter_expression() { - xpath_ast_node *n = parse_primary_expression(); - - while (_lexer.current() == lex_open_square_brace) { - _lexer.next(); - - xpath_ast_node *expr = parse_expression(); - - if (n->rettype() != xpath_type_node_set) - throw_error("Predicate has to be applied to node set"); - - n = new (alloc_node()) - xpath_ast_node(ast_filter, n, expr, predicate_default); - - if (_lexer.current() != lex_close_square_brace) - throw_error("Unmatched square brace"); - - _lexer.next(); - } - - return n; - } - - // Step ::= AxisSpecifier NodeTest Predicate* | AbbreviatedStep - // AxisSpecifier ::= AxisName '::' | '@'? - // NodeTest ::= NameTest | NodeType '(' ')' | 'processing-instruction' '(' - // Literal ')' NameTest ::= '*' | NCName ':' '*' | QName AbbreviatedStep ::= - // '.' | '..' - xpath_ast_node *parse_step(xpath_ast_node *set) { - if (set && set->rettype() != xpath_type_node_set) - throw_error("Step has to be applied to node set"); - - bool axis_specified = false; - axis_t axis = axis_child; // implied child axis - - if (_lexer.current() == lex_axis_attribute) { - axis = axis_attribute; - axis_specified = true; - - _lexer.next(); - } else if (_lexer.current() == lex_dot) { - _lexer.next(); - - return new (alloc_node()) - xpath_ast_node(ast_step, set, axis_self, nodetest_type_node, 0); - } else if (_lexer.current() == lex_double_dot) { - _lexer.next(); - - return new (alloc_node()) - xpath_ast_node(ast_step, set, axis_parent, nodetest_type_node, 0); - } - - nodetest_t nt_type = nodetest_none; - xpath_lexer_string nt_name; - - if (_lexer.current() == lex_string) { - // node name test - nt_name = _lexer.contents(); - _lexer.next(); - - // was it an axis name? - if (_lexer.current() == lex_double_colon) { - // parse axis name - if (axis_specified) - throw_error("Two axis specifiers in one step"); - - axis = parse_axis_name(nt_name, axis_specified); - - if (!axis_specified) - throw_error("Unknown axis"); - - // read actual node test - _lexer.next(); - - if (_lexer.current() == lex_multiply) { - nt_type = nodetest_all; - nt_name = xpath_lexer_string(); - _lexer.next(); - } else if (_lexer.current() == lex_string) { - nt_name = _lexer.contents(); - _lexer.next(); - } else - throw_error("Unrecognized node test"); - } - - if (nt_type == nodetest_none) { - // node type test or processing-instruction - if (_lexer.current() == lex_open_brace) { - _lexer.next(); - - if (_lexer.current() == lex_close_brace) { - _lexer.next(); - - nt_type = parse_node_test_type(nt_name); - - if (nt_type == nodetest_none) - throw_error("Unrecognized node type"); - - nt_name = xpath_lexer_string(); - } else if (nt_name == PUGIXML_TEXT("processing-instruction")) { - if (_lexer.current() != lex_quoted_string) - throw_error("Only literals are allowed as arguments to " - "processing-instruction()"); - - nt_type = nodetest_pi; - nt_name = _lexer.contents(); - _lexer.next(); - - if (_lexer.current() != lex_close_brace) - throw_error("Unmatched brace near processing-instruction()"); - _lexer.next(); - } else - throw_error("Unmatched brace near node type test"); - - } - // QName or NCName:* - else { - if (nt_name.end - nt_name.begin > 2 && nt_name.end[-2] == ':' && - nt_name.end[-1] == '*') // NCName:* - { - nt_name.end--; // erase * - - nt_type = nodetest_all_in_namespace; - } else - nt_type = nodetest_name; - } - } - } else if (_lexer.current() == lex_multiply) { - nt_type = nodetest_all; - _lexer.next(); - } else - throw_error("Unrecognized node test"); - - xpath_ast_node *n = new (alloc_node()) - xpath_ast_node(ast_step, set, axis, nt_type, alloc_string(nt_name)); - - xpath_ast_node *last = 0; - - while (_lexer.current() == lex_open_square_brace) { - _lexer.next(); - - xpath_ast_node *expr = parse_expression(); - - xpath_ast_node *pred = new (alloc_node()) - xpath_ast_node(ast_predicate, 0, expr, predicate_default); - - if (_lexer.current() != lex_close_square_brace) - throw_error("Unmatched square brace"); - _lexer.next(); - - if (last) - last->set_next(pred); - else - n->set_right(pred); - - last = pred; - } - - return n; - } - - // RelativeLocationPath ::= Step | RelativeLocationPath '/' Step | - // RelativeLocationPath '//' Step - xpath_ast_node *parse_relative_location_path(xpath_ast_node *set) { - xpath_ast_node *n = parse_step(set); - - while (_lexer.current() == lex_slash || - _lexer.current() == lex_double_slash) { - lexeme_t l = _lexer.current(); - _lexer.next(); - - if (l == lex_double_slash) - n = new (alloc_node()) xpath_ast_node( - ast_step, n, axis_descendant_or_self, nodetest_type_node, 0); - - n = parse_step(n); - } - - return n; - } - - // LocationPath ::= RelativeLocationPath | AbsoluteLocationPath - // AbsoluteLocationPath ::= '/' RelativeLocationPath? | '//' - // RelativeLocationPath - xpath_ast_node *parse_location_path() { - if (_lexer.current() == lex_slash) { - _lexer.next(); - - xpath_ast_node *n = - new (alloc_node()) xpath_ast_node(ast_step_root, xpath_type_node_set); - - // relative location path can start from axis_attribute, dot, double_dot, - // multiply and string lexemes; any other lexeme means standalone root - // path - lexeme_t l = _lexer.current(); - - if (l == lex_string || l == lex_axis_attribute || l == lex_dot || - l == lex_double_dot || l == lex_multiply) - return parse_relative_location_path(n); - else - return n; - } else if (_lexer.current() == lex_double_slash) { - _lexer.next(); - - xpath_ast_node *n = - new (alloc_node()) xpath_ast_node(ast_step_root, xpath_type_node_set); - n = new (alloc_node()) xpath_ast_node( - ast_step, n, axis_descendant_or_self, nodetest_type_node, 0); - - return parse_relative_location_path(n); - } - - // else clause moved outside of if because of bogus warning 'control may - // reach end of non-void function being inlined' in gcc 4.0.1 - return parse_relative_location_path(0); - } - - // PathExpr ::= LocationPath - // | FilterExpr - // | FilterExpr '/' RelativeLocationPath - // | FilterExpr '//' RelativeLocationPath - // UnionExpr ::= PathExpr | UnionExpr '|' PathExpr - // UnaryExpr ::= UnionExpr | '-' UnaryExpr - xpath_ast_node *parse_path_or_unary_expression() { - // Clarification. - // PathExpr begins with either LocationPath or FilterExpr. - // FilterExpr begins with PrimaryExpr - // PrimaryExpr begins with '$' in case of it being a variable reference, - // '(' in case of it being an expression, string literal, number constant or - // function call. - - if (_lexer.current() == lex_var_ref || _lexer.current() == lex_open_brace || - _lexer.current() == lex_quoted_string || - _lexer.current() == lex_number || _lexer.current() == lex_string) { - if (_lexer.current() == lex_string) { - // This is either a function call, or not - if not, we shall proceed - // with location path - const char_t *state = _lexer.state(); - - while (PUGI__IS_CHARTYPE(*state, ct_space)) - ++state; - - if (*state != '(') - return parse_location_path(); - - // This looks like a function call; however this still can be a - // node-test. Check it. - if (parse_node_test_type(_lexer.contents()) != nodetest_none) - return parse_location_path(); - } - - xpath_ast_node *n = parse_filter_expression(); - - if (_lexer.current() == lex_slash || - _lexer.current() == lex_double_slash) { - lexeme_t l = _lexer.current(); - _lexer.next(); - - if (l == lex_double_slash) { - if (n->rettype() != xpath_type_node_set) - throw_error("Step has to be applied to node set"); - - n = new (alloc_node()) xpath_ast_node( - ast_step, n, axis_descendant_or_self, nodetest_type_node, 0); - } - - // select from location path - return parse_relative_location_path(n); - } - - return n; - } else if (_lexer.current() == lex_minus) { - _lexer.next(); - - // precedence 7+ - only parses union expressions - xpath_ast_node *expr = - parse_expression_rec(parse_path_or_unary_expression(), 7); - - return new (alloc_node()) - xpath_ast_node(ast_op_negate, xpath_type_number, expr); - } else - return parse_location_path(); - } - - struct binary_op_t { - ast_type_t asttype; - xpath_value_type rettype; - int precedence; - - binary_op_t() - : asttype(ast_unknown), rettype(xpath_type_none), precedence(0) {} - - binary_op_t(ast_type_t asttype_, xpath_value_type rettype_, int precedence_) - : asttype(asttype_), rettype(rettype_), precedence(precedence_) {} - - static binary_op_t parse(xpath_lexer &lexer) { - switch (lexer.current()) { - case lex_string: - if (lexer.contents() == PUGIXML_TEXT("or")) - return binary_op_t(ast_op_or, xpath_type_boolean, 1); - else if (lexer.contents() == PUGIXML_TEXT("and")) - return binary_op_t(ast_op_and, xpath_type_boolean, 2); - else if (lexer.contents() == PUGIXML_TEXT("div")) - return binary_op_t(ast_op_divide, xpath_type_number, 6); - else if (lexer.contents() == PUGIXML_TEXT("mod")) - return binary_op_t(ast_op_mod, xpath_type_number, 6); - else - return binary_op_t(); - - case lex_equal: - return binary_op_t(ast_op_equal, xpath_type_boolean, 3); - - case lex_not_equal: - return binary_op_t(ast_op_not_equal, xpath_type_boolean, 3); - - case lex_less: - return binary_op_t(ast_op_less, xpath_type_boolean, 4); - - case lex_greater: - return binary_op_t(ast_op_greater, xpath_type_boolean, 4); - - case lex_less_or_equal: - return binary_op_t(ast_op_less_or_equal, xpath_type_boolean, 4); - - case lex_greater_or_equal: - return binary_op_t(ast_op_greater_or_equal, xpath_type_boolean, 4); - - case lex_plus: - return binary_op_t(ast_op_add, xpath_type_number, 5); - - case lex_minus: - return binary_op_t(ast_op_subtract, xpath_type_number, 5); - - case lex_multiply: - return binary_op_t(ast_op_multiply, xpath_type_number, 6); - - case lex_union: - return binary_op_t(ast_op_union, xpath_type_node_set, 7); - - default: - return binary_op_t(); - } - } - }; - - xpath_ast_node *parse_expression_rec(xpath_ast_node *lhs, int limit) { - binary_op_t op = binary_op_t::parse(_lexer); - - while (op.asttype != ast_unknown && op.precedence >= limit) { - _lexer.next(); - - xpath_ast_node *rhs = parse_path_or_unary_expression(); - - binary_op_t nextop = binary_op_t::parse(_lexer); - - while (nextop.asttype != ast_unknown && - nextop.precedence > op.precedence) { - rhs = parse_expression_rec(rhs, nextop.precedence); - - nextop = binary_op_t::parse(_lexer); - } - - if (op.asttype == ast_op_union && - (lhs->rettype() != xpath_type_node_set || - rhs->rettype() != xpath_type_node_set)) - throw_error("Union operator has to be applied to node sets"); - - lhs = new (alloc_node()) xpath_ast_node(op.asttype, op.rettype, lhs, rhs); - - op = binary_op_t::parse(_lexer); - } - - return lhs; - } - - // Expr ::= OrExpr - // OrExpr ::= AndExpr | OrExpr 'or' AndExpr - // AndExpr ::= EqualityExpr | AndExpr 'and' EqualityExpr - // EqualityExpr ::= RelationalExpr - // | EqualityExpr '=' RelationalExpr - // | EqualityExpr '!=' RelationalExpr - // RelationalExpr ::= AdditiveExpr - // | RelationalExpr '<' AdditiveExpr - // | RelationalExpr '>' AdditiveExpr - // | RelationalExpr '<=' AdditiveExpr - // | RelationalExpr '>=' AdditiveExpr - // AdditiveExpr ::= MultiplicativeExpr - // | AdditiveExpr '+' MultiplicativeExpr - // | AdditiveExpr '-' MultiplicativeExpr - // MultiplicativeExpr ::= UnaryExpr - // | MultiplicativeExpr '*' - // UnaryExpr | MultiplicativeExpr 'div' - // UnaryExpr | MultiplicativeExpr 'mod' UnaryExpr - xpath_ast_node *parse_expression() { - return parse_expression_rec(parse_path_or_unary_expression(), 0); - } - - xpath_parser(const char_t *query, xpath_variable_set *variables, - xpath_allocator *alloc, xpath_parse_result *result) - : _alloc(alloc), _lexer(query), _query(query), _variables(variables), - _result(result) {} - - xpath_ast_node *parse() { - xpath_ast_node *result = parse_expression(); - - if (_lexer.current() != lex_eof) { - // there are still unparsed tokens left, error - throw_error("Incorrect query"); - } - - return result; - } - - static xpath_ast_node *parse(const char_t *query, - xpath_variable_set *variables, - xpath_allocator *alloc, - xpath_parse_result *result) { - xpath_parser parser(query, variables, alloc, result); - -#ifdef PUGIXML_NO_EXCEPTIONS - int error = setjmp(parser._error_handler); - - return (error == 0) ? parser.parse() : 0; -#else - return parser.parse(); -#endif - } -}; - -struct xpath_query_impl { - static xpath_query_impl *create() { - void *memory = xml_memory::allocate(sizeof(xpath_query_impl)); - if (!memory) - return 0; - - return new (memory) xpath_query_impl(); - } - - static void destroy(xpath_query_impl *impl) { - // free all allocated pages - impl->alloc.release(); - - // free allocator memory (with the first page) - xml_memory::deallocate(impl); - } - - xpath_query_impl() : root(0), alloc(&block) { - block.next = 0; - block.capacity = sizeof(block.data); - } - - xpath_ast_node *root; - xpath_allocator alloc; - xpath_memory_block block; -}; - -PUGI__FN xpath_string evaluate_string_impl(xpath_query_impl *impl, - const xpath_node &n, - xpath_stack_data &sd) { - if (!impl) - return xpath_string(); - -#ifdef PUGIXML_NO_EXCEPTIONS - if (setjmp(sd.error_handler)) - return xpath_string(); -#endif - - xpath_context c(n, 1, 1); - - return impl->root->eval_string(c, sd.stack); -} - -PUGI__FN impl::xpath_ast_node * -evaluate_node_set_prepare(xpath_query_impl *impl) { - if (!impl) - return 0; - - if (impl->root->rettype() != xpath_type_node_set) { -#ifdef PUGIXML_NO_EXCEPTIONS - return 0; -#else - xpath_parse_result res; - res.error = "Expression does not evaluate to node set"; - - throw xpath_exception(res); -#endif - } - - return impl->root; -} -PUGI__NS_END - -namespace pugi { -#ifndef PUGIXML_NO_EXCEPTIONS -PUGI__FN xpath_exception::xpath_exception(const xpath_parse_result &result_) - : _result(result_) { - assert(_result.error); -} - -PUGI__FN const char *xpath_exception::what() const throw() { - return _result.error; -} - -PUGI__FN const xpath_parse_result &xpath_exception::result() const { - return _result; -} -#endif - -PUGI__FN xpath_node::xpath_node() {} - -PUGI__FN xpath_node::xpath_node(const xml_node &node_) : _node(node_) {} - -PUGI__FN xpath_node::xpath_node(const xml_attribute &attribute_, - const xml_node &parent_) - : _node(attribute_ ? parent_ : xml_node()), _attribute(attribute_) {} - -PUGI__FN xml_node xpath_node::node() const { - return _attribute ? xml_node() : _node; -} - -PUGI__FN xml_attribute xpath_node::attribute() const { return _attribute; } - -PUGI__FN xml_node xpath_node::parent() const { - return _attribute ? _node : _node.parent(); -} - -PUGI__FN static void unspecified_bool_xpath_node(xpath_node ***) {} - -PUGI__FN xpath_node::operator xpath_node::unspecified_bool_type() const { - return (_node || _attribute) ? unspecified_bool_xpath_node : 0; -} - -PUGI__FN bool xpath_node::operator!() const { return !(_node || _attribute); } - -PUGI__FN bool xpath_node::operator==(const xpath_node &n) const { - return _node == n._node && _attribute == n._attribute; -} - -PUGI__FN bool xpath_node::operator!=(const xpath_node &n) const { - return _node != n._node || _attribute != n._attribute; -} - -#ifdef __BORLANDC__ -PUGI__FN bool operator&&(const xpath_node &lhs, bool rhs) { - return (bool)lhs && rhs; -} - -PUGI__FN bool operator||(const xpath_node &lhs, bool rhs) { - return (bool)lhs || rhs; -} -#endif - -PUGI__FN void xpath_node_set::_assign(const_iterator begin_, - const_iterator end_, type_t type_) { - assert(begin_ <= end_); - - size_t size_ = static_cast(end_ - begin_); - - if (size_ <= 1) { - // deallocate old buffer - if (_begin != &_storage) - impl::xml_memory::deallocate(_begin); - - // use internal buffer - if (begin_ != end_) - _storage = *begin_; - - _begin = &_storage; - _end = &_storage + size_; - _type = type_; - } else { - // make heap copy - xpath_node *storage = static_cast( - impl::xml_memory::allocate(size_ * sizeof(xpath_node))); - - if (!storage) { -#ifdef PUGIXML_NO_EXCEPTIONS - return; -#else - throw std::bad_alloc(); -#endif - } - - memcpy(storage, begin_, size_ * sizeof(xpath_node)); - - // deallocate old buffer - if (_begin != &_storage) - impl::xml_memory::deallocate(_begin); - - // finalize - _begin = storage; - _end = storage + size_; - _type = type_; - } -} - -#if __cplusplus >= 201103 -PUGI__FN void xpath_node_set::_move(xpath_node_set &rhs) { - _type = rhs._type; - _storage = rhs._storage; - _begin = (rhs._begin == &rhs._storage) ? &_storage : rhs._begin; - _end = _begin + (rhs._end - rhs._begin); - - rhs._type = type_unsorted; - rhs._begin = &rhs._storage; - rhs._end = rhs._begin; -} -#endif - -PUGI__FN xpath_node_set::xpath_node_set() - : _type(type_unsorted), _begin(&_storage), _end(&_storage) {} - -PUGI__FN xpath_node_set::xpath_node_set(const_iterator begin_, - const_iterator end_, type_t type_) - : _type(type_unsorted), _begin(&_storage), _end(&_storage) { - _assign(begin_, end_, type_); -} - -PUGI__FN xpath_node_set::~xpath_node_set() { - if (_begin != &_storage) - impl::xml_memory::deallocate(_begin); -} - -PUGI__FN xpath_node_set::xpath_node_set(const xpath_node_set &ns) - : _type(type_unsorted), _begin(&_storage), _end(&_storage) { - _assign(ns._begin, ns._end, ns._type); -} - -PUGI__FN xpath_node_set &xpath_node_set::operator=(const xpath_node_set &ns) { - if (this == &ns) - return *this; - - _assign(ns._begin, ns._end, ns._type); - - return *this; -} - -#if __cplusplus >= 201103 -PUGI__FN xpath_node_set::xpath_node_set(xpath_node_set &&rhs) - : _type(type_unsorted), _begin(&_storage), _end(&_storage) { - _move(rhs); -} - -PUGI__FN xpath_node_set &xpath_node_set::operator=(xpath_node_set &&rhs) { - if (this == &rhs) - return *this; - - if (_begin != &_storage) - impl::xml_memory::deallocate(_begin); - - _move(rhs); - - return *this; -} -#endif - -PUGI__FN xpath_node_set::type_t xpath_node_set::type() const { return _type; } - -PUGI__FN size_t xpath_node_set::size() const { return _end - _begin; } - -PUGI__FN bool xpath_node_set::empty() const { return _begin == _end; } - -PUGI__FN const xpath_node &xpath_node_set::operator[](size_t index) const { - assert(index < size()); - return _begin[index]; -} - -PUGI__FN xpath_node_set::const_iterator xpath_node_set::begin() const { - return _begin; -} - -PUGI__FN xpath_node_set::const_iterator xpath_node_set::end() const { - return _end; -} - -PUGI__FN void xpath_node_set::sort(bool reverse) { - _type = impl::xpath_sort(_begin, _end, _type, reverse); -} - -PUGI__FN xpath_node xpath_node_set::first() const { - return impl::xpath_first(_begin, _end, _type); -} - -PUGI__FN xpath_parse_result::xpath_parse_result() - : error("Internal error"), offset(0) {} - -PUGI__FN xpath_parse_result::operator bool() const { return error == 0; } - -PUGI__FN const char *xpath_parse_result::description() const { - return error ? error : "No error"; -} - -PUGI__FN xpath_variable::xpath_variable(xpath_value_type type_) - : _type(type_), _next(0) {} - -PUGI__FN const char_t *xpath_variable::name() const { - switch (_type) { - case xpath_type_node_set: - return static_cast(this)->name; - - case xpath_type_number: - return static_cast(this)->name; - - case xpath_type_string: - return static_cast(this)->name; - - case xpath_type_boolean: - return static_cast(this)->name; - - default: - assert(!"Invalid variable type"); - return 0; - } -} - -PUGI__FN xpath_value_type xpath_variable::type() const { return _type; } - -PUGI__FN bool xpath_variable::get_boolean() const { - return (_type == xpath_type_boolean) - ? static_cast(this)->value - : false; -} - -PUGI__FN double xpath_variable::get_number() const { - return (_type == xpath_type_number) - ? static_cast(this)->value - : impl::gen_nan(); -} - -PUGI__FN const char_t *xpath_variable::get_string() const { - const char_t *value = - (_type == xpath_type_string) - ? static_cast(this)->value - : 0; - return value ? value : PUGIXML_TEXT(""); -} - -PUGI__FN const xpath_node_set &xpath_variable::get_node_set() const { - return (_type == xpath_type_node_set) - ? static_cast(this)->value - : impl::dummy_node_set; -} - -PUGI__FN bool xpath_variable::set(bool value) { - if (_type != xpath_type_boolean) - return false; - - static_cast(this)->value = value; - return true; -} - -PUGI__FN bool xpath_variable::set(double value) { - if (_type != xpath_type_number) - return false; - - static_cast(this)->value = value; - return true; -} - -PUGI__FN bool xpath_variable::set(const char_t *value) { - if (_type != xpath_type_string) - return false; - - impl::xpath_variable_string *var = - static_cast(this); - - // duplicate string - size_t size = (impl::strlength(value) + 1) * sizeof(char_t); - - char_t *copy = static_cast(impl::xml_memory::allocate(size)); - if (!copy) - return false; - - memcpy(copy, value, size); - - // replace old string - if (var->value) - impl::xml_memory::deallocate(var->value); - var->value = copy; - - return true; -} - -PUGI__FN bool xpath_variable::set(const xpath_node_set &value) { - if (_type != xpath_type_node_set) - return false; - - static_cast(this)->value = value; - return true; -} - -PUGI__FN xpath_variable_set::xpath_variable_set() { - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) - _data[i] = 0; -} - -PUGI__FN xpath_variable_set::~xpath_variable_set() { - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) - _destroy(_data[i]); -} - -PUGI__FN xpath_variable_set::xpath_variable_set(const xpath_variable_set &rhs) { - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) - _data[i] = 0; - - _assign(rhs); -} - -PUGI__FN xpath_variable_set & -xpath_variable_set::operator=(const xpath_variable_set &rhs) { - if (this == &rhs) - return *this; - - _assign(rhs); - - return *this; -} - -#if __cplusplus >= 201103 -PUGI__FN xpath_variable_set::xpath_variable_set(xpath_variable_set &&rhs) { - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) { - _data[i] = rhs._data[i]; - rhs._data[i] = 0; - } -} - -PUGI__FN xpath_variable_set & -xpath_variable_set::operator=(xpath_variable_set &&rhs) { - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) { - _destroy(_data[i]); - - _data[i] = rhs._data[i]; - rhs._data[i] = 0; - } - - return *this; -} -#endif - -PUGI__FN void xpath_variable_set::_assign(const xpath_variable_set &rhs) { - xpath_variable_set temp; - - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) - if (rhs._data[i] && !_clone(rhs._data[i], &temp._data[i])) - return; - - _swap(temp); -} - -PUGI__FN void xpath_variable_set::_swap(xpath_variable_set &rhs) { - for (size_t i = 0; i < sizeof(_data) / sizeof(_data[0]); ++i) { - xpath_variable *chain = _data[i]; - - _data[i] = rhs._data[i]; - rhs._data[i] = chain; - } -} - -PUGI__FN xpath_variable *xpath_variable_set::_find(const char_t *name) const { - const size_t hash_size = sizeof(_data) / sizeof(_data[0]); - size_t hash = impl::hash_string(name) % hash_size; - - // look for existing variable - for (xpath_variable *var = _data[hash]; var; var = var->_next) - if (impl::strequal(var->name(), name)) - return var; - - return 0; -} - -PUGI__FN bool xpath_variable_set::_clone(xpath_variable *var, - xpath_variable **out_result) { - xpath_variable *last = 0; - - while (var) { - // allocate storage for new variable - xpath_variable *nvar = impl::new_xpath_variable(var->_type, var->name()); - if (!nvar) - return false; - - // link the variable to the result immediately to handle failures gracefully - if (last) - last->_next = nvar; - else - *out_result = nvar; - - last = nvar; - - // copy the value; this can fail due to out-of-memory conditions - if (!impl::copy_xpath_variable(nvar, var)) - return false; - - var = var->_next; - } - - return true; -} - -PUGI__FN void xpath_variable_set::_destroy(xpath_variable *var) { - while (var) { - xpath_variable *next = var->_next; - - impl::delete_xpath_variable(var->_type, var); - - var = next; - } -} - -PUGI__FN xpath_variable *xpath_variable_set::add(const char_t *name, - xpath_value_type type) { - const size_t hash_size = sizeof(_data) / sizeof(_data[0]); - size_t hash = impl::hash_string(name) % hash_size; - - // look for existing variable - for (xpath_variable *var = _data[hash]; var; var = var->_next) - if (impl::strequal(var->name(), name)) - return var->type() == type ? var : 0; - - // add new variable - xpath_variable *result = impl::new_xpath_variable(type, name); - - if (result) { - result->_next = _data[hash]; - - _data[hash] = result; - } - - return result; -} - -PUGI__FN bool xpath_variable_set::set(const char_t *name, bool value) { - xpath_variable *var = add(name, xpath_type_boolean); - return var ? var->set(value) : false; -} - -PUGI__FN bool xpath_variable_set::set(const char_t *name, double value) { - xpath_variable *var = add(name, xpath_type_number); - return var ? var->set(value) : false; -} - -PUGI__FN bool xpath_variable_set::set(const char_t *name, const char_t *value) { - xpath_variable *var = add(name, xpath_type_string); - return var ? var->set(value) : false; -} - -PUGI__FN bool xpath_variable_set::set(const char_t *name, - const xpath_node_set &value) { - xpath_variable *var = add(name, xpath_type_node_set); - return var ? var->set(value) : false; -} - -PUGI__FN xpath_variable *xpath_variable_set::get(const char_t *name) { - return _find(name); -} - -PUGI__FN const xpath_variable * -xpath_variable_set::get(const char_t *name) const { - return _find(name); -} - -PUGI__FN xpath_query::xpath_query(const char_t *query, - xpath_variable_set *variables) - : _impl(0) { - impl::xpath_query_impl *qimpl = impl::xpath_query_impl::create(); - - if (!qimpl) { -#ifdef PUGIXML_NO_EXCEPTIONS - _result.error = "Out of memory"; -#else - throw std::bad_alloc(); -#endif - } else { - using impl::auto_deleter; // MSVC7 workaround - auto_deleter impl(qimpl, - impl::xpath_query_impl::destroy); - - qimpl->root = - impl::xpath_parser::parse(query, variables, &qimpl->alloc, &_result); - - if (qimpl->root) { - qimpl->root->optimize(&qimpl->alloc); - - _impl = impl.release(); - _result.error = 0; - } - } -} - -PUGI__FN xpath_query::xpath_query() : _impl(0) {} - -PUGI__FN xpath_query::~xpath_query() { - if (_impl) - impl::xpath_query_impl::destroy( - static_cast(_impl)); -} - -#if __cplusplus >= 201103 -PUGI__FN xpath_query::xpath_query(xpath_query &&rhs) { - _impl = rhs._impl; - _result = rhs._result; - rhs._impl = 0; - rhs._result = xpath_parse_result(); -} - -PUGI__FN xpath_query &xpath_query::operator=(xpath_query &&rhs) { - if (this == &rhs) - return *this; - - if (_impl) - impl::xpath_query_impl::destroy( - static_cast(_impl)); - - _impl = rhs._impl; - _result = rhs._result; - rhs._impl = 0; - rhs._result = xpath_parse_result(); - - return *this; -} -#endif - -PUGI__FN xpath_value_type xpath_query::return_type() const { - if (!_impl) - return xpath_type_none; - - return static_cast(_impl)->root->rettype(); -} - -PUGI__FN bool xpath_query::evaluate_boolean(const xpath_node &n) const { - if (!_impl) - return false; - - impl::xpath_context c(n, 1, 1); - impl::xpath_stack_data sd; - -#ifdef PUGIXML_NO_EXCEPTIONS - if (setjmp(sd.error_handler)) - return false; -#endif - - return static_cast(_impl)->root->eval_boolean( - c, sd.stack); -} - -PUGI__FN double xpath_query::evaluate_number(const xpath_node &n) const { - if (!_impl) - return impl::gen_nan(); - - impl::xpath_context c(n, 1, 1); - impl::xpath_stack_data sd; - -#ifdef PUGIXML_NO_EXCEPTIONS - if (setjmp(sd.error_handler)) - return impl::gen_nan(); -#endif - - return static_cast(_impl)->root->eval_number( - c, sd.stack); -} - -#ifndef PUGIXML_NO_STL -PUGI__FN string_t xpath_query::evaluate_string(const xpath_node &n) const { - impl::xpath_stack_data sd; - - impl::xpath_string r = impl::evaluate_string_impl( - static_cast(_impl), n, sd); - - return string_t(r.c_str(), r.length()); -} -#endif - -PUGI__FN size_t xpath_query::evaluate_string(char_t *buffer, size_t capacity, - const xpath_node &n) const { - impl::xpath_stack_data sd; - - impl::xpath_string r = impl::evaluate_string_impl( - static_cast(_impl), n, sd); - - size_t full_size = r.length() + 1; - - if (capacity > 0) { - size_t size = (full_size < capacity) ? full_size : capacity; - assert(size > 0); - - memcpy(buffer, r.c_str(), (size - 1) * sizeof(char_t)); - buffer[size - 1] = 0; - } - - return full_size; -} - -PUGI__FN xpath_node_set -xpath_query::evaluate_node_set(const xpath_node &n) const { - impl::xpath_ast_node *root = impl::evaluate_node_set_prepare( - static_cast(_impl)); - if (!root) - return xpath_node_set(); - - impl::xpath_context c(n, 1, 1); - impl::xpath_stack_data sd; - -#ifdef PUGIXML_NO_EXCEPTIONS - if (setjmp(sd.error_handler)) - return xpath_node_set(); -#endif - - impl::xpath_node_set_raw r = - root->eval_node_set(c, sd.stack, impl::nodeset_eval_all); - - return xpath_node_set(r.begin(), r.end(), r.type()); -} - -PUGI__FN xpath_node xpath_query::evaluate_node(const xpath_node &n) const { - impl::xpath_ast_node *root = impl::evaluate_node_set_prepare( - static_cast(_impl)); - if (!root) - return xpath_node(); - - impl::xpath_context c(n, 1, 1); - impl::xpath_stack_data sd; - -#ifdef PUGIXML_NO_EXCEPTIONS - if (setjmp(sd.error_handler)) - return xpath_node(); -#endif - - impl::xpath_node_set_raw r = - root->eval_node_set(c, sd.stack, impl::nodeset_eval_first); - - return r.first(); -} - -PUGI__FN const xpath_parse_result &xpath_query::result() const { - return _result; -} - -PUGI__FN static void unspecified_bool_xpath_query(xpath_query ***) {} - -PUGI__FN xpath_query::operator xpath_query::unspecified_bool_type() const { - return _impl ? unspecified_bool_xpath_query : 0; -} - -PUGI__FN bool xpath_query::operator!() const { return !_impl; } - -PUGI__FN xpath_node xml_node::select_node(const char_t *query, - xpath_variable_set *variables) const { - xpath_query q(query, variables); - return select_node(q); -} - -PUGI__FN xpath_node xml_node::select_node(const xpath_query &query) const { - return query.evaluate_node(*this); -} - -PUGI__FN xpath_node_set xml_node::select_nodes( - const char_t *query, xpath_variable_set *variables) const { - xpath_query q(query, variables); - return select_nodes(q); -} - -PUGI__FN xpath_node_set xml_node::select_nodes(const xpath_query &query) const { - return query.evaluate_node_set(*this); -} - -PUGI__FN xpath_node xml_node::select_single_node( - const char_t *query, xpath_variable_set *variables) const { - xpath_query q(query, variables); - return select_single_node(q); -} - -PUGI__FN xpath_node -xml_node::select_single_node(const xpath_query &query) const { - return query.evaluate_node(*this); -} -} // namespace pugi - -#endif - -#ifdef __BORLANDC__ -#pragma option pop -#endif - -// Intel C++ does not properly keep warning state for function templates, -// so popping warning state at the end of translation unit leads to warnings in -// the middle. -#if defined(_MSC_VER) && !defined(__INTEL_COMPILER) -#pragma warning(pop) -#endif - -// Undefine all local macros (makes sure we're not leaking macros in header-only -// mode) -#undef PUGI__NO_INLINE -#undef PUGI__UNLIKELY -#undef PUGI__STATIC_ASSERT -#undef PUGI__DMC_VOLATILE -#undef PUGI__MSVC_CRT_VERSION -#undef PUGI__NS_BEGIN -#undef PUGI__NS_END -#undef PUGI__FN -#undef PUGI__FN_NO_INLINE -#undef PUGI__GETPAGE_IMPL -#undef PUGI__GETPAGE -#undef PUGI__NODETYPE -#undef PUGI__IS_CHARTYPE_IMPL -#undef PUGI__IS_CHARTYPE -#undef PUGI__IS_CHARTYPEX -#undef PUGI__ENDSWITH -#undef PUGI__SKIPWS -#undef PUGI__OPTSET -#undef PUGI__PUSHNODE -#undef PUGI__POPNODE -#undef PUGI__SCANFOR -#undef PUGI__SCANWHILE -#undef PUGI__SCANWHILE_UNROLL -#undef PUGI__ENDSEG -#undef PUGI__THROW_ERROR -#undef PUGI__CHECK_ERROR - -#endif - -/** - * Copyright (c) 2006-2015 Arseny Kapoulkine - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ diff --git a/techlibs/rapidflex/src/pugixml.hpp b/techlibs/rapidflex/src/pugixml.hpp deleted file mode 100644 index 55707f6fa..000000000 --- a/techlibs/rapidflex/src/pugixml.hpp +++ /dev/null @@ -1,1544 +0,0 @@ -/** - * pugixml parser - version 1.7 - * -------------------------------------------------------- - * Copyright (C) 2006-2015, by Arseny Kapoulkine (arseny.kapoulkine@gmail.com) - * Report bugs and download new versions at http://pugixml.org/ - * - * This library is distributed under the MIT License. See notice at the end - * of this file. - * - * This work is based on the pugxml parser, which is: - * Copyright (C) 2003, by Kristen Wegner (kristen@tima.net) - */ - -#ifndef PUGIXML_VERSION -// Define version macro; evaluates to major * 100 + minor so that it's safe to -// use in less-than comparisons -#define PUGIXML_VERSION 170 -#endif - -// Include user configuration file (this can define various configuration -// macros) -#include "pugiconfig.hpp" - -#ifndef HEADER_PUGIXML_HPP -#define HEADER_PUGIXML_HPP - -// Include stddef.h for size_t and ptrdiff_t -#include - -// Include exception header for XPath -#if !defined(PUGIXML_NO_XPATH) && !defined(PUGIXML_NO_EXCEPTIONS) -#include -#endif - -// Include STL headers -#ifndef PUGIXML_NO_STL -#include -#include -#include -#endif - -// Macro for deprecated features -#ifndef PUGIXML_DEPRECATED -#if defined(__GNUC__) -#define PUGIXML_DEPRECATED __attribute__((deprecated)) -#elif defined(_MSC_VER) && _MSC_VER >= 1300 -#define PUGIXML_DEPRECATED __declspec(deprecated) -#else -#define PUGIXML_DEPRECATED -#endif -#endif - -// If no API is defined, assume default -#ifndef PUGIXML_API -#define PUGIXML_API -#endif - -// If no API for classes is defined, assume default -#ifndef PUGIXML_CLASS -#define PUGIXML_CLASS PUGIXML_API -#endif - -// If no API for functions is defined, assume default -#ifndef PUGIXML_FUNCTION -#define PUGIXML_FUNCTION PUGIXML_API -#endif - -// If the platform is known to have long long support, enable long long -// functions -#ifndef PUGIXML_HAS_LONG_LONG -#if __cplusplus >= 201103 -#define PUGIXML_HAS_LONG_LONG -#elif defined(_MSC_VER) && _MSC_VER >= 1400 -#define PUGIXML_HAS_LONG_LONG -#endif -#endif - -// Character interface macros -#ifdef PUGIXML_WCHAR_MODE -#define PUGIXML_TEXT(t) L##t -#define PUGIXML_CHAR wchar_t -#else -#define PUGIXML_TEXT(t) t -#define PUGIXML_CHAR char -#endif - -namespace pugi { -// Character type used for all internal storage and operations; depends on -// PUGIXML_WCHAR_MODE -typedef PUGIXML_CHAR char_t; - -#ifndef PUGIXML_NO_STL -// String type used for operations that work with STL string; depends on -// PUGIXML_WCHAR_MODE -typedef std::basic_string, - std::allocator> - string_t; -#endif -} // namespace pugi - -// The PugiXML namespace -namespace pugi { -// Tree node types -enum xml_node_type { - node_null, // Empty (null) node handle - node_document, // A document tree's absolute root - node_element, // Element tag, i.e. '' - node_pcdata, // Plain character data, i.e. 'text' - node_cdata, // Character data, i.e. '' - node_comment, // Comment tag, i.e. '' - node_pi, // Processing instruction, i.e. '' - node_declaration, // Document declaration, i.e. '' - node_doctype // Document type declaration, i.e. '' -}; - -// Parsing options - -// Minimal parsing mode (equivalent to turning all other flags off). -// Only elements and PCDATA sections are added to the DOM tree, no text -// conversions are performed. -const unsigned int parse_minimal = 0x0000; - -// This flag determines if processing instructions (node_pi) are added to the -// DOM tree. This flag is off by default. -const unsigned int parse_pi = 0x0001; - -// This flag determines if comments (node_comment) are added to the DOM tree. -// This flag is off by default. -const unsigned int parse_comments = 0x0002; - -// This flag determines if CDATA sections (node_cdata) are added to the DOM -// tree. This flag is on by default. -const unsigned int parse_cdata = 0x0004; - -// This flag determines if plain character data (node_pcdata) that consist only -// of whitespace are added to the DOM tree. This flag is off by default; turning -// it on usually results in slower parsing and more memory consumption. -const unsigned int parse_ws_pcdata = 0x0008; - -// This flag determines if character and entity references are expanded during -// parsing. This flag is on by default. -const unsigned int parse_escapes = 0x0010; - -// This flag determines if EOL characters are normalized (converted to #xA) -// during parsing. This flag is on by default. -const unsigned int parse_eol = 0x0020; - -// This flag determines if attribute values are normalized using CDATA -// normalization rules during parsing. This flag is on by default. -const unsigned int parse_wconv_attribute = 0x0040; - -// This flag determines if attribute values are normalized using NMTOKENS -// normalization rules during parsing. This flag is off by default. -const unsigned int parse_wnorm_attribute = 0x0080; - -// This flag determines if document declaration (node_declaration) is added to -// the DOM tree. This flag is off by default. -const unsigned int parse_declaration = 0x0100; - -// This flag determines if document type declaration (node_doctype) is added to -// the DOM tree. This flag is off by default. -const unsigned int parse_doctype = 0x0200; - -// This flag determines if plain character data (node_pcdata) that is the only -// child of the parent node and that consists only of whitespace is added to the -// DOM tree. This flag is off by default; turning it on may result in slower -// parsing and more memory consumption. -const unsigned int parse_ws_pcdata_single = 0x0400; - -// This flag determines if leading and trailing whitespace is to be removed from -// plain character data. This flag is off by default. -const unsigned int parse_trim_pcdata = 0x0800; - -// This flag determines if plain character data that does not have a parent node -// is added to the DOM tree, and if an empty document is a valid document. This -// flag is off by default. -const unsigned int parse_fragment = 0x1000; - -// The default parsing mode. -// Elements, PCDATA and CDATA sections are added to the DOM tree, -// character/reference entities are expanded, End-of-Line characters are -// normalized, attribute values are normalized using CDATA normalization rules. -const unsigned int parse_default = - parse_cdata | parse_escapes | parse_wconv_attribute | parse_eol; - -// The full parsing mode. -// Nodes of all types are added to the DOM tree, character/reference entities -// are expanded, End-of-Line characters are normalized, attribute values are -// normalized using CDATA normalization rules. -const unsigned int parse_full = parse_default | parse_pi | parse_comments | - parse_declaration | parse_doctype; - -// These flags determine the encoding of input data for XML document -enum xml_encoding { - encoding_auto, // Auto-detect input encoding using BOM or < / class xml_object_range { -public: - typedef It const_iterator; - typedef It iterator; - - xml_object_range(It b, It e) : _begin(b), _end(e) {} - - It begin() const { return _begin; } - It end() const { return _end; } - -private: - It _begin, _end; -}; - -// Writer interface for node printing (see xml_node::print) -class PUGIXML_CLASS xml_writer { -public: - virtual ~xml_writer() {} - - // Write memory chunk into stream/file/whatever - virtual void write(const void *data, size_t size) = 0; -}; - -// xml_writer implementation for FILE* -class PUGIXML_CLASS xml_writer_file : public xml_writer { -public: - // Construct writer from a FILE* object; void* is used to avoid header - // dependencies on stdio - xml_writer_file(void *file); - - virtual void write(const void *data, size_t size); - -private: - void *file; -}; - -#ifndef PUGIXML_NO_STL -// xml_writer implementation for streams -class PUGIXML_CLASS xml_writer_stream : public xml_writer { -public: - // Construct writer from an output stream object - xml_writer_stream(std::basic_ostream> &stream); - xml_writer_stream( - std::basic_ostream> &stream); - - virtual void write(const void *data, size_t size); - -private: - std::basic_ostream> *narrow_stream; - std::basic_ostream> *wide_stream; -}; -#endif - -// A light-weight handle for manipulating attributes in DOM tree -class PUGIXML_CLASS xml_attribute { - friend class xml_attribute_iterator; - friend class xml_node; - -private: - xml_attribute_struct *_attr; - - typedef void (*unspecified_bool_type)(xml_attribute ***); - -public: - // Default constructor. Constructs an empty attribute. - xml_attribute(); - - // Constructs attribute from internal pointer - explicit xml_attribute(xml_attribute_struct *attr); - - // Safe bool conversion operator - operator unspecified_bool_type() const; - - // Borland C++ workaround - bool operator!() const; - - // Comparison operators (compares wrapped attribute pointers) - bool operator==(const xml_attribute &r) const; - bool operator!=(const xml_attribute &r) const; - bool operator<(const xml_attribute &r) const; - bool operator>(const xml_attribute &r) const; - bool operator<=(const xml_attribute &r) const; - bool operator>=(const xml_attribute &r) const; - - // Check if attribute is empty - bool empty() const; - - // Get attribute name/value, or "" if attribute is empty - const char_t *name() const; - const char_t *value() const; - - // Get attribute value, or the default value if attribute is empty - const char_t *as_string(const char_t *def = PUGIXML_TEXT("")) const; - - // Get attribute value as a number, or the default value if conversion did not - // succeed or attribute is empty - int as_int(int def = 0) const; - unsigned int as_uint(unsigned int def = 0) const; - double as_double(double def = 0) const; - float as_float(float def = 0) const; - -#ifdef PUGIXML_HAS_LONG_LONG - long long as_llong(long long def = 0) const; - unsigned long long as_ullong(unsigned long long def = 0) const; -#endif - - // Get attribute value as bool (returns true if first character is in '1tTyY' - // set), or the default value if attribute is empty - bool as_bool(bool def = false) const; - - // Set attribute name/value (returns false if attribute is empty or there is - // not enough memory) - bool set_name(const char_t *rhs); - bool set_value(const char_t *rhs); - - // Set attribute value with type conversion (numbers are converted to strings, - // boolean is converted to "true"/"false") - bool set_value(int rhs); - bool set_value(unsigned int rhs); - bool set_value(double rhs); - bool set_value(float rhs); - bool set_value(bool rhs); - -#ifdef PUGIXML_HAS_LONG_LONG - bool set_value(long long rhs); - bool set_value(unsigned long long rhs); -#endif - - // Set attribute value (equivalent to set_value without error checking) - xml_attribute &operator=(const char_t *rhs); - xml_attribute &operator=(int rhs); - xml_attribute &operator=(unsigned int rhs); - xml_attribute &operator=(double rhs); - xml_attribute &operator=(float rhs); - xml_attribute &operator=(bool rhs); - -#ifdef PUGIXML_HAS_LONG_LONG - xml_attribute &operator=(long long rhs); - xml_attribute &operator=(unsigned long long rhs); -#endif - - // Get next/previous attribute in the attribute list of the parent node - xml_attribute next_attribute() const; - xml_attribute previous_attribute() const; - - // Get hash value (unique for handles to the same object) - size_t hash_value() const; - - // Get internal pointer - xml_attribute_struct *internal_object() const; -}; - -#ifdef __BORLANDC__ -// Borland C++ workaround -bool PUGIXML_FUNCTION operator&&(const xml_attribute &lhs, bool rhs); -bool PUGIXML_FUNCTION operator||(const xml_attribute &lhs, bool rhs); -#endif - -// A light-weight handle for manipulating nodes in DOM tree -class PUGIXML_CLASS xml_node { - friend class xml_attribute_iterator; - friend class xml_node_iterator; - friend class xml_named_node_iterator; - -protected: - xml_node_struct *_root; - - typedef void (*unspecified_bool_type)(xml_node ***); - -public: - // Default constructor. Constructs an empty node. - xml_node(); - - // Constructs node from internal pointer - explicit xml_node(xml_node_struct *p); - - // Safe bool conversion operator - operator unspecified_bool_type() const; - - // Borland C++ workaround - bool operator!() const; - - // Comparison operators (compares wrapped node pointers) - bool operator==(const xml_node &r) const; - bool operator!=(const xml_node &r) const; - bool operator<(const xml_node &r) const; - bool operator>(const xml_node &r) const; - bool operator<=(const xml_node &r) const; - bool operator>=(const xml_node &r) const; - - // Check if node is empty. - bool empty() const; - - // Get node type - xml_node_type type() const; - - // Get node name, or "" if node is empty or it has no name - const char_t *name() const; - - // Get node value, or "" if node is empty or it has no value - // Note: For text node.value() does not return "text"! Use - // child_value() or text() methods to access text inside nodes. - const char_t *value() const; - - // Get attribute list - xml_attribute first_attribute() const; - xml_attribute last_attribute() const; - - // Get children list - xml_node first_child() const; - xml_node last_child() const; - - // Get next/previous sibling in the children list of the parent node - xml_node next_sibling() const; - xml_node previous_sibling() const; - - // Get parent node - xml_node parent() const; - - // Get root of DOM tree this node belongs to - xml_node root() const; - - // Get text object for the current node - xml_text text() const; - - // Get child, attribute or next/previous sibling with the specified name - xml_node child(const char_t *name) const; - xml_attribute attribute(const char_t *name) const; - xml_node next_sibling(const char_t *name) const; - xml_node previous_sibling(const char_t *name) const; - - // Get attribute, starting the search from a hint (and updating hint so that - // searching for a sequence of attributes is fast) - xml_attribute attribute(const char_t *name, xml_attribute &hint) const; - - // Get child value of current node; that is, value of the first child node of - // type PCDATA/CDATA - const char_t *child_value() const; - - // Get child value of child with specified name. Equivalent to - // child(name).child_value(). - const char_t *child_value(const char_t *name) const; - - // Set node name/value (returns false if node is empty, there is not enough - // memory, or node can not have name/value) - bool set_name(const char_t *rhs); - bool set_value(const char_t *rhs); - - // Add attribute with specified name. Returns added attribute, or empty - // attribute on errors. - xml_attribute append_attribute(const char_t *name); - xml_attribute prepend_attribute(const char_t *name); - xml_attribute insert_attribute_after(const char_t *name, - const xml_attribute &attr); - xml_attribute insert_attribute_before(const char_t *name, - const xml_attribute &attr); - - // Add a copy of the specified attribute. Returns added attribute, or empty - // attribute on errors. - xml_attribute append_copy(const xml_attribute &proto); - xml_attribute prepend_copy(const xml_attribute &proto); - xml_attribute insert_copy_after(const xml_attribute &proto, - const xml_attribute &attr); - xml_attribute insert_copy_before(const xml_attribute &proto, - const xml_attribute &attr); - - // Add child node with specified type. Returns added node, or empty node on - // errors. - xml_node append_child(xml_node_type type = node_element); - xml_node prepend_child(xml_node_type type = node_element); - xml_node insert_child_after(xml_node_type type, const xml_node &node); - xml_node insert_child_before(xml_node_type type, const xml_node &node); - - // Add child element with specified name. Returns added node, or empty node on - // errors. - xml_node append_child(const char_t *name); - xml_node prepend_child(const char_t *name); - xml_node insert_child_after(const char_t *name, const xml_node &node); - xml_node insert_child_before(const char_t *name, const xml_node &node); - - // Add a copy of the specified node as a child. Returns added node, or empty - // node on errors. - xml_node append_copy(const xml_node &proto); - xml_node prepend_copy(const xml_node &proto); - xml_node insert_copy_after(const xml_node &proto, const xml_node &node); - xml_node insert_copy_before(const xml_node &proto, const xml_node &node); - - // Move the specified node to become a child of this node. Returns moved node, - // or empty node on errors. - xml_node append_move(const xml_node &moved); - xml_node prepend_move(const xml_node &moved); - xml_node insert_move_after(const xml_node &moved, const xml_node &node); - xml_node insert_move_before(const xml_node &moved, const xml_node &node); - - // Remove specified attribute - bool remove_attribute(const xml_attribute &a); - bool remove_attribute(const char_t *name); - - // Remove specified child - bool remove_child(const xml_node &n); - bool remove_child(const char_t *name); - - // Parses buffer as an XML document fragment and appends all nodes as children - // of the current node. Copies/converts the buffer, so it may be deleted or - // changed after the function returns. Note: append_buffer allocates memory - // that has the lifetime of the owning document; removing the appended nodes - // does not immediately reclaim that memory. - xml_parse_result append_buffer(const void *contents, size_t size, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - - // Find attribute using predicate. Returns first attribute for which predicate - // returned true. - template - xml_attribute find_attribute(Predicate pred) const { - if (!_root) - return xml_attribute(); - - for (xml_attribute attrib = first_attribute(); attrib; - attrib = attrib.next_attribute()) - if (pred(attrib)) - return attrib; - - return xml_attribute(); - } - - // Find child node using predicate. Returns first child for which predicate - // returned true. - template xml_node find_child(Predicate pred) const { - if (!_root) - return xml_node(); - - for (xml_node node = first_child(); node; node = node.next_sibling()) - if (pred(node)) - return node; - - return xml_node(); - } - - // Find node from subtree using predicate. Returns first node from subtree - // (depth-first), for which predicate returned true. - template xml_node find_node(Predicate pred) const { - if (!_root) - return xml_node(); - - xml_node cur = first_child(); - - while (cur._root && cur._root != _root) { - if (pred(cur)) - return cur; - - if (cur.first_child()) - cur = cur.first_child(); - else if (cur.next_sibling()) - cur = cur.next_sibling(); - else { - while (!cur.next_sibling() && cur._root != _root) - cur = cur.parent(); - - if (cur._root != _root) - cur = cur.next_sibling(); - } - } - - return xml_node(); - } - - // Find child node by attribute name/value - xml_node find_child_by_attribute(const char_t *name, const char_t *attr_name, - const char_t *attr_value) const; - xml_node find_child_by_attribute(const char_t *attr_name, - const char_t *attr_value) const; - -#ifndef PUGIXML_NO_STL - // Get the absolute node path from root as a text string. - string_t path(char_t delimiter = '/') const; -#endif - - // Search for a node by path consisting of node names and . or .. elements. - xml_node first_element_by_path(const char_t *path, - char_t delimiter = '/') const; - - // Recursively traverse subtree with xml_tree_walker - bool traverse(xml_tree_walker &walker); - -#ifndef PUGIXML_NO_XPATH - // Select single node by evaluating XPath query. Returns first node from the - // resulting node set. - xpath_node select_node(const char_t *query, - xpath_variable_set *variables = 0) const; - xpath_node select_node(const xpath_query &query) const; - - // Select node set by evaluating XPath query - xpath_node_set select_nodes(const char_t *query, - xpath_variable_set *variables = 0) const; - xpath_node_set select_nodes(const xpath_query &query) const; - - // (deprecated: use select_node instead) Select single node by evaluating - // XPath query. - xpath_node select_single_node(const char_t *query, - xpath_variable_set *variables = 0) const; - xpath_node select_single_node(const xpath_query &query) const; - -#endif - - // Print subtree using a writer object - void print(xml_writer &writer, const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, - xml_encoding encoding = encoding_auto, - unsigned int depth = 0) const; - -#ifndef PUGIXML_NO_STL - // Print subtree to stream - void print(std::basic_ostream> &os, - const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, - xml_encoding encoding = encoding_auto, - unsigned int depth = 0) const; - void print(std::basic_ostream> &os, - const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, unsigned int depth = 0) const; -#endif - - // Child nodes iterators - typedef xml_node_iterator iterator; - - iterator begin() const; - iterator end() const; - - // Attribute iterators - typedef xml_attribute_iterator attribute_iterator; - - attribute_iterator attributes_begin() const; - attribute_iterator attributes_end() const; - - // Range-based for support - xml_object_range children() const; - xml_object_range children(const char_t *name) const; - xml_object_range attributes() const; - - // Get node offset in parsed file/string (in char_t units) for debugging - // purposes - ptrdiff_t offset_debug() const; - - // Get hash value (unique for handles to the same object) - size_t hash_value() const; - - // Get internal pointer - xml_node_struct *internal_object() const; -}; - -#ifdef __BORLANDC__ -// Borland C++ workaround -bool PUGIXML_FUNCTION operator&&(const xml_node &lhs, bool rhs); -bool PUGIXML_FUNCTION operator||(const xml_node &lhs, bool rhs); -#endif - -// A helper for working with text inside PCDATA nodes -class PUGIXML_CLASS xml_text { - friend class xml_node; - - xml_node_struct *_root; - - typedef void (*unspecified_bool_type)(xml_text ***); - - explicit xml_text(xml_node_struct *root); - - xml_node_struct *_data_new(); - xml_node_struct *_data() const; - -public: - // Default constructor. Constructs an empty object. - xml_text(); - - // Safe bool conversion operator - operator unspecified_bool_type() const; - - // Borland C++ workaround - bool operator!() const; - - // Check if text object is empty - bool empty() const; - - // Get text, or "" if object is empty - const char_t *get() const; - - // Get text, or the default value if object is empty - const char_t *as_string(const char_t *def = PUGIXML_TEXT("")) const; - - // Get text as a number, or the default value if conversion did not succeed or - // object is empty - int as_int(int def = 0) const; - unsigned int as_uint(unsigned int def = 0) const; - double as_double(double def = 0) const; - float as_float(float def = 0) const; - -#ifdef PUGIXML_HAS_LONG_LONG - long long as_llong(long long def = 0) const; - unsigned long long as_ullong(unsigned long long def = 0) const; -#endif - - // Get text as bool (returns true if first character is in '1tTyY' set), or - // the default value if object is empty - bool as_bool(bool def = false) const; - - // Set text (returns false if object is empty or there is not enough memory) - bool set(const char_t *rhs); - - // Set text with type conversion (numbers are converted to strings, boolean is - // converted to "true"/"false") - bool set(int rhs); - bool set(unsigned int rhs); - bool set(double rhs); - bool set(float rhs); - bool set(bool rhs); - -#ifdef PUGIXML_HAS_LONG_LONG - bool set(long long rhs); - bool set(unsigned long long rhs); -#endif - - // Set text (equivalent to set without error checking) - xml_text &operator=(const char_t *rhs); - xml_text &operator=(int rhs); - xml_text &operator=(unsigned int rhs); - xml_text &operator=(double rhs); - xml_text &operator=(float rhs); - xml_text &operator=(bool rhs); - -#ifdef PUGIXML_HAS_LONG_LONG - xml_text &operator=(long long rhs); - xml_text &operator=(unsigned long long rhs); -#endif - - // Get the data node (node_pcdata or node_cdata) for this object - xml_node data() const; -}; - -#ifdef __BORLANDC__ -// Borland C++ workaround -bool PUGIXML_FUNCTION operator&&(const xml_text &lhs, bool rhs); -bool PUGIXML_FUNCTION operator||(const xml_text &lhs, bool rhs); -#endif - -// Child node iterator (a bidirectional iterator over a collection of xml_node) -class PUGIXML_CLASS xml_node_iterator { - friend class xml_node; - -private: - mutable xml_node _wrap; - xml_node _parent; - - xml_node_iterator(xml_node_struct *ref, xml_node_struct *parent); - -public: - // Iterator traits - typedef ptrdiff_t difference_type; - typedef xml_node value_type; - typedef xml_node *pointer; - typedef xml_node &reference; - -#ifndef PUGIXML_NO_STL - typedef std::bidirectional_iterator_tag iterator_category; -#endif - - // Default constructor - xml_node_iterator(); - - // Construct an iterator which points to the specified node - xml_node_iterator(const xml_node &node); - - // Iterator operators - bool operator==(const xml_node_iterator &rhs) const; - bool operator!=(const xml_node_iterator &rhs) const; - - xml_node &operator*() const; - xml_node *operator->() const; - - const xml_node_iterator &operator++(); - xml_node_iterator operator++(int); - - const xml_node_iterator &operator--(); - xml_node_iterator operator--(int); -}; - -// Attribute iterator (a bidirectional iterator over a collection of -// xml_attribute) -class PUGIXML_CLASS xml_attribute_iterator { - friend class xml_node; - -private: - mutable xml_attribute _wrap; - xml_node _parent; - - xml_attribute_iterator(xml_attribute_struct *ref, xml_node_struct *parent); - -public: - // Iterator traits - typedef ptrdiff_t difference_type; - typedef xml_attribute value_type; - typedef xml_attribute *pointer; - typedef xml_attribute &reference; - -#ifndef PUGIXML_NO_STL - typedef std::bidirectional_iterator_tag iterator_category; -#endif - - // Default constructor - xml_attribute_iterator(); - - // Construct an iterator which points to the specified attribute - xml_attribute_iterator(const xml_attribute &attr, const xml_node &parent); - - // Iterator operators - bool operator==(const xml_attribute_iterator &rhs) const; - bool operator!=(const xml_attribute_iterator &rhs) const; - - xml_attribute &operator*() const; - xml_attribute *operator->() const; - - const xml_attribute_iterator &operator++(); - xml_attribute_iterator operator++(int); - - const xml_attribute_iterator &operator--(); - xml_attribute_iterator operator--(int); -}; - -// Named node range helper -class PUGIXML_CLASS xml_named_node_iterator { - friend class xml_node; - -public: - // Iterator traits - typedef ptrdiff_t difference_type; - typedef xml_node value_type; - typedef xml_node *pointer; - typedef xml_node &reference; - -#ifndef PUGIXML_NO_STL - typedef std::bidirectional_iterator_tag iterator_category; -#endif - - // Default constructor - xml_named_node_iterator(); - - // Construct an iterator which points to the specified node - xml_named_node_iterator(const xml_node &node, const char_t *name); - - // Iterator operators - bool operator==(const xml_named_node_iterator &rhs) const; - bool operator!=(const xml_named_node_iterator &rhs) const; - - xml_node &operator*() const; - xml_node *operator->() const; - - const xml_named_node_iterator &operator++(); - xml_named_node_iterator operator++(int); - - const xml_named_node_iterator &operator--(); - xml_named_node_iterator operator--(int); - -private: - mutable xml_node _wrap; - xml_node _parent; - const char_t *_name; - - xml_named_node_iterator(xml_node_struct *ref, xml_node_struct *parent, - const char_t *name); -}; - -// Abstract tree walker class (see xml_node::traverse) -class PUGIXML_CLASS xml_tree_walker { - friend class xml_node; - -private: - int _depth; - -protected: - // Get current traversal depth - int depth() const; - -public: - xml_tree_walker(); - virtual ~xml_tree_walker(); - - // Callback that is called when traversal begins - virtual bool begin(xml_node &node); - - // Callback that is called for each node traversed - virtual bool for_each(xml_node &node) = 0; - - // Callback that is called when traversal ends - virtual bool end(xml_node &node); -}; - -// Parsing status, returned as part of xml_parse_result object -enum xml_parse_status { - status_ok = 0, // No error - - status_file_not_found, // File was not found during load_file() - status_io_error, // Error reading from file/stream - status_out_of_memory, // Could not allocate memory - status_internal_error, // Internal error occurred - - status_unrecognized_tag, // Parser could not determine tag type - - status_bad_pi, // Parsing error occurred while parsing document - // declaration/processing instruction - status_bad_comment, // Parsing error occurred while parsing comment - status_bad_cdata, // Parsing error occurred while parsing CDATA section - status_bad_doctype, // Parsing error occurred while parsing document type - // declaration - status_bad_pcdata, // Parsing error occurred while parsing PCDATA section - status_bad_start_element, // Parsing error occurred while parsing start - // element tag - status_bad_attribute, // Parsing error occurred while parsing element - // attribute - status_bad_end_element, // Parsing error occurred while parsing end element - // tag - status_end_element_mismatch, // There was a mismatch of start-end tags - // (closing tag had incorrect name, some tag was - // not closed or there was an excessive closing - // tag) - - status_append_invalid_root, // Unable to append nodes since root type is not - // node_element or node_document (exclusive to - // xml_node::append_buffer) - - status_no_document_element // Parsing resulted in a document without element - // nodes -}; - -// Parsing result -struct PUGIXML_CLASS xml_parse_result { - // Parsing status (see xml_parse_status) - xml_parse_status status; - - // Last parsed offset (in char_t units from start of input data) - ptrdiff_t offset; - - // Source document encoding - xml_encoding encoding; - - // Default constructor, initializes object to failed state - xml_parse_result(); - - // Cast to bool operator - operator bool() const; - - // Get error description - const char *description() const; -}; - -// Document class (DOM tree root) -class PUGIXML_CLASS xml_document : public xml_node { -private: - char_t *_buffer; - - char _memory[192]; - - // Non-copyable semantics - xml_document(const xml_document &); - xml_document &operator=(const xml_document &); - - void create(); - void destroy(); - -public: - // Default constructor, makes empty document - xml_document(); - - // Destructor, invalidates all node/attribute handles to this document - ~xml_document(); - - // Removes all nodes, leaving the empty document - void reset(); - - // Removes all nodes, then copies the entire contents of the specified - // document - void reset(const xml_document &proto); - -#ifndef PUGIXML_NO_STL - // Load document from stream. - xml_parse_result - load(std::basic_istream> &stream, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - xml_parse_result - load(std::basic_istream> &stream, - unsigned int options = parse_default); -#endif - - // (deprecated: use load_string instead) Load document from zero-terminated - // string. No encoding conversions are applied. - xml_parse_result load(const char_t *contents, - unsigned int options = parse_default); - - // Load document from zero-terminated string. No encoding conversions are - // applied. - xml_parse_result load_string(const char_t *contents, - unsigned int options = parse_default); - - // Load document from file - xml_parse_result load_file(const char *path, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - xml_parse_result load_file(const wchar_t *path, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - - // Load document from buffer. Copies/converts the buffer, so it may be deleted - // or changed after the function returns. - xml_parse_result load_buffer(const void *contents, size_t size, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - - // Load document from buffer, using the buffer for in-place parsing (the - // buffer is modified and used for storage of document data). You should - // ensure that buffer data will persist throughout the document's lifetime, - // and free the buffer memory manually once document is destroyed. - xml_parse_result load_buffer_inplace(void *contents, size_t size, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - - // Load document from buffer, using the buffer for in-place parsing (the - // buffer is modified and used for storage of document data). You should - // allocate the buffer with pugixml allocation function; document will free - // the buffer when it is no longer needed (you can't use it anymore). - xml_parse_result - load_buffer_inplace_own(void *contents, size_t size, - unsigned int options = parse_default, - xml_encoding encoding = encoding_auto); - - // Save XML document to writer (semantics is slightly different from - // xml_node::print, see documentation for details). - void save(xml_writer &writer, const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, - xml_encoding encoding = encoding_auto) const; - -#ifndef PUGIXML_NO_STL - // Save XML document to stream (semantics is slightly different from - // xml_node::print, see documentation for details). - void save(std::basic_ostream> &stream, - const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, - xml_encoding encoding = encoding_auto) const; - void save(std::basic_ostream> &stream, - const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default) const; -#endif - - // Save XML to file - bool save_file(const char *path, const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, - xml_encoding encoding = encoding_auto) const; - bool save_file(const wchar_t *path, const char_t *indent = PUGIXML_TEXT("\t"), - unsigned int flags = format_default, - xml_encoding encoding = encoding_auto) const; - - // Get document element - xml_node document_element() const; -}; - -#ifndef PUGIXML_NO_XPATH -// XPath query return type -enum xpath_value_type { - xpath_type_none, // Unknown type (query failed to compile) - xpath_type_node_set, // Node set (xpath_node_set) - xpath_type_number, // Number - xpath_type_string, // String - xpath_type_boolean // Boolean -}; - -// XPath parsing result -struct PUGIXML_CLASS xpath_parse_result { - // Error message (0 if no error) - const char *error; - - // Last parsed offset (in char_t units from string start) - ptrdiff_t offset; - - // Default constructor, initializes object to failed state - xpath_parse_result(); - - // Cast to bool operator - operator bool() const; - - // Get error description - const char *description() const; -}; - -// A single XPath variable -class PUGIXML_CLASS xpath_variable { - friend class xpath_variable_set; - -protected: - xpath_value_type _type; - xpath_variable *_next; - - xpath_variable(xpath_value_type type); - - // Non-copyable semantics - xpath_variable(const xpath_variable &); - xpath_variable &operator=(const xpath_variable &); - -public: - // Get variable name - const char_t *name() const; - - // Get variable type - xpath_value_type type() const; - - // Get variable value; no type conversion is performed, default value (false, - // NaN, empty string, empty node set) is returned on type mismatch error - bool get_boolean() const; - double get_number() const; - const char_t *get_string() const; - const xpath_node_set &get_node_set() const; - - // Set variable value; no type conversion is performed, false is returned on - // type mismatch error - bool set(bool value); - bool set(double value); - bool set(const char_t *value); - bool set(const xpath_node_set &value); -}; - -// A set of XPath variables -class PUGIXML_CLASS xpath_variable_set { -private: - xpath_variable *_data[64]; - - void _assign(const xpath_variable_set &rhs); - void _swap(xpath_variable_set &rhs); - - xpath_variable *_find(const char_t *name) const; - - static bool _clone(xpath_variable *var, xpath_variable **out_result); - static void _destroy(xpath_variable *var); - -public: - // Default constructor/destructor - xpath_variable_set(); - ~xpath_variable_set(); - - // Copy constructor/assignment operator - xpath_variable_set(const xpath_variable_set &rhs); - xpath_variable_set &operator=(const xpath_variable_set &rhs); - -#if __cplusplus >= 201103 - // Move semantics support - xpath_variable_set(xpath_variable_set &&rhs); - xpath_variable_set &operator=(xpath_variable_set &&rhs); -#endif - - // Add a new variable or get the existing one, if the types match - xpath_variable *add(const char_t *name, xpath_value_type type); - - // Set value of an existing variable; no type conversion is performed, false - // is returned if there is no such variable or if types mismatch - bool set(const char_t *name, bool value); - bool set(const char_t *name, double value); - bool set(const char_t *name, const char_t *value); - bool set(const char_t *name, const xpath_node_set &value); - - // Get existing variable by name - xpath_variable *get(const char_t *name); - const xpath_variable *get(const char_t *name) const; -}; - -// A compiled XPath query object -class PUGIXML_CLASS xpath_query { -private: - void *_impl; - xpath_parse_result _result; - - typedef void (*unspecified_bool_type)(xpath_query ***); - - // Non-copyable semantics - xpath_query(const xpath_query &); - xpath_query &operator=(const xpath_query &); - -public: - // Construct a compiled object from XPath expression. - // If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on - // compilation errors. - explicit xpath_query(const char_t *query, xpath_variable_set *variables = 0); - - // Constructor - xpath_query(); - - // Destructor - ~xpath_query(); - -#if __cplusplus >= 201103 - // Move semantics support - xpath_query(xpath_query &&rhs); - xpath_query &operator=(xpath_query &&rhs); -#endif - - // Get query expression return type - xpath_value_type return_type() const; - - // Evaluate expression as boolean value in the specified context; performs - // type conversion if necessary. If PUGIXML_NO_EXCEPTIONS is not defined, - // throws std::bad_alloc on out of memory errors. - bool evaluate_boolean(const xpath_node &n) const; - - // Evaluate expression as double value in the specified context; performs type - // conversion if necessary. If PUGIXML_NO_EXCEPTIONS is not defined, throws - // std::bad_alloc on out of memory errors. - double evaluate_number(const xpath_node &n) const; - -#ifndef PUGIXML_NO_STL - // Evaluate expression as string value in the specified context; performs type - // conversion if necessary. If PUGIXML_NO_EXCEPTIONS is not defined, throws - // std::bad_alloc on out of memory errors. - string_t evaluate_string(const xpath_node &n) const; -#endif - - // Evaluate expression as string value in the specified context; performs type - // conversion if necessary. At most capacity characters are written to the - // destination buffer, full result size is returned (includes terminating - // zero). If PUGIXML_NO_EXCEPTIONS is not defined, throws std::bad_alloc on - // out of memory errors. If PUGIXML_NO_EXCEPTIONS is defined, returns empty - // set instead. - size_t evaluate_string(char_t *buffer, size_t capacity, - const xpath_node &n) const; - - // Evaluate expression as node set in the specified context. - // If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on type - // mismatch and std::bad_alloc on out of memory errors. If - // PUGIXML_NO_EXCEPTIONS is defined, returns empty node set instead. - xpath_node_set evaluate_node_set(const xpath_node &n) const; - - // Evaluate expression as node set in the specified context. - // Return first node in document order, or empty node if node set is empty. - // If PUGIXML_NO_EXCEPTIONS is not defined, throws xpath_exception on type - // mismatch and std::bad_alloc on out of memory errors. If - // PUGIXML_NO_EXCEPTIONS is defined, returns empty node instead. - xpath_node evaluate_node(const xpath_node &n) const; - - // Get parsing result (used to get compilation errors in PUGIXML_NO_EXCEPTIONS - // mode) - const xpath_parse_result &result() const; - - // Safe bool conversion operator - operator unspecified_bool_type() const; - - // Borland C++ workaround - bool operator!() const; -}; - -#ifndef PUGIXML_NO_EXCEPTIONS -// XPath exception class -class PUGIXML_CLASS xpath_exception : public std::exception { -private: - xpath_parse_result _result; - -public: - // Construct exception from parse result - explicit xpath_exception(const xpath_parse_result &result); - - // Get error message - virtual const char *what() const throw(); - - // Get parse result - const xpath_parse_result &result() const; -}; -#endif - -// XPath node class (either xml_node or xml_attribute) -class PUGIXML_CLASS xpath_node { -private: - xml_node _node; - xml_attribute _attribute; - - typedef void (*unspecified_bool_type)(xpath_node ***); - -public: - // Default constructor; constructs empty XPath node - xpath_node(); - - // Construct XPath node from XML node/attribute - xpath_node(const xml_node &node); - xpath_node(const xml_attribute &attribute, const xml_node &parent); - - // Get node/attribute, if any - xml_node node() const; - xml_attribute attribute() const; - - // Get parent of contained node/attribute - xml_node parent() const; - - // Safe bool conversion operator - operator unspecified_bool_type() const; - - // Borland C++ workaround - bool operator!() const; - - // Comparison operators - bool operator==(const xpath_node &n) const; - bool operator!=(const xpath_node &n) const; -}; - -#ifdef __BORLANDC__ -// Borland C++ workaround -bool PUGIXML_FUNCTION operator&&(const xpath_node &lhs, bool rhs); -bool PUGIXML_FUNCTION operator||(const xpath_node &lhs, bool rhs); -#endif - -// A fixed-size collection of XPath nodes -class PUGIXML_CLASS xpath_node_set { -public: - // Collection type - enum type_t { - type_unsorted, // Not ordered - type_sorted, // Sorted by document order (ascending) - type_sorted_reverse // Sorted by document order (descending) - }; - - // Constant iterator type - typedef const xpath_node *const_iterator; - - // We define non-constant iterator to be the same as constant iterator so that - // various generic algorithms (i.e. boost foreach) work - typedef const xpath_node *iterator; - - // Default constructor. Constructs empty set. - xpath_node_set(); - - // Constructs a set from iterator range; data is not checked for duplicates - // and is not sorted according to provided type, so be careful - xpath_node_set(const_iterator begin, const_iterator end, - type_t type = type_unsorted); - - // Destructor - ~xpath_node_set(); - - // Copy constructor/assignment operator - xpath_node_set(const xpath_node_set &ns); - xpath_node_set &operator=(const xpath_node_set &ns); - -#if __cplusplus >= 201103 - // Move semantics support - xpath_node_set(xpath_node_set &&rhs); - xpath_node_set &operator=(xpath_node_set &&rhs); -#endif - - // Get collection type - type_t type() const; - - // Get collection size - size_t size() const; - - // Indexing operator - const xpath_node &operator[](size_t index) const; - - // Collection iterators - const_iterator begin() const; - const_iterator end() const; - - // Sort the collection in ascending/descending order by document order - void sort(bool reverse = false); - - // Get first node in the collection by document order - xpath_node first() const; - - // Check if collection is empty - bool empty() const; - -private: - type_t _type; - - xpath_node _storage; - - xpath_node *_begin; - xpath_node *_end; - - void _assign(const_iterator begin, const_iterator end, type_t type); - void _move(xpath_node_set &rhs); -}; -#endif - -#ifndef PUGIXML_NO_STL -// Convert wide string to UTF8 -std::basic_string, std::allocator> - PUGIXML_FUNCTION as_utf8(const wchar_t *str); -std::basic_string, std::allocator> - PUGIXML_FUNCTION - as_utf8(const std::basic_string, - std::allocator> &str); - -// Convert UTF8 to wide string -std::basic_string, std::allocator> - PUGIXML_FUNCTION as_wide(const char *str); -std::basic_string, std::allocator> - PUGIXML_FUNCTION - as_wide(const std::basic_string, - std::allocator> &str); -#endif - -// Memory allocation function interface; returns pointer to allocated memory or -// NULL on failure -typedef void *(*allocation_function)(size_t size); - -// Memory deallocation function interface -typedef void (*deallocation_function)(void *ptr); - -// Override default memory management functions. All subsequent -// allocations/deallocations will be performed via supplied functions. -void PUGIXML_FUNCTION set_memory_management_functions( - allocation_function allocate, deallocation_function deallocate); - -// Get current memory management functions -allocation_function PUGIXML_FUNCTION get_memory_allocation_function(); -deallocation_function PUGIXML_FUNCTION get_memory_deallocation_function(); -} // namespace pugi - -#if !defined(PUGIXML_NO_STL) && (defined(_MSC_VER) || defined(__ICC)) -namespace std { -// Workarounds for (non-standard) iterator category detection for older versions -// (MSVC7/IC8 and earlier) -std::bidirectional_iterator_tag PUGIXML_FUNCTION -_Iter_cat(const pugi::xml_node_iterator &); -std::bidirectional_iterator_tag PUGIXML_FUNCTION -_Iter_cat(const pugi::xml_attribute_iterator &); -std::bidirectional_iterator_tag PUGIXML_FUNCTION -_Iter_cat(const pugi::xml_named_node_iterator &); -} // namespace std -#endif - -#if !defined(PUGIXML_NO_STL) && defined(__SUNPRO_CC) -namespace std { -// Workarounds for (non-standard) iterator category detection -std::bidirectional_iterator_tag PUGIXML_FUNCTION -__iterator_category(const pugi::xml_node_iterator &); -std::bidirectional_iterator_tag PUGIXML_FUNCTION -__iterator_category(const pugi::xml_attribute_iterator &); -std::bidirectional_iterator_tag PUGIXML_FUNCTION -__iterator_category(const pugi::xml_named_node_iterator &); -} // namespace std -#endif - -#endif - -// Make sure implementation is included in header-only mode -// Use macro expansion in #include to work around QMake (QTBUG-11923) -#if defined(PUGIXML_HEADER_ONLY) && !defined(PUGIXML_SOURCE) -#define PUGIXML_SOURCE "pugixml.cpp" -#include PUGIXML_SOURCE -#endif - -/** - * Copyright (c) 2006-2015 Arseny Kapoulkine - * - * Permission is hereby granted, free of charge, to any person - * obtaining a copy of this software and associated documentation - * files (the "Software"), to deal in the Software without - * restriction, including without limitation the rights to use, - * copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following - * conditions: - * - * The above copyright notice and this permission notice shall be - * included in all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, - * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES - * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND - * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT - * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, - * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING - * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - */ diff --git a/techlibs/rapidflex/util/pcnt_cell_sim_gen.py b/techlibs/rapidflex/util/pcnt_cell_sim_gen.py index 85b7e6922..2670d2d83 100644 --- a/techlibs/rapidflex/util/pcnt_cell_sim_gen.py +++ b/techlibs/rapidflex/util/pcnt_cell_sim_gen.py @@ -16,7 +16,7 @@ error_codes = {"SUCCESS": 0, "ERROR": 1, "FILE_ERROR": 3} ##################################################################### # Initialize logger ##################################################################### -logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.INFO) +logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.ERROR) def generate_file_header(f0): From 4973d135a22f97ef998cc325381b6a5f75cfbea2 Mon Sep 17 00:00:00 2001 From: treelin611 Date: Wed, 20 May 2026 15:12:40 +0800 Subject: [PATCH 09/15] fix compile bug --- techlibs/rapidflex/src/rf_new_dsp.pmg | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/rapidflex/src/rf_new_dsp.pmg b/techlibs/rapidflex/src/rf_new_dsp.pmg index 5f4f58337..af97ce1ce 100644 --- a/techlibs/rapidflex/src/rf_new_dsp.pmg +++ b/techlibs/rapidflex/src/rf_new_dsp.pmg @@ -368,7 +368,7 @@ match ff filter GetSize(port(ff, \Q)) >= offset + GetSize(argQ) filter port(ff, \Q).extract(offset, GetSize(argQ)) == argQ - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ @@ -406,7 +406,7 @@ match ff filter GetSize(port(ff, \D)) >= offset + GetSize(argD) filter port(ff, \D).extract(offset, GetSize(argD)) == argD - filter clock == SigBit() || port(ff, \CLK) == clock + filter clock == SigBit() || port(ff, \CLK)[0] == clock endmatch code argQ From 90d3d694cfba1871e1fe82c0c942faac9458fea3 Mon Sep 17 00:00:00 2001 From: JR Lin <145083116+treelin611@users.noreply.github.com> Date: Fri, 22 May 2026 10:35:32 +0800 Subject: [PATCH 10/15] Update techlibs/rapidflex/src/synth_rapidflex.cc Co-authored-by: Lofty --- techlibs/rapidflex/src/synth_rapidflex.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/rapidflex/src/synth_rapidflex.cc b/techlibs/rapidflex/src/synth_rapidflex.cc index 498e860e4..b143b1e45 100644 --- a/techlibs/rapidflex/src/synth_rapidflex.cc +++ b/techlibs/rapidflex/src/synth_rapidflex.cc @@ -245,7 +245,7 @@ struct SynthRapidFlexPass : public ScriptPass { } /* By default, no opt should be enabled. Throw a warning if not */ if (no_opt) { - log_warning("Force to disable any optimization, which may cast an " + log_warning("Disabling optimization, which may have a " "negative impact on QoR\n"); } if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { From b02e23fbad048d0feeebe2dece4a16207026b09d Mon Sep 17 00:00:00 2001 From: JR Lin <145083116+treelin611@users.noreply.github.com> Date: Fri, 22 May 2026 10:35:56 +0800 Subject: [PATCH 11/15] Update techlibs/rapidflex/src/synth_rapidflex.cc log Co-authored-by: Lofty --- techlibs/rapidflex/src/synth_rapidflex.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/rapidflex/src/synth_rapidflex.cc b/techlibs/rapidflex/src/synth_rapidflex.cc index b143b1e45..29abbe371 100644 --- a/techlibs/rapidflex/src/synth_rapidflex.cc +++ b/techlibs/rapidflex/src/synth_rapidflex.cc @@ -233,7 +233,7 @@ struct SynthRapidFlexPass : public ScriptPass { /* Force to enable/disable options upon device limits */ if (family == ALKDL_DNAME || family == ALKDC_DNAME) { if (!nodsp) { - log_warning("Force to disable dsp inference as the selected device " + log_warning("Disabling DSP inference as the selected device " "does not contain dedicated resources\n"); nodsp = true; } From c3785eb2de5d0d8d78a921eab2d72ee7378511a6 Mon Sep 17 00:00:00 2001 From: JR Lin <145083116+treelin611@users.noreply.github.com> Date: Fri, 22 May 2026 10:36:13 +0800 Subject: [PATCH 12/15] Update techlibs/rapidflex/src/synth_rapidflex.cc log Co-authored-by: Lofty --- techlibs/rapidflex/src/synth_rapidflex.cc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/techlibs/rapidflex/src/synth_rapidflex.cc b/techlibs/rapidflex/src/synth_rapidflex.cc index 29abbe371..a4cca763e 100644 --- a/techlibs/rapidflex/src/synth_rapidflex.cc +++ b/techlibs/rapidflex/src/synth_rapidflex.cc @@ -238,7 +238,7 @@ struct SynthRapidFlexPass : public ScriptPass { nodsp = true; } if (inferBram) { - log_warning("Force to disable RAM inference as the selected device " + log_warning("Disabling RAM inference as the selected device " "does not contain dedicated resources\n"); inferBram = false; } From 7a9a01ff8ead3c360536f45574ee39836fc84444 Mon Sep 17 00:00:00 2001 From: treelin611 Date: Fri, 22 May 2026 10:38:31 +0800 Subject: [PATCH 13/15] delete redundant .ys files --- techlibs/rapidflex/alkaidC/synth.ys | 128 ------------------ techlibs/rapidflex/alkaidC/synth_no_adder.ys | 128 ------------------ techlibs/rapidflex/alkaidC/verilog_rewrite.ys | 41 ------ 3 files changed, 297 deletions(-) delete mode 100644 techlibs/rapidflex/alkaidC/synth.ys delete mode 100644 techlibs/rapidflex/alkaidC/synth_no_adder.ys delete mode 100644 techlibs/rapidflex/alkaidC/verilog_rewrite.ys diff --git a/techlibs/rapidflex/alkaidC/synth.ys b/techlibs/rapidflex/alkaidC/synth.ys deleted file mode 100644 index 4844ccf0b..000000000 --- a/techlibs/rapidflex/alkaidC/synth.ys +++ /dev/null @@ -1,128 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt -nodffe - -opt_expr -opt_clean -check -opt -nodffe -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -#memory_dff -#wreduce t:$mul -#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -#select a:mul2dsp -#setattr -unset mul2dsp -#opt_expr -fine -#wreduce -#select -clear -#chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -alumacc -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#opt -fast -nodffe -#opt_expr -#opt_merge -#opt_clean -#opt -nodffe -#share -#opt -nodffe -#fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -#opt -fast -nodffe -opt -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -#techmap -map ${YOSYS_BRAM_MAP_VERILOG} -#opt -fast -mux_undef -undriven -fine -nodffe -#memory_map -#opt -undriven -fine -nodffe - -######################## -# Map Adders -techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -opt -fast -nodffe -opt_expr -opt_merge -opt_clean -opt -nodffe - -######################### -# Map flip-flops -######################### -memory -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_dff -nodffe -opt_clean -opt -nodffe - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} -# Map dff again since ABC may generate some new FFs -techmap -map ${YOSYS_DFF_MAP_VERILOG} -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} -write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidC/synth_no_adder.ys b/techlibs/rapidflex/alkaidC/synth_no_adder.ys deleted file mode 100644 index bef3c7dc5..000000000 --- a/techlibs/rapidflex/alkaidC/synth_no_adder.ys +++ /dev/null @@ -1,128 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt -nodffe - -opt_expr -opt_clean -check -opt -nodffe -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -#memory_dff -#wreduce t:$mul -#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -#select a:mul2dsp -#setattr -unset mul2dsp -#opt_expr -fine -#wreduce -#select -clear -#chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -alumacc -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#opt -fast -nodffe -#opt_expr -#opt_merge -#opt_clean -#opt -nodffe -#share -#opt -nodffe -#fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -#opt -fast -nodffe -opt -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -#techmap -map ${YOSYS_BRAM_MAP_VERILOG} -#opt -fast -mux_undef -undriven -fine -nodffe -#memory_map -#opt -undriven -fine -nodffe - -######################## -# Map Adders -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#opt -fast -nodffe -#opt_expr -#opt_merge -#opt_clean -#opt -nodffe - -######################### -# Map flip-flops -######################### -memory -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_dff -nodffe -opt_clean -opt -nodffe - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} -# Map dff again since ABC may generate some new FFs -techmap -map ${YOSYS_DFF_MAP_VERILOG} -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} -write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidC/verilog_rewrite.ys b/techlibs/rapidflex/alkaidC/verilog_rewrite.ys deleted file mode 100644 index 217e8d558..000000000 --- a/techlibs/rapidflex/alkaidC/verilog_rewrite.ys +++ /dev/null @@ -1,41 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} - -# Technology mapping -hierarchy -top ${TOP_MODULE} -proc -techmap -D NO_LUT -map +/adff2dff.v - -# Synthesis -flatten -opt_expr -opt_clean -check -opt -nodffe -nosdff -fsm -opt -nodffe -nosdff -wreduce -peepopt -opt_clean -opt -nodffe -nosdff -memory -nomap -opt_clean -opt -fast -full -nodffe -nosdff -memory_map -opt -full -nodffe -nosdff -techmap -opt -fast -nodffe -nosdff -clean - -clean - -# LUT mapping -abc -lut ${LUT_SIZE} - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_verilog ${OUTPUT_VERILOG} From 0f8477d2bf2304b45b866986b5d8daba731c0eb6 Mon Sep 17 00:00:00 2001 From: treelin611 Date: Thu, 28 May 2026 14:16:46 +0800 Subject: [PATCH 14/15] rename pass --- techlibs/rapidflex/src/clock_buffer_cmd.cc | 6 +++--- techlibs/rapidflex/src/synth_rapidflex.cc | 10 +++++++--- 2 files changed, 10 insertions(+), 6 deletions(-) diff --git a/techlibs/rapidflex/src/clock_buffer_cmd.cc b/techlibs/rapidflex/src/clock_buffer_cmd.cc index 72536c2d8..5f642fb70 100644 --- a/techlibs/rapidflex/src/clock_buffer_cmd.cc +++ b/techlibs/rapidflex/src/clock_buffer_cmd.cc @@ -15,7 +15,7 @@ PRIVATE_NAMESPACE_BEGIN struct InsertClockBuffer : public Pass { InsertClockBuffer() - : Pass("insert_clock_buffer", + : Pass("rapidflex_insert_clock_buffer", "This command is to insert clock buffer into the design") {} /*utility function used by insert_ckbuff; copied from blif.cc*/ @@ -519,7 +519,7 @@ struct InsertClockBuffer : public Pass { } void execute(std::vector args, RTLIL::Design *design) override { - log("Arguments to the command insert_clock_buffer:\n"); + log("Arguments to the command rapidflex_insert_clock_buffer:\n"); std::string top_module_name; std::string cell_map_file; for (size_t i = 0; i < args.size(); i++) { @@ -576,6 +576,6 @@ struct InsertClockBuffer : public Pass { } design->check(); } -} Insert_clock_buffer; +} rapidflex_insert_clock_buffer; PRIVATE_NAMESPACE_END diff --git a/techlibs/rapidflex/src/synth_rapidflex.cc b/techlibs/rapidflex/src/synth_rapidflex.cc index a4cca763e..4d38cfa89 100644 --- a/techlibs/rapidflex/src/synth_rapidflex.cc +++ b/techlibs/rapidflex/src/synth_rapidflex.cc @@ -1,4 +1,4 @@ -/* +/* * Copyright 2020-2024 RapidFlex */ #include "kernel/celltypes.h" @@ -476,8 +476,12 @@ struct SynthRapidFlexPass : public ScriptPass { if (check_label("insert_clock_buffer", "(if -insert_clock_buffer)")) { if (insert_clock_buffer) { - run(stringf("insert_clock_buffer -top %s -cell_map_file %s", - top_opt.c_str(), cell_map_file.c_str())); + if (top_opt == "-auto-top") + run(stringf("rapidflex_insert_clock_buffer -cell_map_file %s", + cell_map_file.c_str())); + else + run(stringf("rapidflex_insert_clock_buffer %s -cell_map_file %s", + top_opt.c_str(), cell_map_file.c_str())); } } From a49a35ae7b04168df28ce61513000f19080a3a09 Mon Sep 17 00:00:00 2001 From: treelin611 Date: Thu, 28 May 2026 14:19:11 +0800 Subject: [PATCH 15/15] delete redundant ys files --- techlibs/rapidflex/alkaidL/synth.ys | 128 ------------------ techlibs/rapidflex/alkaidL/synth_no_adder.ys | 128 ------------------ techlibs/rapidflex/alkaidL/verilog_rewrite.ys | 41 ------ techlibs/rapidflex/alkaidT/synth.ys | 123 ----------------- techlibs/rapidflex/alkaidT/verilog_rewrite.ys | 41 ------ 5 files changed, 461 deletions(-) delete mode 100644 techlibs/rapidflex/alkaidL/synth.ys delete mode 100644 techlibs/rapidflex/alkaidL/synth_no_adder.ys delete mode 100644 techlibs/rapidflex/alkaidL/verilog_rewrite.ys delete mode 100644 techlibs/rapidflex/alkaidT/synth.ys delete mode 100644 techlibs/rapidflex/alkaidT/verilog_rewrite.ys diff --git a/techlibs/rapidflex/alkaidL/synth.ys b/techlibs/rapidflex/alkaidL/synth.ys deleted file mode 100644 index 4844ccf0b..000000000 --- a/techlibs/rapidflex/alkaidL/synth.ys +++ /dev/null @@ -1,128 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt -nodffe - -opt_expr -opt_clean -check -opt -nodffe -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -#memory_dff -#wreduce t:$mul -#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -#select a:mul2dsp -#setattr -unset mul2dsp -#opt_expr -fine -#wreduce -#select -clear -#chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -alumacc -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#opt -fast -nodffe -#opt_expr -#opt_merge -#opt_clean -#opt -nodffe -#share -#opt -nodffe -#fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -#opt -fast -nodffe -opt -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -#techmap -map ${YOSYS_BRAM_MAP_VERILOG} -#opt -fast -mux_undef -undriven -fine -nodffe -#memory_map -#opt -undriven -fine -nodffe - -######################## -# Map Adders -techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -opt -fast -nodffe -opt_expr -opt_merge -opt_clean -opt -nodffe - -######################### -# Map flip-flops -######################### -memory -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_dff -nodffe -opt_clean -opt -nodffe - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} -# Map dff again since ABC may generate some new FFs -techmap -map ${YOSYS_DFF_MAP_VERILOG} -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} -write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidL/synth_no_adder.ys b/techlibs/rapidflex/alkaidL/synth_no_adder.ys deleted file mode 100644 index bef3c7dc5..000000000 --- a/techlibs/rapidflex/alkaidL/synth_no_adder.ys +++ /dev/null @@ -1,128 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt -nodffe - -opt_expr -opt_clean -check -opt -nodffe -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -#memory_dff -#wreduce t:$mul -#techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -#select a:mul2dsp -#setattr -unset mul2dsp -#opt_expr -fine -#wreduce -#select -clear -#chtype -set $mul t:$__soft_mul# Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -alumacc -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#opt -fast -nodffe -#opt_expr -#opt_merge -#opt_clean -#opt -nodffe -#share -#opt -nodffe -#fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -#opt -fast -nodffe -opt -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -#memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -#techmap -map ${YOSYS_BRAM_MAP_VERILOG} -#opt -fast -mux_undef -undriven -fine -nodffe -#memory_map -#opt -undriven -fine -nodffe - -######################## -# Map Adders -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#opt -fast -nodffe -#opt_expr -#opt_merge -#opt_clean -#opt -nodffe - -######################### -# Map flip-flops -######################### -memory -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_dff -nodffe -opt_clean -opt -nodffe - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} -# Map dff again since ABC may generate some new FFs -techmap -map ${YOSYS_DFF_MAP_VERILOG} -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} -write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidL/verilog_rewrite.ys b/techlibs/rapidflex/alkaidL/verilog_rewrite.ys deleted file mode 100644 index 217e8d558..000000000 --- a/techlibs/rapidflex/alkaidL/verilog_rewrite.ys +++ /dev/null @@ -1,41 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} - -# Technology mapping -hierarchy -top ${TOP_MODULE} -proc -techmap -D NO_LUT -map +/adff2dff.v - -# Synthesis -flatten -opt_expr -opt_clean -check -opt -nodffe -nosdff -fsm -opt -nodffe -nosdff -wreduce -peepopt -opt_clean -opt -nodffe -nosdff -memory -nomap -opt_clean -opt -fast -full -nodffe -nosdff -memory_map -opt -full -nodffe -nosdff -techmap -opt -fast -nodffe -nosdff -clean - -clean - -# LUT mapping -abc -lut ${LUT_SIZE} - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_verilog ${OUTPUT_VERILOG} diff --git a/techlibs/rapidflex/alkaidT/synth.ys b/techlibs/rapidflex/alkaidT/synth.ys deleted file mode 100644 index d600a87f5..000000000 --- a/techlibs/rapidflex/alkaidT/synth.ys +++ /dev/null @@ -1,123 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} - -######################### -# Parse input files -######################### -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} -# Read technology library -read_verilog -lib -specify ${YOSYS_CELL_SIM_VERILOG} - -######################### -# Prepare for synthesis -######################### -# Identify top module from hierarchy -hierarchy -check -top ${TOP_MODULE} -# - Convert process blocks to AST -proc -# Flatten all the gates/primitives -flatten -# Identify tri-state buffers from 'z' signal in AST -# with follow-up optimizations to clean up AST -tribuf -logic -opt_expr -opt_clean -# demote inout ports to input or output port -# with follow-up optimizations to clean up AST -deminout -opt -nodffe - -opt_expr -opt_clean -check -opt -nodffe -wreduce -keepdc -peepopt -pmuxtree -opt_clean - -######################## -# Map multipliers -# Inspired from synth_xilinx.cc -######################### -# Avoid merging any registers into DSP, reserve memory port registers first -memory_dff -wreduce t:$mul -techmap -map +/mul2dsp.v -map ${YOSYS_DSP_MAP_VERILOG} ${YOSYS_DSP_MAP_PARAMETERS} -select a:mul2dsp -setattr -unset mul2dsp -opt_expr -fine -wreduce -select -clear -chtype -set $mul t:$__soft_mul # Extract arithmetic functions - -######################### -# Run coarse synthesis -######################### -# Run a tech map with default library -alumacc -opt -#techmap -map +/techmap.v -map ${YOSYS_ADDER_MAP_VERILOG} -#share -#opt -nodffe -#fsm -# Run a quick follow-up optimization to sweep out unused nets/signals -#opt -fast -nodffe -# Optimize any memory cells by merging share-able ports and collecting all the ports belonging to memorcy cells -memory -nomap -opt_clean - -######################### -# Map logics to BRAMs -######################### -memory_bram -rules ${YOSYS_BRAM_MAP_RULES} -techmap -map ${YOSYS_BRAM_MAP_VERILOG} -opt -fast -mux_undef -undriven -fine -nodffe -memory_map -opt -undriven -fine -nodffe - -######################## -# Map Adders -#techmap -map +/techmap.v -map ${YOSYS_ADDER_AVG_MAP_VERILOG} -opt -fast -nodffe -opt_expr -opt_merge -opt_clean -opt -nodffe - -######################### -# Map flip-flops -######################### -memory -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_???_ 01 -cell $_SDFF_???_ 01 -techmap -map +/techmap.v -map ${YOSYS_DFF_MAP_VERILOG} -opt_expr -mux_undef -simplemap -opt_expr -opt_merge -opt_dff -nodffe -opt_clean -opt -nodffe - -######################### -# Map LUTs -######################### -abc -lut ${LUT_SIZE} -# Map dff again since ABC may generate some new FFs -techmap -map ${YOSYS_DFF_MAP_VERILOG} -techmap -map ${YOSYS_ADDER_MAP_VERILOG} - -######################### -# Check and show statisitics -######################### -hierarchy -check -stat - -######################### -# Output netlists -######################### -opt_clean -purge -write_blif ${OUTPUT_BLIF} -write_verilog ${TOP_MODULE}_post_synth.v diff --git a/techlibs/rapidflex/alkaidT/verilog_rewrite.ys b/techlibs/rapidflex/alkaidT/verilog_rewrite.ys deleted file mode 100644 index 217e8d558..000000000 --- a/techlibs/rapidflex/alkaidT/verilog_rewrite.ys +++ /dev/null @@ -1,41 +0,0 @@ -# Yosys synthesis script for ${TOP_MODULE} -# Read verilog files -read_verilog ${READ_VERILOG_OPTIONS} ${VERILOG_FILES} - -# Technology mapping -hierarchy -top ${TOP_MODULE} -proc -techmap -D NO_LUT -map +/adff2dff.v - -# Synthesis -flatten -opt_expr -opt_clean -check -opt -nodffe -nosdff -fsm -opt -nodffe -nosdff -wreduce -peepopt -opt_clean -opt -nodffe -nosdff -memory -nomap -opt_clean -opt -fast -full -nodffe -nosdff -memory_map -opt -full -nodffe -nosdff -techmap -opt -fast -nodffe -nosdff -clean - -clean - -# LUT mapping -abc -lut ${LUT_SIZE} - -# Check -synth -run check - -# Clean and output blif -opt_clean -purge -write_verilog ${OUTPUT_VERILOG}