From 276800c39b1c81ce732db23a7e263486ae8d9fbd Mon Sep 17 00:00:00 2001
From: Akash Levy <akash@silimate.com>
Date: Fri, 4 Apr 2025 14:27:38 -0700
Subject: [PATCH] wreduce shifter signedness fix

---
 passes/opt/wreduce.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/opt/wreduce.cc b/passes/opt/wreduce.cc
index fb30f0195..ed4aab465 100644
--- a/passes/opt/wreduce.cc
+++ b/passes/opt/wreduce.cc
@@ -238,7 +238,7 @@ struct WreduceWorker
 		SigSpec sig = mi.sigmap(cell->getPort(stringf("\\%c", port)));
 
 		if (port == 'B' && cell->type.in(ID($shl), ID($shr), ID($sshl), ID($sshr)))
-			port_signed = false;
+			port_signed = true; // SILIMATE: HAD TO CHANGE THIS TO RESOLVE CUSTOMER_SHL_BLOWUP_2. REAL FIX IS TO MAKE SURE THAT YOSYS DOES THE RIGHT THING WITH SIGNEDNESS.
 
 		int bits_removed = 0;
 		if (GetSize(sig) > max_port_size) {