From 23cfeabfe16ba363c7a4cbceac9d2e45e2d69691 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 27 Mar 2026 08:42:38 +0100 Subject: [PATCH 1/2] Update ABC as per 2026-03-27 --- abc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/abc b/abc index b4a657e75..de0ebae1c 160000 --- a/abc +++ b/abc @@ -1 +1 @@ -Subproject commit b4a657e75b16b68c514a7326642ea074f8460939 +Subproject commit de0ebae1c5ddbb345871c2e3c4c2a99c9c881ad2 From 417e871b06baf709a8de4a66e9eab890a8f9d041 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Fri, 27 Mar 2026 09:44:19 +0100 Subject: [PATCH 2/2] Fix tests due to ABC improvements --- tests/arch/analogdevices/logic.ys | 5 ++--- tests/arch/analogdevices/mux.ys | 6 ++---- tests/arch/ecp5/add_sub.ys | 8 +++----- tests/arch/ecp5/lutram.ys | 7 +++---- tests/arch/gowin/logic.ys | 4 ++-- tests/arch/gowin/mux.ys | 19 +++++++------------ tests/arch/intel_alm/logic.ys | 4 ++-- tests/arch/nexus/add_sub.ys | 4 ++-- tests/pyosys/test_design_run_pass.py | 8 +++----- tests/pyosys/test_ecp5_addsub.py | 8 +++----- 10 files changed, 29 insertions(+), 44 deletions(-) diff --git a/tests/arch/analogdevices/logic.ys b/tests/arch/analogdevices/logic.ys index 9314c7825..2289685ac 100644 --- a/tests/arch/analogdevices/logic.ys +++ b/tests/arch/analogdevices/logic.ys @@ -6,6 +6,5 @@ design -load postopt # load the post-opt design (otherwise equiv_opt loads the p cd top # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 -select -assert-count 6 t:LUT2 -select -assert-count 2 t:LUT4 -select -assert-none t:LUT1 t:LUT2 t:LUT4 %% t:* %D +select -assert-count 9 t:LUT2 +select -assert-none t:LUT1 t:LUT2 %% t:* %D diff --git a/tests/arch/analogdevices/mux.ys b/tests/arch/analogdevices/mux.ys index 375ce90f2..3244b0dc3 100644 --- a/tests/arch/analogdevices/mux.ys +++ b/tests/arch/analogdevices/mux.ys @@ -41,10 +41,8 @@ equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux16 # Constrain all select calls below inside the top module select -assert-max 2 t:LUT3 -select -assert-max 2 t:LUT4 +select -assert-max 1 t:LUT5 select -assert-min 4 t:LUT6 -select -assert-max 7 t:LUT6 -select -assert-max 2 t:LUTMUX7 dump -select -assert-none t:LUT6 t:LUT4 t:LUT3 t:LUTMUX7 %% t:* %D +select -assert-none t:LUT6 t:LUT5 t:LUT3 %% t:* %D diff --git a/tests/arch/ecp5/add_sub.ys b/tests/arch/ecp5/add_sub.ys index c3ce8c56d..9c3c03499 100644 --- a/tests/arch/ecp5/add_sub.ys +++ b/tests/arch/ecp5/add_sub.ys @@ -4,9 +4,7 @@ proc equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module -select -assert-min 25 t:LUT4 -select -assert-max 26 t:LUT4 -select -assert-count 10 t:PFUMX -select -assert-count 6 t:L6MUX21 -select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D +select -assert-min 11 t:LUT4 +select -assert-count 2 t:PFUMX +select -assert-none t:LUT4 t:PFUMX %% t:* %D diff --git a/tests/arch/ecp5/lutram.ys b/tests/arch/ecp5/lutram.ys index 9bef37c68..e83890a54 100644 --- a/tests/arch/ecp5/lutram.ys +++ b/tests/arch/ecp5/lutram.ys @@ -11,9 +11,8 @@ sat -verify -prove-asserts -seq 5 -set-init-zero -show-inputs -show-outputs mite design -load postopt cd lutram_1w1r -select -assert-count 8 t:L6MUX21 -select -assert-count 36 t:LUT4 -select -assert-count 16 t:PFUMX +select -assert-count 28 t:LUT4 +select -assert-count 8 t:PFUMX select -assert-count 8 t:TRELLIS_DPR16X4 select -assert-count 8 t:TRELLIS_FF -select -assert-none t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D +select -assert-none t:LUT4 t:PFUMX t:TRELLIS_DPR16X4 t:TRELLIS_FF %% t:* %D diff --git a/tests/arch/gowin/logic.ys b/tests/arch/gowin/logic.ys index d2b9e4540..15f050e9b 100644 --- a/tests/arch/gowin/logic.ys +++ b/tests/arch/gowin/logic.ys @@ -7,7 +7,7 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:LUT1 select -assert-count 6 t:LUT2 -select -assert-count 2 t:LUT4 +select -assert-count 2 t:LUT3 select -assert-count 8 t:IBUF select -assert-count 10 t:OBUF -select -assert-none t:LUT1 t:LUT2 t:LUT4 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT1 t:LUT2 t:LUT3 t:IBUF t:OBUF %% t:* %D diff --git a/tests/arch/gowin/mux.ys b/tests/arch/gowin/mux.ys index 2ca973520..fddf91d0e 100644 --- a/tests/arch/gowin/mux.ys +++ b/tests/arch/gowin/mux.ys @@ -18,13 +18,12 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux4 # Constrain all select calls below inside the top module -select -assert-count 4 t:LUT* -select -assert-count 2 t:MUX2_LUT5 -select -assert-count 1 t:MUX2_LUT6 +select -assert-count 3 t:LUT* +select -assert-count 1 t:MUX2_LUT5 select -assert-count 6 t:IBUF select -assert-count 1 t:OBUF -select -assert-none t:LUT* t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D +select -assert-none t:LUT* t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux8 @@ -32,17 +31,13 @@ proc equiv_opt -assert -map +/gowin/cells_sim.v synth_gowin # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd mux8 # Constrain all select calls below inside the top module -select -assert-count 3 t:LUT1 -select -assert-count 2 t:LUT3 -select -assert-count 1 t:LUT4 -select -assert-count 5 t:MUX2_LUT5 -select -assert-count 2 t:MUX2_LUT6 -select -assert-count 1 t:MUX2_LUT7 +select -assert-count 1 t:LUT3 +select -assert-count 5 t:LUT4 +select -assert-count 1 t:MUX2_LUT5 select -assert-count 11 t:IBUF select -assert-count 1 t:OBUF -select -assert-count 1 t:GND -select -assert-none t:LUT* t:MUX2_LUT7 t:MUX2_LUT6 t:MUX2_LUT5 t:IBUF t:OBUF t:GND %% t:* %D +select -assert-none t:LUT* t:MUX2_LUT5 t:IBUF t:OBUF %% t:* %D design -load read hierarchy -top mux16 diff --git a/tests/arch/intel_alm/logic.ys b/tests/arch/intel_alm/logic.ys index 831f9f174..91d6043e0 100644 --- a/tests/arch/intel_alm/logic.ys +++ b/tests/arch/intel_alm/logic.ys @@ -7,6 +7,6 @@ cd top # Constrain all select calls below inside the top module select -assert-count 1 t:MISTRAL_NOT select -assert-count 6 t:MISTRAL_ALUT2 -select -assert-count 2 t:MISTRAL_ALUT4 -select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT4 %% t:* %D +select -assert-count 2 t:MISTRAL_ALUT3 +select -assert-none t:MISTRAL_NOT t:MISTRAL_ALUT2 t:MISTRAL_ALUT3 %% t:* %D diff --git a/tests/arch/nexus/add_sub.ys b/tests/arch/nexus/add_sub.ys index 4317bab81..c1599c57e 100644 --- a/tests/arch/nexus/add_sub.ys +++ b/tests/arch/nexus/add_sub.ys @@ -16,6 +16,6 @@ equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module stat -select -assert-count 6 t:LUT4 -select -assert-count 4 t:WIDEFN9 +select -assert-count 7 t:LUT4 +select -assert-count 2 t:WIDEFN9 select -assert-none t:IB t:OB t:VLO t:LUT4 t:WIDEFN9 %% t:* %D diff --git a/tests/pyosys/test_design_run_pass.py b/tests/pyosys/test_design_run_pass.py index f0013577d..6e31a7f1c 100644 --- a/tests/pyosys/test_design_run_pass.py +++ b/tests/pyosys/test_design_run_pass.py @@ -13,8 +13,6 @@ base.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5") postopt = ys.Design() postopt.run_pass("design -load postopt") postopt.run_pass(["cd", "top"]) -postopt.run_pass("select -assert-min 25 t:LUT4") -postopt.run_pass("select -assert-max 26 t:LUT4") -postopt.run_pass(["select", "-assert-count", "10", "t:PFUMX"]) -postopt.run_pass(["select", "-assert-count", "6", "t:L6MUX21"]) -postopt.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D") +postopt.run_pass("select -assert-min 11 t:LUT4") +postopt.run_pass(["select", "-assert-count", "2", "t:PFUMX"]) +postopt.run_pass("select -assert-none t:LUT4 t:PFUMX %% t:* %D") diff --git a/tests/pyosys/test_ecp5_addsub.py b/tests/pyosys/test_ecp5_addsub.py index ddc50b775..96258e3ba 100644 --- a/tests/pyosys/test_ecp5_addsub.py +++ b/tests/pyosys/test_ecp5_addsub.py @@ -13,8 +13,6 @@ ys.run_pass("equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5", base) postopt = ys.Design() ys.run_pass("design -load postopt", postopt) ys.run_pass("cd top", postopt) -ys.run_pass("select -assert-min 25 t:LUT4", postopt) -ys.run_pass("select -assert-max 26 t:LUT4", postopt) -ys.run_pass("select -assert-count 10 t:PFUMX", postopt) -ys.run_pass("select -assert-count 6 t:L6MUX21", postopt) -ys.run_pass("select -assert-none t:LUT4 t:PFUMX t:L6MUX21 %% t:* %D", postopt) +ys.run_pass("select -assert-min 11 t:LUT4", postopt) +ys.run_pass("select -assert-count 2 t:PFUMX", postopt) +ys.run_pass("select -assert-none t:LUT4 t:PFUMX %% t:* %D", postopt)