diff --git a/Makefile b/Makefile
index d4b17b2cb..3aac18ccc 100644
--- a/Makefile
+++ b/Makefile
@@ -177,7 +177,7 @@ ifeq ($(OS), Haiku)
 CXXFLAGS += -D_DEFAULT_SOURCE
 endif
 
-YOSYS_VER := 0.60+51
+YOSYS_VER := 0.60+64
 YOSYS_MAJOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f1)
 YOSYS_MINOR := $(shell echo $(YOSYS_VER) | cut -d'.' -f2)
 YOSYS_COMMIT := $(shell echo $(YOSYS_VER) | cut -d'.' -f3)
diff --git a/abc b/abc
index bd05a6454..9182a8048 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit bd05a6454e8c157caaa58ceda676ae0249d8e27c
+Subproject commit 9182a8048d0bc86b39a6cb6b0488a7e1d10b2607
diff --git a/backends/cxxrtl/cxxrtl_backend.cc b/backends/cxxrtl/cxxrtl_backend.cc
index d575b5879..71913d2db 100644
--- a/backends/cxxrtl/cxxrtl_backend.cc
+++ b/backends/cxxrtl/cxxrtl_backend.cc
@@ -756,7 +756,7 @@ struct CxxrtlWorker {
 	//  1b. Generated identifiers for internal names (beginning with `$`) start with `i_`.
 	//  2. An underscore is escaped with another underscore, i.e. `__`.
 	//  3. Any other non-alnum character is escaped with underscores around its lowercase hex code, e.g. `@` as `_40_`.
-	std::string mangle_name(const RTLIL::IdString &name)
+	std::string mangle_name(RTLIL::IdString name)
 	{
 		std::string mangled;
 		bool first = true;
@@ -786,7 +786,7 @@ struct CxxrtlWorker {
 		return mangled;
 	}
 
-	std::string mangle_module_name(const RTLIL::IdString &name, bool is_blackbox = false)
+	std::string mangle_module_name(RTLIL::IdString name, bool is_blackbox = false)
 	{
 		// Class namespace.
 		if (is_blackbox)
@@ -794,19 +794,19 @@ struct CxxrtlWorker {
 		return mangle_name(name);
 	}
 
-	std::string mangle_memory_name(const RTLIL::IdString &name)
+	std::string mangle_memory_name(RTLIL::IdString name)
 	{
 		// Class member namespace.
 		return "memory_" + mangle_name(name);
 	}
 
-	std::string mangle_cell_name(const RTLIL::IdString &name)
+	std::string mangle_cell_name(RTLIL::IdString name)
 	{
 		// Class member namespace.
 		return "cell_" + mangle_name(name);
 	}
 
-	std::string mangle_wire_name(const RTLIL::IdString &name)
+	std::string mangle_wire_name(RTLIL::IdString name)
 	{
 		// Class member namespace.
 		return mangle_name(name);
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index c26750c98..86ea70b51 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -844,6 +844,7 @@ struct AST_INTERNAL::ProcessGenerator
 
 				RTLIL::Cell *cell = current_module->addCell(cellname, ID($check));
 				set_src_attr(cell, ast);
+				cell->set_bool_attribute(ID(keep));
 				for (auto &attr : ast->attributes) {
 					if (attr.second->type != AST_CONSTANT)
 						log_file_error(*ast->location.begin.filename, ast->location.begin.line, "Attribute `%s' with non-constant value!\n", attr.first);
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 83174e963..b1331420e 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -879,7 +879,7 @@ static void check_auto_nosync(AstNode *node)
 	}
 
 	// remove the attributes we've "consumed"
-	for (const RTLIL::IdString &str : attrs_to_drop) {
+	for (RTLIL::IdString str : attrs_to_drop) {
 		auto it = node->attributes.find(str);
 		node->attributes.erase(it);
 	}
diff --git a/frontends/verific/verificsva.cc b/frontends/verific/verificsva.cc
index dffe6e8e0..c2cfe7e75 100644
--- a/frontends/verific/verificsva.cc
+++ b/frontends/verific/verificsva.cc
@@ -1846,7 +1846,10 @@ struct VerificSvaImporter
 				if (mode_assume) c = module->addAssume(root_name, sig_a_q, sig_en_q);
 				if (mode_cover) c = module->addCover(root_name, sig_a_q, sig_en_q);
 
-				if (c) importer->import_attributes(c->attributes, root);
+				if (c) {
+					c->set_bool_attribute(ID(keep));
+					importer->import_attributes(c->attributes, root);
+				}
 			}
 		}
 		catch (ParserErrorException)
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 2c3535eac..34b013dd9 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -305,18 +305,18 @@ struct CellTypes
 		cell_types.clear();
 	}
 
-	bool cell_known(const RTLIL::IdString &type) const
+	bool cell_known(RTLIL::IdString type) const
 	{
 		return cell_types.count(type) != 0;
 	}
 
-	bool cell_output(const RTLIL::IdString &type, const RTLIL::IdString &port) const
+	bool cell_output(RTLIL::IdString type, RTLIL::IdString port) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.outputs.count(port) != 0;
 	}
 
-	bool cell_input(const RTLIL::IdString &type, const RTLIL::IdString &port) const
+	bool cell_input(RTLIL::IdString type, RTLIL::IdString port) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.inputs.count(port) != 0;
@@ -332,7 +332,7 @@ struct CellTypes
 		return RTLIL::PortDir(is_input + is_output * 2);
 	}
 
-	bool cell_evaluable(const RTLIL::IdString &type) const
+	bool cell_evaluable(RTLIL::IdString type) const
 	{
 		auto it = cell_types.find(type);
 		return it != cell_types.end() && it->second.is_evaluable;
diff --git a/kernel/io.cc b/kernel/io.cc
index 4f805e43b..078fa139c 100644
--- a/kernel/io.cc
+++ b/kernel/io.cc
@@ -602,7 +602,7 @@ void format_emit_string_view(std::string &result, std::string_view spec, int *dy
 }
 
 void format_emit_idstring(std::string &result, std::string_view spec, int *dynamic_ints,
-	DynamicIntCount num_dynamic_ints, const IdString &arg)
+	DynamicIntCount num_dynamic_ints, const RTLIL::IdString &arg)
 {
 	if (spec == "%s") {
 		// Format checking will have guaranteed num_dynamic_ints == 0.
diff --git a/kernel/modtools.h b/kernel/modtools.h
index 27ba98d7d..a081c7556 100644
--- a/kernel/modtools.h
+++ b/kernel/modtools.h
@@ -161,7 +161,7 @@ struct ModIndex : public RTLIL::Monitor
 #endif
 	}
 
-	void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
+	void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
 		log_assert(module == cell->module);
 
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index bdf56250d..0b019a6fd 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1019,12 +1019,12 @@ RTLIL::Const RTLIL::Const::extract(int offset, int len, RTLIL::State padding) co
 }
 #undef check /* check(condition) for Const */
 
-bool RTLIL::AttrObject::has_attribute(const RTLIL::IdString &id) const
+bool RTLIL::AttrObject::has_attribute(RTLIL::IdString id) const
 {
 	return attributes.count(id);
 }
 
-void RTLIL::AttrObject::set_bool_attribute(const RTLIL::IdString &id, bool value)
+void RTLIL::AttrObject::set_bool_attribute(RTLIL::IdString id, bool value)
 {
 	if (value)
 		attributes[id] = RTLIL::Const(1);
@@ -1032,7 +1032,7 @@ void RTLIL::AttrObject::set_bool_attribute(const RTLIL::IdString &id, bool value
 		attributes.erase(id);
 }
 
-bool RTLIL::AttrObject::get_bool_attribute(const RTLIL::IdString &id) const
+bool RTLIL::AttrObject::get_bool_attribute(RTLIL::IdString id) const
 {
 	const auto it = attributes.find(id);
 	if (it == attributes.end())
@@ -1040,7 +1040,7 @@ bool RTLIL::AttrObject::get_bool_attribute(const RTLIL::IdString &id) const
 	return it->second.as_bool();
 }
 
-void RTLIL::AttrObject::set_string_attribute(const RTLIL::IdString& id, string value)
+void RTLIL::AttrObject::set_string_attribute(RTLIL::IdString id, string value)
 {
 	if (value.empty())
 		attributes.erase(id);
@@ -1048,7 +1048,7 @@ void RTLIL::AttrObject::set_string_attribute(const RTLIL::IdString& id, string v
 		attributes[id] = value;
 }
 
-string RTLIL::AttrObject::get_string_attribute(const RTLIL::IdString &id) const
+string RTLIL::AttrObject::get_string_attribute(RTLIL::IdString id) const
 {
 	std::string value;
 	const auto it = attributes.find(id);
@@ -1057,7 +1057,7 @@ string RTLIL::AttrObject::get_string_attribute(const RTLIL::IdString &id) const
 	return value;
 }
 
-void RTLIL::AttrObject::set_strpool_attribute(const RTLIL::IdString& id, const std::set<string> &data)
+void RTLIL::AttrObject::set_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
 {
 	string attrval;
 	for (const auto &s : data) {
@@ -1068,25 +1068,17 @@ void RTLIL::AttrObject::set_strpool_attribute(const RTLIL::IdString& id, const s
 	set_string_attribute(id, attrval);
 }
 
-void RTLIL::AttrObject::add_strpool_attribute(const RTLIL::IdString& id, const std::set<string> &data)
+void RTLIL::AttrObject::add_strpool_attribute(RTLIL::IdString id, const pool<string> &data)
 {
-	std::set<string> union_data = get_strpool_attribute(id);
+	pool<string> union_data = get_strpool_attribute(id);
 	union_data.insert(data.begin(), data.end());
 	if (!union_data.empty())
 		set_strpool_attribute(id, union_data);
 }
 
-void RTLIL::AttrObject::add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data)
+pool<string> RTLIL::AttrObject::get_strpool_attribute(RTLIL::IdString id) const
 {
-	std::set<string> union_data = get_strpool_attribute(id);
-	union_data.insert(data.begin(), data.end());
-	if (!union_data.empty())
-		set_strpool_attribute(id, union_data);
-}
-
-std::set<string> RTLIL::AttrObject::get_strpool_attribute(const RTLIL::IdString &id) const
-{
-	std::set<string> data;
+	pool<string> data;
 	if (attributes.count(id) != 0)
 		for (auto s : split_tokens(get_string_attribute(id), "|"))
 			data.insert(s);
@@ -1109,7 +1101,7 @@ vector<string> RTLIL::AttrObject::get_hdlname_attribute() const
 	return split_tokens(get_string_attribute(ID::hdlname), " ");
 }
 
-void RTLIL::AttrObject::set_intvec_attribute(const RTLIL::IdString& id, const std::vector<int> &data)
+void RTLIL::AttrObject::set_intvec_attribute(RTLIL::IdString id, const vector<int> &data)
 {
 	std::stringstream attrval;
 	for (auto &i : data) {
@@ -1120,7 +1112,7 @@ void RTLIL::AttrObject::set_intvec_attribute(const RTLIL::IdString& id, const st
 	attributes[id] = RTLIL::Const(attrval.str());
 }
 
-vector<int> RTLIL::AttrObject::get_intvec_attribute(const RTLIL::IdString &id) const
+vector<int> RTLIL::AttrObject::get_intvec_attribute(RTLIL::IdString id) const
 {
 	vector<int> data;
 	auto it = attributes.find(id);
@@ -1138,7 +1130,7 @@ vector<int> RTLIL::AttrObject::get_intvec_attribute(const RTLIL::IdString &id) c
 	return data;
 }
 
-bool RTLIL::Selection::boxed_module(const RTLIL::IdString &mod_name) const
+bool RTLIL::Selection::boxed_module(RTLIL::IdString mod_name) const
 {
 	if (current_design != nullptr) {
 		auto module = current_design->module(mod_name);
@@ -1149,7 +1141,7 @@ bool RTLIL::Selection::boxed_module(const RTLIL::IdString &mod_name) const
 	}
 }
 
-bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const
+bool RTLIL::Selection::selected_module(RTLIL::IdString mod_name) const
 {
 	if (complete_selection)
 		return true;
@@ -1164,7 +1156,7 @@ bool RTLIL::Selection::selected_module(const RTLIL::IdString &mod_name) const
 	return false;
 }
 
-bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) const
+bool RTLIL::Selection::selected_whole_module(RTLIL::IdString mod_name) const
 {
 	if (complete_selection)
 		return true;
@@ -1177,7 +1169,7 @@ bool RTLIL::Selection::selected_whole_module(const RTLIL::IdString &mod_name) co
 	return false;
 }
 
-bool RTLIL::Selection::selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const
+bool RTLIL::Selection::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 {
 	if (complete_selection)
 		return true;
@@ -1304,12 +1296,12 @@ RTLIL::ObjRange<RTLIL::Module*> RTLIL::Design::modules()
 	return RTLIL::ObjRange<RTLIL::Module*>(&modules_, &refcount_modules_);
 }
 
-RTLIL::Module *RTLIL::Design::module(const RTLIL::IdString& name)
+RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name)
 {
 	return modules_.count(name) ? modules_.at(name) : NULL;
 }
 
-const RTLIL::Module *RTLIL::Design::module(const RTLIL::IdString& name) const
+const RTLIL::Module *RTLIL::Design::module(RTLIL::IdString name) const
 {
 	return modules_.count(name) ? modules_.at(name) : NULL;
 }
@@ -1498,21 +1490,21 @@ void RTLIL::Design::optimize()
 		it.second.optimize(this);
 }
 
-bool RTLIL::Design::selected_module(const RTLIL::IdString& mod_name) const
+bool RTLIL::Design::selected_module(RTLIL::IdString mod_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
 	return selection().selected_module(mod_name);
 }
 
-bool RTLIL::Design::selected_whole_module(const RTLIL::IdString& mod_name) const
+bool RTLIL::Design::selected_whole_module(RTLIL::IdString mod_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
 	return selection().selected_whole_module(mod_name);
 }
 
-bool RTLIL::Design::selected_member(const RTLIL::IdString& mod_name, const RTLIL::IdString& memb_name) const
+bool RTLIL::Design::selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const
 {
 	if (!selected_active_module.empty() && mod_name != selected_active_module)
 		return false;
@@ -1709,7 +1701,7 @@ RTLIL::IdString RTLIL::Module::derive(RTLIL::Design*, const dict<RTLIL::IdString
 	log_error("Module `%s' is used with parameters but is not parametric!\n", id2cstr(name));
 }
 
-size_t RTLIL::Module::count_id(const RTLIL::IdString& id)
+size_t RTLIL::Module::count_id(RTLIL::IdString id)
 {
 	return wires_.count(id) + memories.count(id) + cells_.count(id) + processes.count(id);
 }
@@ -1734,7 +1726,7 @@ namespace {
 					cell->name.c_str(), cell->type.c_str(), __FILE__, linenr, buf.str().c_str());
 		}
 
-		int param(const RTLIL::IdString& name)
+		int param(RTLIL::IdString name)
 		{
 			auto it = cell->parameters.find(name);
 			if (it == cell->parameters.end())
@@ -1743,7 +1735,7 @@ namespace {
 			return it->second.as_int();
 		}
 
-		int param_bool(const RTLIL::IdString& name)
+		int param_bool(RTLIL::IdString name)
 		{
 			int v = param(name);
 			if (GetSize(cell->parameters.at(name)) > 32)
@@ -1753,7 +1745,7 @@ namespace {
 			return v;
 		}
 
-		int param_bool(const RTLIL::IdString& name, bool expected)
+		int param_bool(RTLIL::IdString name, bool expected)
 		{
 			int v = param_bool(name);
 			if (v != expected)
@@ -1761,20 +1753,20 @@ namespace {
 			return v;
 		}
 
-		void param_bits(const RTLIL::IdString& name, int width)
+		void param_bits(RTLIL::IdString name, int width)
 		{
 			param(name);
 			if (GetSize(cell->parameters.at(name)) != width)
 				error(__LINE__);
 		}
 
-		std::string param_string(const RTLIL::IdString &name)
+		std::string param_string(RTLIL::IdString name)
 		{
 			param(name);
 			return cell->parameters.at(name).decode_string();
 		}
 
-		void port(const RTLIL::IdString& name, int width)
+		void port(RTLIL::IdString name, int width)
 		{
 			auto it = cell->connections_.find(name);
 			if (it == cell->connections_.end())
@@ -4419,14 +4411,14 @@ std::map<unsigned int, RTLIL::Cell*> *RTLIL::Cell::get_all_cells(void)
 }
 #endif
 
-bool RTLIL::Cell::hasPort(const RTLIL::IdString& portname) const
+bool RTLIL::Cell::hasPort(RTLIL::IdString portname) const
 {
 	return connections_.count(portname) != 0;
 }
 
 // bufnorm
 
-const RTLIL::SigSpec &RTLIL::Cell::getPort(const RTLIL::IdString& portname) const
+const RTLIL::SigSpec &RTLIL::Cell::getPort(RTLIL::IdString portname) const
 {
 	return connections_.at(portname);
 }
@@ -4445,7 +4437,7 @@ bool RTLIL::Cell::known() const
 	return false;
 }
 
-bool RTLIL::Cell::input(const RTLIL::IdString& portname) const
+bool RTLIL::Cell::input(RTLIL::IdString portname) const
 {
 	if (yosys_celltypes.cell_known(type))
 		return yosys_celltypes.cell_input(type, portname);
@@ -4457,7 +4449,7 @@ bool RTLIL::Cell::input(const RTLIL::IdString& portname) const
 	return false;
 }
 
-bool RTLIL::Cell::output(const RTLIL::IdString& portname) const
+bool RTLIL::Cell::output(RTLIL::IdString portname) const
 {
 	if (yosys_celltypes.cell_known(type))
 		return yosys_celltypes.cell_output(type, portname);
@@ -4469,7 +4461,7 @@ bool RTLIL::Cell::output(const RTLIL::IdString& portname) const
 	return false;
 }
 
-RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const
+RTLIL::PortDir RTLIL::Cell::port_dir(RTLIL::IdString portname) const
 {
 	if (yosys_celltypes.cell_known(type))
 		return yosys_celltypes.cell_port_dir(type, portname);
@@ -4485,22 +4477,22 @@ RTLIL::PortDir RTLIL::Cell::port_dir(const RTLIL::IdString& portname) const
 	return PortDir::PD_UNKNOWN;
 }
 
-bool RTLIL::Cell::hasParam(const RTLIL::IdString& paramname) const
+bool RTLIL::Cell::hasParam(RTLIL::IdString paramname) const
 {
 	return parameters.count(paramname) != 0;
 }
 
-void RTLIL::Cell::unsetParam(const RTLIL::IdString& paramname)
+void RTLIL::Cell::unsetParam(RTLIL::IdString paramname)
 {
 	parameters.erase(paramname);
 }
 
-void RTLIL::Cell::setParam(const RTLIL::IdString& paramname, RTLIL::Const value)
+void RTLIL::Cell::setParam(RTLIL::IdString paramname, RTLIL::Const value)
 {
 	parameters[paramname] = std::move(value);
 }
 
-const RTLIL::Const &RTLIL::Cell::getParam(const RTLIL::IdString& paramname) const
+const RTLIL::Const &RTLIL::Cell::getParam(RTLIL::IdString paramname) const
 {
 	const auto &it = parameters.find(paramname);
 	if (it != parameters.end())
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 7cfbd2a8f..692f70cbb 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -241,8 +241,6 @@ struct RTLIL::IdString
 		*this = id;
 	}
 
-	constexpr inline const IdString &id_string() const { return *this; }
-
 	inline const char *c_str() const {
 		if (index_ >= 0)
 			return global_id_storage_.at(index_).buf;
@@ -372,7 +370,7 @@ struct RTLIL::IdString
 		return Substrings(global_autoidx_id_storage_.at(index_).prefix, -index_);
 	}
 
-	inline bool lt_by_name(const IdString &rhs) const {
+	inline bool lt_by_name(IdString rhs) const {
 		Substrings lhs_it = substrings();
 		Substrings rhs_it = rhs.substrings();
 		std::string_view lhs_substr = lhs_it.first();
@@ -399,12 +397,12 @@ struct RTLIL::IdString
 		}
 	}
 
-	inline bool operator<(const IdString &rhs) const {
+	inline bool operator<(IdString rhs) const {
 		return index_ < rhs.index_;
 	}
 
-	inline bool operator==(const IdString &rhs) const { return index_ == rhs.index_; }
-	inline bool operator!=(const IdString &rhs) const { return index_ != rhs.index_; }
+	inline bool operator==(IdString rhs) const { return index_ == rhs.index_; }
+	inline bool operator!=(IdString rhs) const { return index_ != rhs.index_; }
 
 	// The methods below are just convenience functions for better compatibility with std::string.
 
@@ -528,7 +526,7 @@ struct RTLIL::IdString
 		return (... || in(args));
 	}
 
-	bool in(const IdString &rhs) const { return *this == rhs; }
+	bool in(IdString rhs) const { return *this == rhs; }
 	bool in(const char *rhs) const { return *this == rhs; }
 	bool in(const std::string &rhs) const { return *this == rhs; }
 	inline bool in(const pool<IdString> &rhs) const;
@@ -646,13 +644,13 @@ private:
 namespace hashlib {
 	template <>
 	struct hash_ops<RTLIL::IdString> {
-		static inline bool cmp(const RTLIL::IdString &a, const RTLIL::IdString &b) {
+		static inline bool cmp(RTLIL::IdString a, RTLIL::IdString b) {
 			return a == b;
 		}
-		[[nodiscard]] static inline Hasher hash(const RTLIL::IdString &id) {
+		[[nodiscard]] static inline Hasher hash(RTLIL::IdString id) {
 			return id.hash_top();
 		}
-		[[nodiscard]] static inline Hasher hash_into(const RTLIL::IdString &id, Hasher h) {
+		[[nodiscard]] static inline Hasher hash_into(RTLIL::IdString id, Hasher h) {
 			return id.hash_into(h);
 		}
 	};
@@ -759,11 +757,11 @@ namespace RTLIL {
 		return str.substr(1);
 	}
 
-	static inline std::string unescape_id(const RTLIL::IdString &str) {
+	static inline std::string unescape_id(RTLIL::IdString str) {
 		return unescape_id(str.str());
 	}
 
-	static inline const char *id2cstr(const RTLIL::IdString &str) {
+	static inline const char *id2cstr(RTLIL::IdString str) {
 		return log_id(str);
 	}
 
@@ -780,7 +778,7 @@ namespace RTLIL {
 	};
 
 	struct sort_by_id_str {
-		bool operator()(const RTLIL::IdString &a, const RTLIL::IdString &b) const {
+		bool operator()(RTLIL::IdString a, RTLIL::IdString b) const {
 			return a.lt_by_name(b);
 		}
 	};
@@ -1252,23 +1250,22 @@ struct RTLIL::AttrObject
 {
 	dict<RTLIL::IdString, RTLIL::Const> attributes;
 
-	bool has_attribute(const RTLIL::IdString &id) const;
+	bool has_attribute(RTLIL::IdString id) const;
 
-	void set_bool_attribute(const RTLIL::IdString &id, bool value=true);
-	bool get_bool_attribute(const RTLIL::IdString &id) const;
+	void set_bool_attribute(RTLIL::IdString id, bool value=true);
+	bool get_bool_attribute(RTLIL::IdString id) const;
 
 	[[deprecated("Use Module::get_blackbox_attribute() instead.")]]
 	bool get_blackbox_attribute(bool ignore_wb=false) const {
 		return get_bool_attribute(ID::blackbox) || (!ignore_wb && get_bool_attribute(ID::whitebox));
 	}
 
-	void set_string_attribute(const RTLIL::IdString& id, string value);
-	string get_string_attribute(const RTLIL::IdString &id) const;
+	void set_string_attribute(RTLIL::IdString  id, string value);
+	string get_string_attribute(RTLIL::IdString id) const;
 
-	void set_strpool_attribute(const RTLIL::IdString& id, const std::set<string> &data);
-	void add_strpool_attribute(const RTLIL::IdString& id, const std::set<string> &data);
-	void add_strpool_attribute(const RTLIL::IdString& id, const pool<string> &data);
-	std::set<string> get_strpool_attribute(const RTLIL::IdString &id) const;
+	void set_strpool_attribute(RTLIL::IdString  id, const pool<string> &data);
+	void add_strpool_attribute(RTLIL::IdString  id, const pool<string> &data);
+	pool<string> get_strpool_attribute(RTLIL::IdString id) const;
 
 	void set_src_attribute(const std::string &src) {
 		set_string_attribute(ID::src, src);
@@ -1280,8 +1277,8 @@ struct RTLIL::AttrObject
 	void set_hdlname_attribute(const std::vector<string> &hierarchy);
 	std::vector<string> get_hdlname_attribute() const;
 
-	void set_intvec_attribute(const RTLIL::IdString& id, const std::vector<int> &data);
-	std::vector<int> get_intvec_attribute(const RTLIL::IdString &id) const;
+	void set_intvec_attribute(RTLIL::IdString  id, const vector<int> &data);
+	vector<int> get_intvec_attribute(RTLIL::IdString id) const;
 };
 
 struct RTLIL::NamedObject : public RTLIL::AttrObject
@@ -1789,18 +1786,18 @@ struct RTLIL::Selection
 
 	// checks if the given module exists in the current design and is a
 	// boxed module, warning the user if the current design is not set
-	bool boxed_module(const RTLIL::IdString &mod_name) const;
+	bool boxed_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given module is included in this selection
-	bool selected_module(const RTLIL::IdString &mod_name) const;
+	bool selected_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given module is wholly included in this selection,
 	// i.e. not partially selected
-	bool selected_whole_module(const RTLIL::IdString &mod_name) const;
+	bool selected_whole_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given member from the given module is included in this
 	// selection
-	bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
+	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
 
 	// optimizes this selection for the given design by:
 	// - removing non-existent modules and members, any boxed modules and
@@ -1870,7 +1867,7 @@ struct RTLIL::Monitor
 	virtual ~Monitor() { }
 	virtual void notify_module_add(RTLIL::Module*) { }
 	virtual void notify_module_del(RTLIL::Module*) { }
-	virtual void notify_connect(RTLIL::Cell*, const RTLIL::IdString&, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
+	virtual void notify_connect(RTLIL::Cell*, RTLIL::IdString, const RTLIL::SigSpec&, const RTLIL::SigSpec&) { }
 	virtual void notify_connect(RTLIL::Module*, const RTLIL::SigSig&) { }
 	virtual void notify_connect(RTLIL::Module*, const std::vector<RTLIL::SigSig>&) { }
 	virtual void notify_blackout(RTLIL::Module*) { }
@@ -1905,11 +1902,11 @@ struct RTLIL::Design
 	~Design();
 
 	RTLIL::ObjRange<RTLIL::Module*> modules();
-	RTLIL::Module *module(const RTLIL::IdString &name);
-	const RTLIL::Module *module(const RTLIL::IdString &name) const;
+	RTLIL::Module *module(RTLIL::IdString name);
+	const RTLIL::Module *module(RTLIL::IdString name) const;
 	RTLIL::Module *top_module() const;
 
-	bool has(const RTLIL::IdString &id) const {
+	bool has(RTLIL::IdString id) const {
 		return modules_.count(id) != 0;
 	}
 
@@ -1936,15 +1933,15 @@ struct RTLIL::Design
 	void optimize();
 
 	// checks if the given module is included in the current selection
-	bool selected_module(const RTLIL::IdString &mod_name) const;
+	bool selected_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given module is wholly included in the current
 	// selection, i.e. not partially selected
-	bool selected_whole_module(const RTLIL::IdString &mod_name) const;
+	bool selected_whole_module(RTLIL::IdString mod_name) const;
 
 	// checks if the given member from the given module is included in the
 	// current selection
-	bool selected_member(const RTLIL::IdString &mod_name, const RTLIL::IdString &memb_name) const;
+	bool selected_member(RTLIL::IdString mod_name, RTLIL::IdString memb_name) const;
 
 	// checks if the given module is included in the current selection
 	bool selected_module(RTLIL::Module *mod) const;
@@ -2080,7 +2077,7 @@ public:
 	virtual ~Module();
 	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, bool mayfail = false);
 	virtual RTLIL::IdString derive(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Const> &parameters, const dict<RTLIL::IdString, RTLIL::Module*> &interfaces, const dict<RTLIL::IdString, RTLIL::IdString> &modports, bool mayfail = false);
-	virtual size_t count_id(const RTLIL::IdString& id);
+	virtual size_t count_id(RTLIL::IdString id);
 	virtual void expand_interfaces(RTLIL::Design *design, const dict<RTLIL::IdString, RTLIL::Module *> &local_interfaces);
 	virtual bool reprocess_if_necessary(RTLIL::Design *design);
 
@@ -2132,20 +2129,20 @@ public:
 		return design->selected_member(name, member->name);
 	}
 
-	RTLIL::Wire* wire(const RTLIL::IdString &id) {
+	RTLIL::Wire* wire(RTLIL::IdString id) {
 		auto it = wires_.find(id);
 		return it == wires_.end() ? nullptr : it->second;
 	}
-	RTLIL::Cell* cell(const RTLIL::IdString &id) {
+	RTLIL::Cell* cell(RTLIL::IdString id) {
 		auto it = cells_.find(id);
 		return it == cells_.end() ? nullptr : it->second;
 	}
 
-	const RTLIL::Wire* wire(const RTLIL::IdString &id) const{
+	const RTLIL::Wire* wire(RTLIL::IdString id) const{
 		auto it = wires_.find(id);
 		return it == wires_.end() ? nullptr : it->second;
 	}
-	const RTLIL::Cell* cell(const RTLIL::IdString &id) const {
+	const RTLIL::Cell* cell(RTLIL::IdString id) const {
 		auto it = cells_.find(id);
 		return it == cells_.end() ? nullptr : it->second;
 	}
@@ -2505,23 +2502,23 @@ public:
 	dict<RTLIL::IdString, RTLIL::Const> parameters;
 
 	// access cell ports
-	bool hasPort(const RTLIL::IdString &portname) const;
-	void unsetPort(const RTLIL::IdString &portname);
-	void setPort(const RTLIL::IdString &portname, RTLIL::SigSpec signal);
-	const RTLIL::SigSpec &getPort(const RTLIL::IdString &portname) const;
+	bool hasPort(RTLIL::IdString portname) const;
+	void unsetPort(RTLIL::IdString portname);
+	void setPort(RTLIL::IdString portname, RTLIL::SigSpec signal);
+	const RTLIL::SigSpec &getPort(RTLIL::IdString portname) const;
 	const dict<RTLIL::IdString, RTLIL::SigSpec> &connections() const;
 
 	// information about cell ports
 	bool known() const;
-	bool input(const RTLIL::IdString &portname) const;
-	bool output(const RTLIL::IdString &portname) const;
-	PortDir port_dir(const RTLIL::IdString &portname) const;
+	bool input(RTLIL::IdString portname) const;
+	bool output(RTLIL::IdString portname) const;
+	PortDir port_dir(RTLIL::IdString portname) const;
 
 	// access cell parameters
-	bool hasParam(const RTLIL::IdString &paramname) const;
-	void unsetParam(const RTLIL::IdString &paramname);
-	void setParam(const RTLIL::IdString &paramname, RTLIL::Const value);
-	const RTLIL::Const &getParam(const RTLIL::IdString &paramname) const;
+	bool hasParam(RTLIL::IdString paramname) const;
+	void unsetParam(RTLIL::IdString paramname);
+	void setParam(RTLIL::IdString paramname, RTLIL::Const value);
+	const RTLIL::Const &getParam(RTLIL::IdString paramname) const;
 
 	void sort();
 	void check();
diff --git a/kernel/rtlil_bufnorm.cc b/kernel/rtlil_bufnorm.cc
index d0561f880..5f74b3380 100644
--- a/kernel/rtlil_bufnorm.cc
+++ b/kernel/rtlil_bufnorm.cc
@@ -526,7 +526,7 @@ void RTLIL::Module::bufNormalize()
 	pending_deleted_cells.clear();
 }
 
-void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
+void RTLIL::Cell::unsetPort(RTLIL::IdString portname)
 {
 	RTLIL::SigSpec signal;
 	auto conn_it = connections_.find(portname);
@@ -586,7 +586,7 @@ void RTLIL::Cell::unsetPort(const RTLIL::IdString& portname)
 	}
 }
 
-void RTLIL::Cell::setPort(const RTLIL::IdString& portname, RTLIL::SigSpec signal)
+void RTLIL::Cell::setPort(RTLIL::IdString portname, RTLIL::SigSpec signal)
 {
 	auto r = connections_.insert(portname);
 	auto conn_it = r.first;
diff --git a/kernel/scopeinfo.cc b/kernel/scopeinfo.cc
index 7ed9ebf33..59dd746b5 100644
--- a/kernel/scopeinfo.cc
+++ b/kernel/scopeinfo.cc
@@ -97,13 +97,13 @@ static const char *attr_prefix(ScopeinfoAttrs attrs)
 	}
 }
 
-bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id)
+bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id)
 {
 	log_assert(scopeinfo->type == ID($scopeinfo));
 	return scopeinfo->has_attribute(attr_prefix(attrs) + RTLIL::unescape_id(id));
 }
 
-RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id)
+RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id)
 {
 	log_assert(scopeinfo->type == ID($scopeinfo));
 	auto found = scopeinfo->attributes.find(attr_prefix(attrs) + RTLIL::unescape_id(id));
diff --git a/kernel/scopeinfo.h b/kernel/scopeinfo.h
index 3bc1a8162..a3939b903 100644
--- a/kernel/scopeinfo.h
+++ b/kernel/scopeinfo.h
@@ -433,10 +433,10 @@ enum class ScopeinfoAttrs {
 };
 
 // Check whether the flattened module or flattened cell corresponding to a $scopeinfo cell had a specific attribute.
-bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);
+bool scopeinfo_has_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id);
 
 // Get a specific attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
-RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, const RTLIL::IdString &id);
+RTLIL::Const scopeinfo_get_attribute(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs, RTLIL::IdString id);
 
 // Get all attribute from the flattened module or flattened cell corresponding to a $scopeinfo cell.
 dict<RTLIL::IdString, RTLIL::Const> scopeinfo_attributes(const RTLIL::Cell *scopeinfo, ScopeinfoAttrs attrs);
diff --git a/passes/cmds/example_dt.cc b/passes/cmds/example_dt.cc
index 7d1c42a79..b10f50502 100644
--- a/passes/cmds/example_dt.cc
+++ b/passes/cmds/example_dt.cc
@@ -77,7 +77,7 @@ struct ExampleDtPass : public Pass
 			auto enqueue = [&](DriveSpec const &spec) {
 				int index = queue(spec);
 				if (index == GetSize(graph_nodes))
-					graph_nodes.emplace_back(compute_graph.add(ID($pending).id_string(), index).index());
+					graph_nodes.emplace_back(compute_graph.add(ID($pending), index).index());
 				//if (index >= GetSize(graph_nodes))
 				return compute_graph[graph_nodes[index]];
 			};
diff --git a/passes/cmds/icell_liberty.cc b/passes/cmds/icell_liberty.cc
index d49cd360a..a928e5d58 100644
--- a/passes/cmds/icell_liberty.cc
+++ b/passes/cmds/icell_liberty.cc
@@ -163,7 +163,6 @@ struct IcellLiberty : Pass {
 		log_header(d, "Executing ICELL_LIBERTY pass.\n");
 
 		size_t argidx;
-		IdString naming_attr;
 		std::string liberty_filename;
 		auto liberty_file = std::make_unique<std::ofstream>();
 
diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc
index e4e78b0ea..6a1fab072 100644
--- a/passes/cmds/printattrs.cc
+++ b/passes/cmds/printattrs.cc
@@ -45,7 +45,7 @@ struct PrintAttrsPass : public Pass {
 		return stringf("%*s", indent, "");
 	}
 
-	static void log_const(const RTLIL::IdString &s, const RTLIL::Const &x, const unsigned int indent) {
+	static void log_const(RTLIL::IdString s, const RTLIL::Const &x, const unsigned int indent) {
 		if (x.flags & RTLIL::CONST_FLAG_STRING)
 			log("%s(* %s=\"%s\" *)\n", get_indent_str(indent), log_id(s), x.decode_string());
 		else if (x.flags == RTLIL::CONST_FLAG_NONE || x.flags == RTLIL::CONST_FLAG_SIGNED)
diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
index b374f16bd..ae13e77c0 100644
--- a/passes/cmds/trace.cc
+++ b/passes/cmds/trace.cc
@@ -36,7 +36,7 @@ struct TraceMonitor : public RTLIL::Monitor
 		log("#TRACE# Module delete: %s\n", log_id(module));
 	}
 
-	void notify_connect(RTLIL::Cell *cell, const RTLIL::IdString &port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
+	void notify_connect(RTLIL::Cell *cell, RTLIL::IdString port, const RTLIL::SigSpec &old_sig, const RTLIL::SigSpec &sig) override
 	{
 		log("#TRACE# Cell connect: %s.%s.%s = %s (was: %s)\n", log_id(cell->module), log_id(cell), log_id(port), log_signal(sig), log_signal(old_sig));
 	}
diff --git a/passes/opt/opt_merge.cc b/passes/opt/opt_merge.cc
index 6cdcbc822..307c2bcd3 100644
--- a/passes/opt/opt_merge.cc
+++ b/passes/opt/opt_merge.cc
@@ -227,6 +227,11 @@ struct OptMergeWorker
 		ct.cell_types.erase(ID($anyconst));
 		ct.cell_types.erase(ID($allseq));
 		ct.cell_types.erase(ID($allconst));
+		ct.cell_types.erase(ID($check));
+		ct.cell_types.erase(ID($assert));
+		ct.cell_types.erase(ID($assume));
+		ct.cell_types.erase(ID($live));
+		ct.cell_types.erase(ID($cover));
 
 		log("Finding identical cells in module `%s'.\n", module->name);
 		assign_map.set(module);
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 6d8446f82..3374768fd 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -256,7 +256,7 @@ std::optional<AbcProcess> spawn_abc(const char* abc_exe, DeferredLogs &logs) {
 	char arg1[] = "-s";
 	char* argv[] = { strdup(abc_exe), arg1, nullptr };
 	if (0 != posix_spawnp(&result.pid, abc_exe, &file_actions, nullptr, argv, environ)) {
-		logs.log_error("posix_spawnp %s failed", abc_exe);
+		logs.log_error("posix_spawnp %s failed (errno=%s)", abc_exe, strerrorname_np(errno));
 		return std::nullopt;
 	}
 	free(argv[0]);
diff --git a/passes/techmap/bufnorm.cc b/passes/techmap/bufnorm.cc
index a4552c71b..123687255 100644
--- a/passes/techmap/bufnorm.cc
+++ b/passes/techmap/bufnorm.cc
@@ -415,7 +415,7 @@ struct BufnormPass : public Pass {
 				return mapped_bits.at(bit);
 			};
 
-			auto make_buffer_f = [&](const IdString &type, const SigSpec &src, const SigSpec &dst)
+			auto make_buffer_f = [&](IdString type, const SigSpec &src, const SigSpec &dst)
 			{
 				auto it = old_buffers.find(pair<IdString, SigSpec>(type, dst));
 
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index 224ef37b3..da6a4ca0a 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -27,7 +27,7 @@
 USING_YOSYS_NAMESPACE
 YOSYS_NAMESPACE_BEGIN
 
-static void transfer_attr (Cell* to, const Cell* from, const IdString& attr) {
+static void transfer_attr (Cell* to, const Cell* from, IdString attr) {
 	if (from->has_attribute(attr))
 		to->attributes[attr] = from->attributes.at(attr);
 }
diff --git a/pyosys/wrappers_tpl.cc b/pyosys/wrappers_tpl.cc
index 34ac22b09..c299f165f 100644
--- a/pyosys/wrappers_tpl.cc
+++ b/pyosys/wrappers_tpl.cc
@@ -113,7 +113,7 @@ namespace pyosys {
 
 		void notify_connect(
 			RTLIL::Cell *cell,
-			const RTLIL::IdString &port,
+			RTLIL::IdString port,
 			const RTLIL::SigSpec &old_sig,
 			const RTLIL::SigSpec &sig
 		) override {
@@ -238,7 +238,7 @@ namespace pyosys {
 				"notify_connect",
 				py::overload_cast<
 					RTLIL::Cell *,
-					const RTLIL::IdString &,
+					RTLIL::IdString,
 					const RTLIL::SigSpec &,
 					const RTLIL::SigSpec &
 				>(&RTLIL::Monitor::notify_connect)
diff --git a/tests/opt/opt_merge_properties.ys b/tests/opt/opt_merge_properties.ys
new file mode 100644
index 000000000..dddc13bfb
--- /dev/null
+++ b/tests/opt/opt_merge_properties.ys
@@ -0,0 +1,16 @@
+read_verilog -sv <<EOF
+module top ();
+    always_comb begin
+        label1: cover(0);
+        label2: cover(0);
+    end
+endmodule
+EOF
+
+hierarchy -top top
+proc
+chformal -lower
+clean
+opt_merge
+select -assert-count 2 t:$cover
+