From 18a7d4c2625ca5f92f64ec4af28e6bca9edfbfe9 Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Mon, 15 Dec 2025 15:42:41 +1300
Subject: [PATCH] Document nesting packages as unsupported

---
 docs/source/using_yosys/verilog.rst | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst
index a557360b7..ef52bfc25 100644
--- a/docs/source/using_yosys/verilog.rst
+++ b/docs/source/using_yosys/verilog.rst
@@ -355,6 +355,9 @@ from SystemVerilog:
   design with `read_verilog`, all its packages are available to SystemVerilog
   files being read into the same design afterwards.
 
+  - nested packages are currently not supported (i.e. calling ``import`` inside
+    a ``package`` .. ``endpackage`` block)
+
 - typedefs are supported (including inside packages)
 
   - type casts are currently not supported