diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 6d3c39565..6a0f20002 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -4137,6 +4137,10 @@ void RTLIL::Module::bufNormalize()
 				continue;
 			}
 
+			if (cell->type == ID($connect) && portname == ID::A) {
+				continue;
+			}
+
 			Wire *wire = addWire(NEW_ID, GetSize(sig));
 			sigmap.add(sig, wire);
 			cell->setPort(portname, wire);