From 431d5f5e33ba37f8b9453bf020fa3749923d77a4 Mon Sep 17 00:00:00 2001 From: nella Date: Tue, 14 Jul 2026 10:39:17 +0200 Subject: [PATCH 1/8] check make always_latch exempt. --- passes/cmds/check.cc | 10 ++++++---- passes/proc/proc_dlatch.cc | 8 ++++++++ techlibs/efinix/synth_efinix.cc | 3 ++- techlibs/fabulous/synth_fabulous.cc | 3 ++- techlibs/ice40/synth_ice40.cc | 3 ++- techlibs/lattice/synth_lattice.cc | 3 ++- techlibs/nanoxplore/synth_nanoxplore.cc | 3 ++- techlibs/quicklogic/synth_quicklogic.cc | 3 ++- 8 files changed, 26 insertions(+), 10 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index 178653c41..fb0e070ad 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -63,7 +63,8 @@ struct CheckPass : public Pass { log(" -nolatches\n"); log(" also check for latch cells ($dlatch, $adlatch, $dlatchsr and their\n"); log(" $_DLATCH_*/$_DLATCHSR_* mappings) remaining in the design. Use this\n"); - log(" before techmapping in flows that must not emit latches.\n"); + log(" before techmapping in flows that must not emit latches. Cells marked\n"); + log(" with the 'always_latch' attribute are not reported.\n"); log("\n"); log(" -latchonly\n"); log(" check only for latch cells (as listed under -nolatches), skipping all\n"); @@ -142,10 +143,10 @@ struct CheckPass : public Pass { // latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below if (latchonly) { for (auto cell : module->cells()) - if ( + if (( cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_") - ) { + ) && !cell->get_bool_attribute(ID::always_latch)) { log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); counter++; } @@ -300,7 +301,8 @@ struct CheckPass : public Pass { if ( nolatches && ( cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || - cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")) + cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")) && + !cell->get_bool_attribute(ID::always_latch) ) { log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); counter++; diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 1f5f5b9c6..72a9f0f6b 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -546,11 +546,16 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy) else cell = db.module->addDlatch(NEW_ID, en, rhs, lhs); cell->set_src_attribute(src); + if (proc->get_bool_attribute(ID::always_latch)) + cell->set_bool_attribute(ID::always_latch); db.generated_dlatches.insert(cell); if (proc->get_bool_attribute(ID::always_comb)) log_error("Latch inferred for signal `%s.%s' from always_comb process `%s.%s'.\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str()); + else if (proc->get_bool_attribute(ID::always_latch)) + log("Latch inferred for signal `%s.%s' from always_latch process `%s.%s': %s\n", + db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); else if (policy == POLICY_ERROR) log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); @@ -580,6 +585,9 @@ struct ProcDlatchPass : public Pass { log(" -latches \n"); log(" controls how the inference of a latch is reported. Alternatively, one\n"); log(" can use the 'proc.latches' scratchpad variable. Defaults to 'warn'.\n"); + log(" Latches requested explicitly with 'always_latch' processes are exempt\n"); + log(" from this policy and always reported at info level. The generated\n"); + log(" latch cells carry the 'always_latch' attribute.\n"); log("\n"); } void execute(std::vector args, RTLIL::Design *design) override diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index 5bb517112..a35d1d7af 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -68,6 +68,7 @@ struct SynthEfinixPass : public ScriptPass log(" dedicated hardware primitive and are implemented using LUTs\n"); log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -160,7 +161,7 @@ struct SynthEfinixPass : public ScriptPass if (flatten && check_label("flatten", "(unless -noflatten)")) { - run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); + run("proc -latches " + latches); run("check"); run("flatten"); run("tribuf -logic"); diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 49f84294e..7185aafe5 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -115,6 +115,7 @@ struct SynthPass : public ScriptPass { log(" dedicated hardware primitive and are implemented using LUTs\n"); log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -289,7 +290,7 @@ struct SynthPass : public ScriptPass { run("hierarchy -check"); } else run(stringf("hierarchy -check -top %s", top_module)); - run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); + run("proc -latches " + latches); } if (check_label("flatten", "(unless -noflatten)")) { diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index 68db38c51..c01c3deb0 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -119,6 +119,7 @@ struct SynthIce40Pass : public ScriptPass log(" dedicated hardware primitive and are implemented using LUTs\n"); log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -304,7 +305,7 @@ struct SynthIce40Pass : public ScriptPass { run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); - run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); + run("proc -latches " + latches); } if (check_label("flatten", "(unless -noflatten)")) diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index a6daf8f85..d1f26ecdf 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -161,6 +161,7 @@ struct SynthLatticePass : public ScriptPass log(" dedicated hardware primitive and are implemented using LUTs\n"); log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); log(" (ignored with -asyncprld, which has a latch primitive)\n"); log("\n"); log("\n"); @@ -416,7 +417,7 @@ struct SynthLatticePass : public ScriptPass if (check_label("coarse")) { - run("proc -latches " + ((asyncprld || latches == "info") ? std::string("info") : std::string("warn"))); + run("proc -latches " + (asyncprld ? std::string("info") : latches)); if (flatten || help_mode) { run("check"); run("flatten"); diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 20919bead..3cc97f8a4 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -102,6 +102,7 @@ struct SynthNanoXplorePass : public ScriptPass log(" dedicated hardware primitive and are implemented using LUTs\n"); log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -263,7 +264,7 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("coarse")) { - run("proc -latches " + (latches == "info" ? std::string("info") : std::string("warn"))); + run("proc -latches " + latches); if (flatten || help_mode) { run("check"); run("flatten", "(skip if -noflatten)"); diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index 8dddff14c..ca38a6f78 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -77,6 +77,7 @@ struct SynthQuickLogicPass : public ScriptPass { log(" dedicated hardware primitive and are implemented using LUTs\n"); log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); log(" (only applies to the pp3 family)\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -226,7 +227,7 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("prepare")) { - run("proc -latches " + ((family == "pp3" && latches != "info") ? std::string("warn") : std::string("info"))); + run("proc -latches " + (family == "pp3" ? latches : std::string("info"))); if (flatten) { run("check"); run("flatten", "(unless -noflatten)"); From e35beca5af51fad1d9f30c0189956fbfe3c2d70e Mon Sep 17 00:00:00 2001 From: nella Date: Tue, 14 Jul 2026 10:39:29 +0200 Subject: [PATCH 2/8] Test. --- tests/proc/proc_latches.ys | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/tests/proc/proc_latches.ys b/tests/proc/proc_latches.ys index 91749b6a7..ba22bf879 100644 --- a/tests/proc/proc_latches.ys +++ b/tests/proc/proc_latches.ys @@ -22,6 +22,20 @@ logger -check-expected design -reset +# always_latch is exempt +read_verilog -sv < Date: Tue, 14 Jul 2026 10:39:38 +0200 Subject: [PATCH 3/8] Test. --- tests/various/check_nolatches.ys | 12 ++++++++++++ tests/various/synth_latch_warning.ys | 17 ++++++++++++++--- 2 files changed, 26 insertions(+), 3 deletions(-) diff --git a/tests/various/check_nolatches.ys b/tests/various/check_nolatches.ys index 98ae07a26..f1cc124b0 100644 --- a/tests/various/check_nolatches.ys +++ b/tests/various/check_nolatches.ys @@ -21,6 +21,18 @@ hierarchy -top top proc check -nolatches -assert +design -reset +read_verilog -sv < Date: Tue, 14 Jul 2026 10:39:58 +0200 Subject: [PATCH 4/8] Document always_latch. --- docs/source/using_yosys/verilog.rst | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst index ef52bfc25..20f697cec 100644 --- a/docs/source/using_yosys/verilog.rst +++ b/docs/source/using_yosys/verilog.rst @@ -172,7 +172,10 @@ Verilog Attributes and non-standard features - The frontend sets attributes ``always_comb``, ``always_latch`` and ``always_ff`` on processes derived from SystemVerilog style always blocks according to the type of the always. These are checked for correctness in - ``proc_dlatch``. + ``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt + from the ``proc -latches `` reporting policy, and the + generated latch cells carry the ``always_latch`` attribute, which also + exempts them from `check` ``-nolatches``/``-latchonly``. - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete connections From c6f4f2f79dac20f98be26a82f0d8620127f9824b Mon Sep 17 00:00:00 2001 From: nella Date: Fri, 24 Jul 2026 10:45:03 +0200 Subject: [PATCH 5/8] Fixup README. --- docs/source/using_yosys/verilog.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/source/using_yosys/verilog.rst b/docs/source/using_yosys/verilog.rst index 20f697cec..c503bd182 100644 --- a/docs/source/using_yosys/verilog.rst +++ b/docs/source/using_yosys/verilog.rst @@ -175,7 +175,7 @@ Verilog Attributes and non-standard features ``proc_dlatch``. Latches inferred from ``always_latch`` processes are exempt from the ``proc -latches `` reporting policy, and the generated latch cells carry the ``always_latch`` attribute, which also - exempts them from `check` ``-nolatches``/``-latchonly``. + exempts them from `check` ``-nolatches``. - The cell attribute ``wildcard_port_conns`` represents wildcard port connections (SystemVerilog ``.*``). These are resolved to concrete connections From fcffeba23835580a2d8e310f61bc97db25d99542 Mon Sep 17 00:00:00 2001 From: nella Date: Fri, 24 Jul 2026 10:53:40 +0200 Subject: [PATCH 6/8] Extend latch policy. --- passes/cmds/check.cc | 10 ++++----- passes/proc/proc.cc | 2 +- techlibs/analogdevices/synth_analogdevices.cc | 21 +++++++++++++++++-- techlibs/common/synth.cc | 2 +- techlibs/intel_alm/synth_intel_alm.cc | 21 +++++++++++++++++-- 5 files changed, 44 insertions(+), 12 deletions(-) diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc index fb0e070ad..15d7583fc 100644 --- a/passes/cmds/check.cc +++ b/passes/cmds/check.cc @@ -143,10 +143,9 @@ struct CheckPass : public Pass { // latch-only mode only flags latches, skipping the (potentially false-positive mid-flow) undriven/driver/loop checks below if (latchonly) { for (auto cell : module->cells()) - if (( + if (!cell->get_bool_attribute(ID::always_latch) && ( cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || - cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_") - ) && !cell->get_bool_attribute(ID::always_latch)) { + cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_"))) { log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); counter++; } @@ -299,10 +298,9 @@ struct CheckPass : public Pass { } if ( - nolatches && ( + nolatches && !cell->get_bool_attribute(ID::always_latch) && ( cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr)) || - cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")) && - !cell->get_bool_attribute(ID::always_latch) + cell->type.begins_with("$_DLATCH_") || cell->type.begins_with("$_DLATCHSR_")) ) { log_warning("Cell %s.%s is a latch of type %s.\n", module, cell, cell->type.unescape()); counter++; diff --git a/passes/proc/proc.cc b/passes/proc/proc.cc index d781d9047..1f25c5608 100644 --- a/passes/proc/proc.cc +++ b/passes/proc/proc.cc @@ -69,7 +69,7 @@ struct ProcPass : public Pass { log(" -noopt\n"); log(" Will omit the opt_expr pass.\n"); log("\n"); - log(" -latches \n"); + log(" -latches \n"); log(" controls how the inference of a latch is reported.\n"); log("\n"); } diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index aa27c78b6..8653fbf32 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -108,13 +108,20 @@ struct SynthAnalogDevicesPass : public ScriptPass log(" -noabc9\n"); log(" disable use of new ABC9 flow\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - std::string top_opt, edif_file, json_file, tech, tech_param; + std::string top_opt, edif_file, json_file, tech, tech_param, latches; bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp; bool abc9, dff; bool flatten_before_abc; @@ -127,6 +134,7 @@ struct SynthAnalogDevicesPass : public ScriptPass edif_file.clear(); tech = "t16ffc"; tech_param = " -D IS_T16FFC"; + latches = "error"; flatten = true; retime = false; noiopad = false; @@ -244,10 +252,17 @@ struct SynthAnalogDevicesPass : public ScriptPass json_file = args[++argidx]; continue; } + if (args[argidx] == "-latches" && argidx+1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); + if (!(tech == "t16ffc" || tech == "t40lp")) log_cmd_error("Invalid ADI -tech setting: '%s'.\n", tech); @@ -276,7 +291,7 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("prepare")) { - run("proc"); + run("proc -latches " + latches); if (flatten || help_mode) { run("check"); run("flatten", "(with '-flatten')"); @@ -439,6 +454,8 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("map_ffs")) { + if (latches == "error" || help_mode) + run("check -latchonly -assert", "(only if -latches error, the default)"); run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"); if (abc9 || help_mode) { if (dff || help_mode) diff --git a/techlibs/common/synth.cc b/techlibs/common/synth.cc index 31986f25b..cfe8e1b8d 100644 --- a/techlibs/common/synth.cc +++ b/techlibs/common/synth.cc @@ -78,7 +78,7 @@ struct SynthPass : public ScriptPass { log(" -nordff\n"); log(" passed to 'memory'. prohibits merging of FFs into memory read ports\n"); log("\n"); - log(" -latches \n"); + log(" -latches \n"); log(" controls how the inference of a latch is reported.\n"); log("\n"); log(" -noshare\n"); diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 95dbb6e35..869399f42 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -72,12 +72,19 @@ struct SynthIntelALMPass : public ScriptPass { log(" -noclkbuf\n"); log(" do not insert global clock buffers\n"); log("\n"); + log(" -latches \n"); + log(" select the behaviour for latches that cannot be mapped to a\n"); + log(" dedicated hardware primitive and are implemented using LUTs\n"); + log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); + log(" prints a warning, and 'info' permits them with an info-level message.\n"); + log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, family_opt, bram_type; + string top_opt, family_opt, bram_type, latches; bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf; void clear_flags() override @@ -85,6 +92,7 @@ struct SynthIntelALMPass : public ScriptPass { top_opt = "-auto-top"; family_opt = "cyclonev"; bram_type = "m10k"; + latches = "error"; flatten = true; nolutram = false; nobram = false; @@ -145,10 +153,17 @@ struct SynthIntelALMPass : public ScriptPass { noclkbuf = true; continue; } + if (args[argidx] == "-latches" && argidx + 1 < args.size()) { + latches = args[++argidx]; + continue; + } break; } extra_args(args, argidx, design); + if (latches != "info" && latches != "warn" && latches != "error") + log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); + if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -183,7 +198,7 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("coarse")) { - run("proc"); + run("proc -latches " + latches); if (flatten || help_mode) { run("check"); run("flatten", "(skip if -noflatten)"); @@ -241,6 +256,8 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_ffs")) { + if (latches == "error" || help_mode) + run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap"); run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0"); run("techmap -map +/intel_alm/common/dff_map.v"); From 8b50a13181f94221efd77a37cf6a6e102243b879 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 10 Aug 2026 10:53:58 +0200 Subject: [PATCH 7/8] Add global latch policy. --- passes/proc/CMakeLists.txt | 1 + passes/proc/proc_dlatch.cc | 19 ++---- passes/proc/proc_dlatch.h | 67 +++++++++++++++++++ techlibs/analogdevices/CMakeLists.txt | 1 + techlibs/analogdevices/latches_map.v | 11 +++ techlibs/analogdevices/synth_analogdevices.cc | 25 +++---- techlibs/efinix/synth_efinix.cc | 23 +++---- techlibs/fabulous/synth_fabulous.cc | 23 +++---- techlibs/ice40/synth_ice40.cc | 23 +++---- techlibs/intel_alm/CMakeLists.txt | 1 + techlibs/intel_alm/common/latches_map.v | 11 +++ techlibs/intel_alm/synth_intel_alm.cc | 25 +++---- techlibs/lattice/synth_lattice.cc | 24 +++---- techlibs/nanoxplore/synth_nanoxplore.cc | 24 +++---- techlibs/quicklogic/synth_quicklogic.cc | 24 +++---- 15 files changed, 162 insertions(+), 140 deletions(-) create mode 100644 passes/proc/proc_dlatch.h create mode 100644 techlibs/analogdevices/latches_map.v create mode 100644 techlibs/intel_alm/common/latches_map.v diff --git a/passes/proc/CMakeLists.txt b/passes/proc/CMakeLists.txt index b68f7c3d6..98ce8f775 100644 --- a/passes/proc/CMakeLists.txt +++ b/passes/proc/CMakeLists.txt @@ -23,6 +23,7 @@ yosys_pass(proc_mux ) yosys_pass(proc_dlatch proc_dlatch.cc + proc_dlatch.h ) yosys_pass(proc_dff proc_dff.cc diff --git a/passes/proc/proc_dlatch.cc b/passes/proc/proc_dlatch.cc index 72a9f0f6b..76a719b04 100644 --- a/passes/proc/proc_dlatch.cc +++ b/passes/proc/proc_dlatch.cc @@ -22,6 +22,7 @@ #include "kernel/ffinit.h" #include "kernel/consteval.h" #include "kernel/log.h" +#include "passes/proc/proc_dlatch.h" #include #include #include @@ -416,12 +417,6 @@ struct proc_dlatch_db_t } }; -enum LatchPolicy { - POLICY_INFO, - POLICY_WARN, - POLICY_ERROR -}; - void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy) { RTLIL::SigSig latches_bits, nolatches_bits; @@ -556,10 +551,10 @@ void proc_dlatch(proc_dlatch_db_t &db, RTLIL::Process *proc, LatchPolicy policy) else if (proc->get_bool_attribute(ID::always_latch)) log("Latch inferred for signal `%s.%s' from always_latch process `%s.%s': %s\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); - else if (policy == POLICY_ERROR) + else if (policy == LatchPolicy::Error) log_error("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); - else if (policy == POLICY_WARN) + else if (policy == LatchPolicy::Warn) log_warning("Latch inferred for signal `%s.%s' from process `%s.%s': %s\n", db.module->name.c_str(), log_signal(lhs), db.module->name.c_str(), proc->name.c_str(), cell); else @@ -610,13 +605,7 @@ struct ProcDlatchPass : public Pass { policy_str = design->scratchpad_get_string("proc.latches", "warn"); LatchPolicy policy; - if (policy_str == "info") - policy = POLICY_INFO; - else if (policy_str == "warn") - policy = POLICY_WARN; - else if (policy_str == "error") - policy = POLICY_ERROR; - else + if (!latch_policy_from_string(policy_str, policy)) log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", policy_str.c_str()); for (auto mod : design->all_selected_modules()) { diff --git a/passes/proc/proc_dlatch.h b/passes/proc/proc_dlatch.h new file mode 100644 index 000000000..25bb4d134 --- /dev/null +++ b/passes/proc/proc_dlatch.h @@ -0,0 +1,67 @@ +#ifndef PROC_DLATCH_H +#define PROC_DLATCH_H + +#include "kernel/yosys_common.h" +#include "kernel/log.h" + +YOSYS_NAMESPACE_BEGIN + +enum class LatchPolicy { + Info, + Warn, + Error +}; + +inline bool latch_policy_from_string(const std::string &str, LatchPolicy &policy) +{ + if (str == "info") + policy = LatchPolicy::Info; + else if (str == "warn") + policy = LatchPolicy::Warn; + else if (str == "error") + policy = LatchPolicy::Error; + else + return false; + return true; +} + +inline const char *latch_policy_str(LatchPolicy policy) +{ + switch (policy) { + case LatchPolicy::Info: return "info"; + case LatchPolicy::Warn: return "warn"; + default: return "error"; + } +} + +// shared -latches option handling for synth_* passes +struct SynthLatchesConfig { + LatchPolicy policy = LatchPolicy::Error; + + bool parse(const std::vector &args, size_t &idx) + { + if (args[idx] == "-latches" && idx+1 < args.size()) { + if (!latch_policy_from_string(args[++idx], policy)) + log_cmd_error("Invalid value '%s' for -latches (expected info|warn|error).\n", args[idx].c_str()); + return true; + } + return false; + } + + const char *str() const { return latch_policy_str(policy); } + + static const char *help() + { + return + " -latches \n" + " select the behaviour for latches that cannot be mapped to a\n" + " dedicated hardware primitive and are implemented using LUTs\n" + " instead. 'error' (the default) aborts synthesis, 'warn' only\n" + " prints a warning, and 'info' permits them with an info-level message.\n" + " Latches explicitly requested with 'always_latch' are always permitted.\n"; + } +}; + +YOSYS_NAMESPACE_END + +#endif diff --git a/techlibs/analogdevices/CMakeLists.txt b/techlibs/analogdevices/CMakeLists.txt index 40ee0dcf4..12fe4756b 100644 --- a/techlibs/analogdevices/CMakeLists.txt +++ b/techlibs/analogdevices/CMakeLists.txt @@ -58,6 +58,7 @@ yosys_pass(synth_analogdevices arith_map.v ff_map.v + latches_map.v lut_map.v mux_map.v dsp_map.v diff --git a/techlibs/analogdevices/latches_map.v b/techlibs/analogdevices/latches_map.v new file mode 100644 index 000000000..c28f88cf7 --- /dev/null +++ b/techlibs/analogdevices/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 8653fbf32..0f0d509ea 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -22,6 +22,7 @@ #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -108,12 +109,7 @@ struct SynthAnalogDevicesPass : public ScriptPass log(" -noabc9\n"); log(" disable use of new ABC9 flow\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -121,7 +117,8 @@ struct SynthAnalogDevicesPass : public ScriptPass log("\n"); } - std::string top_opt, edif_file, json_file, tech, tech_param, latches; + std::string top_opt, edif_file, json_file, tech, tech_param; + SynthLatchesConfig latches; bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp; bool abc9, dff; bool flatten_before_abc; @@ -134,7 +131,7 @@ struct SynthAnalogDevicesPass : public ScriptPass edif_file.clear(); tech = "t16ffc"; tech_param = " -D IS_T16FFC"; - latches = "error"; + latches = SynthLatchesConfig(); flatten = true; retime = false; noiopad = false; @@ -252,17 +249,12 @@ struct SynthAnalogDevicesPass : public ScriptPass json_file = args[++argidx]; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); - if (!(tech == "t16ffc" || tech == "t40lp")) log_cmd_error("Invalid ADI -tech setting: '%s'.\n", tech); @@ -291,7 +283,7 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("prepare")) { - run("proc -latches " + latches); + run(stringf("proc -latches %s", latches.str())); if (flatten || help_mode) { run("check"); run("flatten", "(with '-flatten')"); @@ -454,8 +446,9 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("map_ffs")) { - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); + run("techmap -map +/analogdevices/latches_map.v"); run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"); if (abc9 || help_mode) { if (dff || help_mode) diff --git a/techlibs/efinix/synth_efinix.cc b/techlibs/efinix/synth_efinix.cc index a35d1d7af..785ede9f8 100644 --- a/techlibs/efinix/synth_efinix.cc +++ b/techlibs/efinix/synth_efinix.cc @@ -22,6 +22,7 @@ #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -63,12 +64,7 @@ struct SynthEfinixPass : public ScriptPass log(" -nobram\n"); log(" do not use EFX_RAM_5K cells in output netlist\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -76,7 +72,8 @@ struct SynthEfinixPass : public ScriptPass log("\n"); } - string top_opt, edif_file, json_file, latches; + string top_opt, edif_file, json_file; + SynthLatchesConfig latches; bool flatten, retime, nobram; void clear_flags() override @@ -87,7 +84,7 @@ struct SynthEfinixPass : public ScriptPass flatten = true; retime = false; nobram = false; - latches = "error"; + latches = SynthLatchesConfig(); } void execute(std::vector args, RTLIL::Design *design) override @@ -130,18 +127,14 @@ struct SynthEfinixPass : public ScriptPass nobram = true; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); log_header(design, "Executing SYNTH_EFINIX pass.\n"); log_push(); @@ -161,7 +154,7 @@ struct SynthEfinixPass : public ScriptPass if (flatten && check_label("flatten", "(unless -noflatten)")) { - run("proc -latches " + latches); + run(stringf("proc -latches %s", latches.str())); run("check"); run("flatten"); run("tribuf -logic"); @@ -204,7 +197,7 @@ struct SynthEfinixPass : public ScriptPass if (check_label("map_ffs")) { run("dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x"); - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap -D NO_LUT -map +/efinix/cells_map.v"); run("opt_expr -mux_undef"); diff --git a/techlibs/fabulous/synth_fabulous.cc b/techlibs/fabulous/synth_fabulous.cc index 7185aafe5..60c1bd058 100644 --- a/techlibs/fabulous/synth_fabulous.cc +++ b/techlibs/fabulous/synth_fabulous.cc @@ -21,6 +21,7 @@ #include "kernel/log.h" #include "kernel/register.h" #include "kernel/rtlil.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -110,12 +111,7 @@ struct SynthPass : public ScriptPass { log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -123,7 +119,8 @@ struct SynthPass : public ScriptPass { log("\n"); } - string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map, latches; + string top_module, json_file, fsm_opts, memory_opts, carry_mode, cells_map, arith_map, clkbuf_map, multiplier_map; + SynthLatchesConfig latches; std::vector extra_plib, extra_map, extra_mlibmap; std::vector> extra_ffs; @@ -142,7 +139,7 @@ struct SynthPass : public ScriptPass { carry_mode = "none"; flatten = true; json_file = ""; - latches = "error"; + latches = SynthLatchesConfig(); } void execute(std::vector args, RTLIL::Design *design) override @@ -252,18 +249,14 @@ struct SynthPass : public ScriptPass { flatten = false; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); log_header(design, "Executing SYNTH_FABULOUS pass.\n"); log_push(); @@ -290,7 +283,7 @@ struct SynthPass : public ScriptPass { run("hierarchy -check"); } else run(stringf("hierarchy -check -top %s", top_module)); - run("proc -latches " + latches); + run(stringf("proc -latches %s", latches.str())); } if (check_label("flatten", "(unless -noflatten)")) { @@ -399,7 +392,7 @@ struct SynthPass : public ScriptPass { dff_str += stringf(" -cell %s %s", cell, init); run(dff_str); } - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("opt_merge"); } diff --git a/techlibs/ice40/synth_ice40.cc b/techlibs/ice40/synth_ice40.cc index c01c3deb0..2e4313450 100644 --- a/techlibs/ice40/synth_ice40.cc +++ b/techlibs/ice40/synth_ice40.cc @@ -21,6 +21,7 @@ #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -114,12 +115,7 @@ struct SynthIce40Pass : public ScriptPass log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -127,7 +123,8 @@ struct SynthIce40Pass : public ScriptPass log("\n"); } - string top_opt, blif_file, edif_file, json_file, device_opt, latches; + string top_opt, blif_file, edif_file, json_file, device_opt; + SynthLatchesConfig latches; bool nocarry, nodffe, nobram, spram, dsp, flatten, retime, noabc, abc2, vpr, abc9, dff, no_rw_check; int min_ce_use; @@ -151,7 +148,7 @@ struct SynthIce40Pass : public ScriptPass abc9 = true; device_opt = "hx"; no_rw_check = false; - latches = "error"; + latches = SynthLatchesConfig(); } void execute(std::vector args, RTLIL::Design *design) override @@ -258,10 +255,8 @@ struct SynthIce40Pass : public ScriptPass no_rw_check = true; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); @@ -270,8 +265,6 @@ struct SynthIce40Pass : public ScriptPass log_cmd_error("This command only operates on fully selected designs!\n"); if (device_opt != "hx" && device_opt != "lp" && device_opt !="u") log_cmd_error("Invalid or no device specified: '%s'\n", device_opt); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); if (abc9 && retime) log_cmd_error("-retime option not currently compatible with -abc9!\n"); @@ -305,7 +298,7 @@ struct SynthIce40Pass : public ScriptPass { run("read_verilog " + define + " -lib -specify +/ice40/cells_sim.v"); run(stringf("hierarchy -check %s", help_mode ? "-top " : top_opt)); - run("proc -latches " + latches); + run(stringf("proc -latches %s", latches.str())); } if (check_label("flatten", "(unless -noflatten)")) @@ -408,7 +401,7 @@ struct SynthIce40Pass : public ScriptPass run("abc", " (only if -abc2)"); run("ice40_opt", "(only if -abc2)"); } - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap -map +/ice40/latches_map.v"); if (noabc || help_mode) { diff --git a/techlibs/intel_alm/CMakeLists.txt b/techlibs/intel_alm/CMakeLists.txt index 3eaa8b8e6..3f77fd63a 100644 --- a/techlibs/intel_alm/CMakeLists.txt +++ b/techlibs/intel_alm/CMakeLists.txt @@ -41,6 +41,7 @@ yosys_pass(synth_intel_alm common/arith_alm_map.v common/dff_map.v common/dff_sim.v + common/latches_map.v common/dsp_sim.v common/dsp_map.v common/mem_sim.v diff --git a/techlibs/intel_alm/common/latches_map.v b/techlibs/intel_alm/common/latches_map.v new file mode 100644 index 000000000..c28f88cf7 --- /dev/null +++ b/techlibs/intel_alm/common/latches_map.v @@ -0,0 +1,11 @@ +module \$_DLATCH_N_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = !E ? D : Q; +endmodule + +module \$_DLATCH_P_ (E, D, Q); + wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; + input E, D; + output Q = E ? D : Q; +endmodule diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 869399f42..56acf9077 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -22,6 +22,7 @@ #include "kernel/log.h" #include "kernel/register.h" #include "kernel/rtlil.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -72,19 +73,15 @@ struct SynthIntelALMPass : public ScriptPass { log(" -noclkbuf\n"); log(" do not insert global clock buffers\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } - string top_opt, family_opt, bram_type, latches; + string top_opt, family_opt, bram_type; + SynthLatchesConfig latches; bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf; void clear_flags() override @@ -92,7 +89,7 @@ struct SynthIntelALMPass : public ScriptPass { top_opt = "-auto-top"; family_opt = "cyclonev"; bram_type = "m10k"; - latches = "error"; + latches = SynthLatchesConfig(); flatten = true; nolutram = false; nobram = false; @@ -153,17 +150,12 @@ struct SynthIntelALMPass : public ScriptPass { noclkbuf = true; continue; } - if (args[argidx] == "-latches" && argidx + 1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); - if (!design->full_selection()) log_cmd_error("This command only operates on fully selected designs!\n"); @@ -198,7 +190,7 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("coarse")) { - run("proc -latches " + latches); + run(stringf("proc -latches %s", latches.str())); if (flatten || help_mode) { run("check"); run("flatten", "(skip if -noflatten)"); @@ -256,9 +248,10 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_ffs")) { - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap"); + run("techmap -map +/intel_alm/common/latches_map.v"); run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0"); run("techmap -map +/intel_alm/common/dff_map.v"); run("opt -full -undriven -mux_undef"); diff --git a/techlibs/lattice/synth_lattice.cc b/techlibs/lattice/synth_lattice.cc index d1f26ecdf..8742aa9dc 100644 --- a/techlibs/lattice/synth_lattice.cc +++ b/techlibs/lattice/synth_lattice.cc @@ -22,6 +22,7 @@ #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -156,12 +157,7 @@ struct SynthLatticePass : public ScriptPass log(" implement constant comparisons in soft logic, do not involve\n"); log(" hard carry chains\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log(" (ignored with -asyncprld, which has a latch primitive)\n"); log("\n"); log("\n"); @@ -170,7 +166,8 @@ struct SynthLatticePass : public ScriptPass log("\n"); } - string top_opt, edif_file, json_file, family, latches; + string top_opt, edif_file, json_file, family; + SynthLatchesConfig latches; bool noccu2, nodffe, nobram, nolutram, nowidelut, asyncprld, flatten, dff, retime, abc2, abc9, iopad, nodsp, no_rw_check, have_dsp; bool cmp2softlogic; string postfix, arith_map, brams_map, dsp_map, cells_map, map_ram_default, widelut_abc; @@ -197,7 +194,7 @@ struct SynthLatticePass : public ScriptPass iopad = false; nodsp = false; no_rw_check = false; - latches = "error"; + latches = SynthLatchesConfig(); postfix = ""; arith_map = ""; brams_map = ""; @@ -327,10 +324,8 @@ struct SynthLatticePass : public ScriptPass cmp2softlogic = true; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); @@ -338,9 +333,6 @@ struct SynthLatticePass : public ScriptPass if (family.empty()) log_cmd_error("Lattice family parameter must be set.\n"); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); - if (family == "ecp5") { postfix = "_ecp5"; arith_map = "_ccu2c"; @@ -417,7 +409,7 @@ struct SynthLatticePass : public ScriptPass if (check_label("coarse")) { - run("proc -latches " + (asyncprld ? std::string("info") : latches)); + run(stringf("proc -latches %s", asyncprld ? "info" : latches.str())); if (flatten || help_mode) { run("check"); run("flatten"); @@ -548,7 +540,7 @@ struct SynthLatticePass : public ScriptPass if (abc2 || help_mode) run("abc", " (only if -abc2)"); if (!asyncprld || help_mode) { - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(skip if -asyncprld; only if -latches error, the default)"); run("techmap -map +/lattice/latches_map.v", "(skip if -asyncprld)"); } diff --git a/techlibs/nanoxplore/synth_nanoxplore.cc b/techlibs/nanoxplore/synth_nanoxplore.cc index 3cc97f8a4..b126dc981 100644 --- a/techlibs/nanoxplore/synth_nanoxplore.cc +++ b/techlibs/nanoxplore/synth_nanoxplore.cc @@ -22,6 +22,7 @@ #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -97,12 +98,7 @@ struct SynthNanoXplorePass : public ScriptPass log(" read/write collision\" (same result as setting the no_rw_check\n"); log(" attribute on all memories).\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -110,7 +106,8 @@ struct SynthNanoXplorePass : public ScriptPass log("\n"); } - string top_opt, json_file, family, latches; + string top_opt, json_file, family; + SynthLatchesConfig latches; bool flatten, abc9, nocy, nodffe, norfram, nobram, noiopad, no_rw_check; std::string postfix; int min_ce_use, min_srst_use; @@ -131,7 +128,7 @@ struct SynthNanoXplorePass : public ScriptPass postfix = ""; min_ce_use = 8; min_srst_use = 8; - latches = "error"; + latches = SynthLatchesConfig(); } void execute(std::vector args, RTLIL::Design *design) override @@ -210,17 +207,12 @@ struct SynthNanoXplorePass : public ScriptPass no_rw_check = true; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); - if (family.empty()) { //log_warning("NanoXplore family not set, setting it to NG-ULTRA.\n"); family = "ultra"; @@ -264,7 +256,7 @@ struct SynthNanoXplorePass : public ScriptPass if (check_label("coarse")) { - run("proc -latches " + latches); + run(stringf("proc -latches %s", latches.str())); if (flatten || help_mode) { run("check"); run("flatten", "(skip if -noflatten)"); @@ -340,7 +332,7 @@ struct SynthNanoXplorePass : public ScriptPass dfflegalize_args += stringf(" -cell $_DLATCH_?_ x -mince %d -minsrst %d", min_ce_use, min_srst_use); run("dfflegalize" + dfflegalize_args,"($_*DFFE_* only if not -nodffe)"); run("opt_merge"); - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap -map +/nanoxplore/latches_map.v"); run("techmap -map +/nanoxplore/cells_map.v"); diff --git a/techlibs/quicklogic/synth_quicklogic.cc b/techlibs/quicklogic/synth_quicklogic.cc index ca38a6f78..0eff71cdc 100644 --- a/techlibs/quicklogic/synth_quicklogic.cc +++ b/techlibs/quicklogic/synth_quicklogic.cc @@ -21,6 +21,7 @@ #include "kernel/log.h" #include "kernel/register.h" #include "kernel/rtlil.h" +#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -72,12 +73,7 @@ struct SynthQuickLogicPass : public ScriptPass { log(" use old ABC flow, which has generally worse mapping results but is less\n"); log(" likely to have bugs.\n"); log("\n"); - log(" -latches \n"); - log(" select the behaviour for latches that cannot be mapped to a\n"); - log(" dedicated hardware primitive and are implemented using LUTs\n"); - log(" instead. 'error' (the default) aborts synthesis, 'warn' only\n"); - log(" prints a warning, and 'info' permits them with an info-level message.\n"); - log(" Latches explicitly requested with 'always_latch' are always permitted.\n"); + log("%s", SynthLatchesConfig::help()); log(" (only applies to the pp3 family)\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); @@ -85,7 +81,8 @@ struct SynthQuickLogicPass : public ScriptPass { log("\n"); } - string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path, latches; + string top_opt, blif_file, edif_file, family, currmodule, verilog_file, lib_path; + SynthLatchesConfig latches; bool abc9, inferAdder, nobram, bramTypes, dsp, ioff, flatten; void clear_flags() override @@ -104,7 +101,7 @@ struct SynthQuickLogicPass : public ScriptPass { dsp = true; ioff = true; flatten = true; - latches = "error"; + latches = SynthLatchesConfig(); } void set_scratchpad_defaults(RTLIL::Design *design) { @@ -177,10 +174,8 @@ struct SynthQuickLogicPass : public ScriptPass { flatten = false; continue; } - if (args[argidx] == "-latches" && argidx+1 < args.size()) { - latches = args[++argidx]; + if (latches.parse(args, argidx)) continue; - } break; } extra_args(args, argidx, design); @@ -191,9 +186,6 @@ struct SynthQuickLogicPass : public ScriptPass { if (family != "pp3" && family != "qlf_k6n10f") log_cmd_error("Invalid family specified: '%s'\n", family); - if (latches != "info" && latches != "warn" && latches != "error") - log_cmd_error("Invalid value '%s' for -latches (expected info, warn or error)\n", latches.c_str()); - if (abc9 && design->scratchpad_get_int("abc9.D", 0) == 0) { log_warning("delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.\n"); design->scratchpad_set_int("abc9.D", 41667); // 12MHz = 83.33.. ns; divided by two to allow for interconnect delay. @@ -227,7 +219,7 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("prepare")) { - run("proc -latches " + (family == "pp3" ? latches : std::string("info"))); + run(stringf("proc -latches %s", family == "pp3" ? latches.str() : "info")); if (flatten) { run("check"); run("flatten", "(unless -noflatten)"); @@ -331,7 +323,7 @@ struct SynthQuickLogicPass : public ScriptPass { } if (check_label("map_luts", "(for pp3)") && (help_mode || family == "pp3")) { - if (latches == "error" || help_mode) + if (latches.policy == LatchPolicy::Error || help_mode) run("check -latchonly -assert", "(only if -latches error, the default)"); run("techmap -map " + lib_path + family + "/latches_map.v"); if (abc9) { From f93651e6bafe69540f98a229679963eac3b08459 Mon Sep 17 00:00:00 2001 From: nella Date: Mon, 10 Aug 2026 15:02:43 +0200 Subject: [PATCH 8/8] Latches always err add missing. --- techlibs/analogdevices/CMakeLists.txt | 1 - techlibs/analogdevices/latches_map.v | 11 ----------- techlibs/analogdevices/synth_analogdevices.cc | 13 ++----------- techlibs/intel_alm/CMakeLists.txt | 1 - techlibs/intel_alm/common/latches_map.v | 11 ----------- techlibs/intel_alm/synth_intel_alm.cc | 13 ++----------- 6 files changed, 4 insertions(+), 46 deletions(-) delete mode 100644 techlibs/analogdevices/latches_map.v delete mode 100644 techlibs/intel_alm/common/latches_map.v diff --git a/techlibs/analogdevices/CMakeLists.txt b/techlibs/analogdevices/CMakeLists.txt index 12fe4756b..40ee0dcf4 100644 --- a/techlibs/analogdevices/CMakeLists.txt +++ b/techlibs/analogdevices/CMakeLists.txt @@ -58,7 +58,6 @@ yosys_pass(synth_analogdevices arith_map.v ff_map.v - latches_map.v lut_map.v mux_map.v dsp_map.v diff --git a/techlibs/analogdevices/latches_map.v b/techlibs/analogdevices/latches_map.v deleted file mode 100644 index c28f88cf7..000000000 --- a/techlibs/analogdevices/latches_map.v +++ /dev/null @@ -1,11 +0,0 @@ -module \$_DLATCH_N_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = !E ? D : Q; -endmodule - -module \$_DLATCH_P_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = E ? D : Q; -endmodule diff --git a/techlibs/analogdevices/synth_analogdevices.cc b/techlibs/analogdevices/synth_analogdevices.cc index 0f0d509ea..c80a58d05 100644 --- a/techlibs/analogdevices/synth_analogdevices.cc +++ b/techlibs/analogdevices/synth_analogdevices.cc @@ -22,7 +22,6 @@ #include "kernel/celltypes.h" #include "kernel/rtlil.h" #include "kernel/log.h" -#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -109,8 +108,6 @@ struct SynthAnalogDevicesPass : public ScriptPass log(" -noabc9\n"); log(" disable use of new ABC9 flow\n"); log("\n"); - log("%s", SynthLatchesConfig::help()); - log("\n"); log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); @@ -118,7 +115,6 @@ struct SynthAnalogDevicesPass : public ScriptPass } std::string top_opt, edif_file, json_file, tech, tech_param; - SynthLatchesConfig latches; bool flatten, retime, noiopad, noclkbuf, nobram, nolutram, nosrl, nocarry, nowidelut, nodsp; bool abc9, dff; bool flatten_before_abc; @@ -131,7 +127,6 @@ struct SynthAnalogDevicesPass : public ScriptPass edif_file.clear(); tech = "t16ffc"; tech_param = " -D IS_T16FFC"; - latches = SynthLatchesConfig(); flatten = true; retime = false; noiopad = false; @@ -249,8 +244,6 @@ struct SynthAnalogDevicesPass : public ScriptPass json_file = args[++argidx]; continue; } - if (latches.parse(args, argidx)) - continue; break; } extra_args(args, argidx, design); @@ -283,7 +276,7 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("prepare")) { - run(stringf("proc -latches %s", latches.str())); + run("proc -latches error"); if (flatten || help_mode) { run("check"); run("flatten", "(with '-flatten')"); @@ -446,9 +439,7 @@ struct SynthAnalogDevicesPass : public ScriptPass } if (check_label("map_ffs")) { - if (latches.policy == LatchPolicy::Error || help_mode) - run("check -latchonly -assert", "(only if -latches error, the default)"); - run("techmap -map +/analogdevices/latches_map.v"); + run("check -latchonly -assert"); run("dfflegalize -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r"); if (abc9 || help_mode) { if (dff || help_mode) diff --git a/techlibs/intel_alm/CMakeLists.txt b/techlibs/intel_alm/CMakeLists.txt index 3f77fd63a..3eaa8b8e6 100644 --- a/techlibs/intel_alm/CMakeLists.txt +++ b/techlibs/intel_alm/CMakeLists.txt @@ -41,7 +41,6 @@ yosys_pass(synth_intel_alm common/arith_alm_map.v common/dff_map.v common/dff_sim.v - common/latches_map.v common/dsp_sim.v common/dsp_map.v common/mem_sim.v diff --git a/techlibs/intel_alm/common/latches_map.v b/techlibs/intel_alm/common/latches_map.v deleted file mode 100644 index c28f88cf7..000000000 --- a/techlibs/intel_alm/common/latches_map.v +++ /dev/null @@ -1,11 +0,0 @@ -module \$_DLATCH_N_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = !E ? D : Q; -endmodule - -module \$_DLATCH_P_ (E, D, Q); - wire [1023:0] _TECHMAP_DO_ = "simplemap; opt"; - input E, D; - output Q = E ? D : Q; -endmodule diff --git a/techlibs/intel_alm/synth_intel_alm.cc b/techlibs/intel_alm/synth_intel_alm.cc index 56acf9077..eeca6d244 100644 --- a/techlibs/intel_alm/synth_intel_alm.cc +++ b/techlibs/intel_alm/synth_intel_alm.cc @@ -22,7 +22,6 @@ #include "kernel/log.h" #include "kernel/register.h" #include "kernel/rtlil.h" -#include "passes/proc/proc_dlatch.h" USING_YOSYS_NAMESPACE PRIVATE_NAMESPACE_BEGIN @@ -73,15 +72,12 @@ struct SynthIntelALMPass : public ScriptPass { log(" -noclkbuf\n"); log(" do not insert global clock buffers\n"); log("\n"); - log("%s", SynthLatchesConfig::help()); - log("\n"); log("The following commands are executed by this synthesis command:\n"); help_script(); log("\n"); } string top_opt, family_opt, bram_type; - SynthLatchesConfig latches; bool flatten, nolutram, nobram, dff, nodsp, noiopad, noclkbuf; void clear_flags() override @@ -89,7 +85,6 @@ struct SynthIntelALMPass : public ScriptPass { top_opt = "-auto-top"; family_opt = "cyclonev"; bram_type = "m10k"; - latches = SynthLatchesConfig(); flatten = true; nolutram = false; nobram = false; @@ -150,8 +145,6 @@ struct SynthIntelALMPass : public ScriptPass { noclkbuf = true; continue; } - if (latches.parse(args, argidx)) - continue; break; } extra_args(args, argidx, design); @@ -190,7 +183,7 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("coarse")) { - run(stringf("proc -latches %s", latches.str())); + run("proc -latches error"); if (flatten || help_mode) { run("check"); run("flatten", "(skip if -noflatten)"); @@ -248,10 +241,8 @@ struct SynthIntelALMPass : public ScriptPass { } if (check_label("map_ffs")) { - if (latches.policy == LatchPolicy::Error || help_mode) - run("check -latchonly -assert", "(only if -latches error, the default)"); + run("check -latchonly -assert"); run("techmap"); - run("techmap -map +/intel_alm/common/latches_map.v"); run("dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0"); run("techmap -map +/intel_alm/common/dff_map.v"); run("opt -full -undriven -mux_undef");