diff --git a/abc b/abc
index da3457143..0b06bc1ab 160000
--- a/abc
+++ b/abc
@@ -1 +1 @@
-Subproject commit da3457143c09ddc9e3e8ae73f8d41c92f288daa1
+Subproject commit 0b06bc1ab08186152de5f74e1a71674d9cdb974c
diff --git a/passes/techmap/abc.cc b/passes/techmap/abc.cc
index 4f9fb3a95..3f284f844 100644
--- a/passes/techmap/abc.cc
+++ b/passes/techmap/abc.cc
@@ -992,7 +992,7 @@ void AbcModuleState::prepare_module(RTLIL::Design *design, RTLIL::Module *module
 	log_header(design, "Extracting gate netlist of module `%s' to `%s/input.blif'..\n",
 			module->name.c_str(), replace_tempdir(run_abc.tempdir_name, run_abc.tempdir_name, config.show_tempdir).c_str());
 
-	std::string abc_script = stringf("read_blif " + (config.abc_node_retention ? " -r" : "") + " \"%s/input.blif\"; ", run_abc.tempdir_name);
+	std::string abc_script = stringf((std::string("read_blif") + (config.abc_node_retention ? " -r" : "") + " \"%s/input.blif\"; ").c_str(), run_abc.tempdir_name);
 
 	if (!config.liberty_files.empty() || !config.genlib_files.empty()) {
 		std::string dont_use_args;