From bc07c6b1b00de5a0af64d08ddf22b166ae3fe150 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 18 May 2026 13:39:04 +0200
Subject: [PATCH 01/16] Improve arith_tree: FMA add, elarith WIP.

---
 kernel/compressor_tree.h     | 332 +++++++++++++++++++++++++++++
 kernel/wallace_tree.h        | 112 ----------
 passes/techmap/arith_tree.cc | 402 +++++++++++++++++++++++------------
 passes/techmap/booth.cc      |   8 +-
 4 files changed, 599 insertions(+), 255 deletions(-)
 create mode 100644 kernel/compressor_tree.h
 delete mode 100644 kernel/wallace_tree.h

diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
new file mode 100644
index 000000000..1b631eb36
--- /dev/null
+++ b/kernel/compressor_tree.h
@@ -0,0 +1,332 @@
+/**
+ * Generalized compressor-tree utilities for multi-operand addition
+ *
+ * Terminology:
+ * - compressor: $fa viewed as reducing N inputs to M outputs (sum + shifted carry) (N:M compressor)
+ * - level:      A stage of parallel compression operations
+ * - depth:      Maximum number of N:M compressor levels from any input to a signal
+ *
+ * Supported compressors:
+ * - 3:2 compressor
+ * - 4:2 compressor
+ *
+ * References:
+ * - "Some schemes for parallel multipliers" (https://www.acsel-lab.com/arithmetic/arith6/papers/ARITH6_Dadda.pdf)
+ * - "Binary Adder Architectures for Cell-Based VLSI" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
+ * - "Basilisk: Achieving Competitive Performance with Open EDA Tools" (https://arxiv.org/pdf/2405.03523)
+ * - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
+ * - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
+ */
+
+#ifndef COMPRESSOR_TREE_H
+#define COMPRESSOR_TREE_H
+
+#include "kernel/sigtools.h"
+#include "kernel/yosys.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+namespace CompressorTree
+{
+
+// Width threshold below which a ripple is preferred over parallel-prefix
+constexpr int RIPPLE_PREFIX_THRESHOLD = 16;
+
+enum class Strategy {
+	FA_ONLY,   // 3:2 compressors
+	PREFER_42, // Prefer 4:2 grouping when >=4 operands ready
+	DADDA,     // Defer compression until column counts exceed
+};
+
+struct DepthSig {
+	SigSpec sig;
+	int depth;
+};
+
+enum class FinalAdder {
+	DEFAULT,         // emit $add and let downstream techmap pick
+	RIPPLE,          // emit $add with explicit narrow hint
+	PARALLEL_PREFIX, // emit $add with PARALLEL_PREFIX
+	ELARITH_FAST,    // black-box instance of \AddCfast
+	ELARITH_MOP_CSV, // black-box instance of \AddMopCsv
+};
+
+enum class FinalMode {
+	AUTO,
+	RIPPLE,
+	PREFIX,
+	ELARITH
+};
+
+inline std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
+{
+	SigSpec sum = module->addWire(NEW_ID, width);
+	SigSpec cout = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, a, b, c, cout, sum);
+
+	SigSpec carry;
+	carry.append(State::S0);
+	carry.append(cout.extract(0, width - 1));
+	return {sum, carry};
+}
+
+inline std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
+{
+	// First FA: a + b + c -> s0
+	SigSpec s0 = module->addWire(NEW_ID, width);
+	SigSpec cout_h_full = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
+
+	// cin[0] = 0, cin[i] = cout_h_full[i-1]
+	SigSpec cin;
+	cin.append(State::S0);
+	if (width > 1)
+		cin.append(cout_h_full.extract(0, width - 1));
+
+	// Second FA: s0 + d + cin -> sum
+	SigSpec sum = module->addWire(NEW_ID, width);
+	SigSpec carry_full = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
+
+	SigSpec carry;
+	carry.append(State::S0);
+	if (width > 1)
+		carry.append(carry_full.extract(0, width - 1));
+
+	return {sum, carry};
+}
+
+inline SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
+{
+	// Zero/sign-extend to width
+	if (GetSize(sig) < width) {
+		SigBit pad;
+		if (is_signed && GetSize(sig) > 0)
+			pad = sig[GetSize(sig) - 1];
+		else
+			pad = State::S0;
+		sig.append(SigSpec(pad, width - GetSize(sig)));
+	}
+	// Truncate to width
+	if (GetSize(sig) > width)
+		sig = sig.extract(0, width);
+	return sig;
+}
+
+inline bool supports_signedness(bool a_signed, bool b_signed) {
+	return !(a_signed || b_signed);
+}
+
+/**
+ * generate_partial_products() - Generate partial products for FMA concat
+ * @module:The Yosys module to which the compressors will be added
+ * @a: Signal A
+ * @b: Signal B
+ * @a_signed: Whether signal A is signed
+ * @b_signed: Whether signal B is signed
+ * @width: Target width
+ *
+ * Return: Radix-2 partial product matrix as a set of depth-0 vectors
+ */
+inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
+	// TODO: Baugh-Wooley sign extension for mixed sign and sign*sign cases, don't bail out to non-FMA
+	log_assert(supports_signedness(a_signed, b_signed) && "CompressorTree::generate_partial_products: signed inputs unsupported");
+
+	int width_a = GetSize(a);
+	std::vector<DepthSig> products;
+	products.reserve(width_a);
+
+	for (int i = 0; i < width_a; i++) {
+		SigBit ai = a[i];
+
+		// b_shifted = (0_i ## b)
+		SigSpec b_shifted = SigSpec(State::S0, i);
+		b_shifted.append(b);
+		b_shifted = normalize_to_width(b_shifted, false, width);
+
+		// product = b_shifted & replicate(a[i], width)
+		SigSpec ai_rep = SigSpec(ai, width);
+		SigSpec product = module->addWire(NEW_ID, width);
+		module->addAnd(NEW_ID, b_shifted, ai_rep, product);
+
+		products.push_back({product, 0});
+	}
+
+	return products;
+}
+
+/**
+ * reduce_scheduled() - Reduce multiple operands to two using a compressor tree
+ * @module: The Yosys module to which the compressors will be added
+ * @operands: Vector of operands to be reduced
+ * @sigs: Vector of input signals (operands) to be reduced
+ * @width: Target bit-width to which all operands will be zero-extended
+ * @strategy: Compression strategy to use
+ * @compressor_count: Optional pointer to return the number of $fa cells emitted
+ *
+ * Return: The final two reduced operands, that are to be fed into an adder
+ */
+inline std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr) {
+	int levels = 0;
+	int fa_count = 0;
+	int c42_count = 0;
+	int final_depth = 0;
+
+	for (auto &op : operands)
+		op.sig.extend_u0(width);
+
+	// Only compress operands ready at current level
+	for (int level = 0; operands.size() > 2; level++) {
+		// Partition operands into ready and waiting
+		std::vector<DepthSig> ready;
+		std::vector<DepthSig> waiting;
+		ready.reserve(operands.size());
+		for (auto &op : operands) {
+			if (op.depth <= level)
+				ready.push_back(op);
+			else
+				waiting.push_back(op);
+		}
+
+		if (ready.size() < 3) {
+			levels++;
+			continue;
+		}
+
+		// Apply compressors to ready operands
+		std::vector<DepthSig> compressed;
+		compressed.reserve(ready.size());
+		size_t i = 0;
+
+		// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
+		// FA_ONLY skips
+		// DADDA = PREFER_42 (TODO: inspect column heights?)
+		bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
+
+		while (i < ready.size()) {
+			size_t remaining = ready.size() - i;
+
+			if (try_42 && remaining >= 4) {
+				DepthSig a = ready[i + 0];
+				DepthSig b = ready[i + 1];
+				DepthSig c = ready[i + 2];
+				DepthSig d = ready[i + 3];
+
+				auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
+				int dmax = std::max({a.depth, a.depth, a.depth, a.depth});
+
+				compressed.push_back({sum, dmax + 2});
+				compressed.push_back({carry, dmax + 2});
+
+				fa_count += 2;
+				c42_count += 1;
+				i += 4;
+			} else if (remaining >= 3) {
+				DepthSig a = ready[i + 0];
+				DepthSig b = ready[i + 1];
+				DepthSig c = ready[i + 2];
+
+				auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
+				int dmax = std::max({a.depth, b.depth, c.depth});
+
+				compressed.push_back({sum, dmax + 1});
+				compressed.push_back({carry, dmax + 1});
+
+				fa_count += 1;
+				i += 3;
+			} else {
+				// Uncompressed operands pass through to next level
+				for (; i < ready.size(); i++)
+					compressed.push_back(ready[i]);
+				break;
+			}
+		}
+
+		// Merge compressed with waiting operands
+		for (auto &op : waiting)
+			compressed.push_back(op);
+
+		operands = std::move(compressed);
+		levels++;
+	}
+
+	if(compressor_count)
+		*compressor_count = fa_count;
+
+	if (operands.size() == 0)
+		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
+	if (operands.size() == 1)
+		return {operands[0].sig, SigSpec(State::S0, width)};
+
+	final_depth = std::max(operands[0].depth, operands[1].depth);
+	log_assert(operands.size() == 2);
+	log("    CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
+	return {operands[0].sig, operands[1].sig};
+}
+
+/**
+ * emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
+ * @module:The Yosys module to which the compressors will be added
+ * @a: Signal A
+ * @b: Signal B
+ * @y: Signal Y
+ * @choice: Adder type to instantiate
+ * @any_signed: Signed info for library macros
+ *
+ * Return: Cell* of the emitted instance
+ */
+inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice, bool any_signed) {
+	switch (choice) {
+		case FinalAdder::DEFAULT:
+		case FinalAdder::RIPPLE: {
+			return module->addAdd(NEW_ID, a, b, y, false);
+		}
+		case FinalAdder::PARALLEL_PREFIX: {
+			Cell *c = module->addAdd(NEW_ID, a, b, y,false);
+			c->set_string_attribute(ID(adder_arch), "parallel_prefix");
+			return c;
+		}
+		case FinalAdder::ELARITH_FAST: {
+			Cell *c = module->addCell(NEW_ID, IdString("\\AddCfast"));
+			int w = GetSize(y);
+			c->setParam(IdString("\\WIDTH"), w);
+			c->setParam(IdString("\\SPEED"), Const("fast"));
+			c->setParam(IdString("\\SIGNED"), any_signed ? 1 : 0);
+			c->setPort(IdString("\\A"), a);
+			c->setPort(IdString("\\B"), b);
+			c->setPort(IdString("\\Cin"), State::S0);
+			c->setPort(IdString("\\Sum"), y);
+			c->setPort(IdString("\\Cout"), module->addWire(NEW_ID));
+			return c;
+		}
+		case FinalAdder::ELARITH_MOP_CSV: {
+			Cell *c = module->addCell(NEW_ID, IdString("\\AddMopCsv"));
+			int w = GetSize(y);
+			c->setParam(IdString("\\WIDTH"), w);
+			c->setParam(IdString("\\NUM_OPERANDS"), 2);
+			c->setParam(IdString("\\SIGNED"), any_signed ? 1 : 0);
+			c->setParam(IdString("\\SPEED"), Const("fast"));
+			c->setPort(IdString("\\Operands"), {a, b});
+			c->setPort(IdString("\\Sum"), y);
+			return c;
+		}
+	}
+	log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
+	return nullptr;
+}
+
+inline FinalAdder pick_final_adder(int width, FinalMode mode) {
+	switch (mode) {
+		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
+		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
+		case FinalMode::ELARITH: return FinalAdder::ELARITH_FAST;
+		case FinalMode::AUTO:
+		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
+	}
+}
+
+} // namespace CompressorTree
+
+YOSYS_NAMESPACE_END
+
+#endif // COMPRESSOR_TREE_H
\ No newline at end of file
diff --git a/kernel/wallace_tree.h b/kernel/wallace_tree.h
deleted file mode 100644
index eb3513803..000000000
--- a/kernel/wallace_tree.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/**
- * Wallace tree utilities for multi-operand addition using carry-save adders
- *
- * Terminology:
- * - compressor: $fa viewed as reducing 3 inputs to 2 outputs (sum + shifted carry) (3:2 compressor)
- * - level:      A stage of parallel compression operations
- * - depth:      Maximum number of 3:2 compressor levels from any input to a signal
- *
- * References:
- * - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
- * - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
- */
-
-#ifndef WALLACE_TREE_H
-#define WALLACE_TREE_H
-
-#include "kernel/sigtools.h"
-#include "kernel/yosys.h"
-
-YOSYS_NAMESPACE_BEGIN
-
-inline std::pair<SigSpec, SigSpec> emit_fa(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
-{
-	SigSpec sum = module->addWire(NEW_ID, width);
-	SigSpec cout = module->addWire(NEW_ID, width);
-
-	module->addFa(NEW_ID, a, b, c, cout, sum);
-
-	SigSpec carry;
-	carry.append(State::S0);
-	carry.append(cout.extract(0, width - 1));
-	return {sum, carry};
-}
-
-/**
- * wallace_reduce_scheduled() - Reduce multiple operands to two using a Wallace tree
- * @module: The Yosys module to which the compressors will be added
- * @sigs: Vector of input signals (operands) to be reduced
- * @width: Target bit-width to which all operands will be zero-extended
- * @compressor_count: Optional pointer to return the number of $fa cells emitted
- *
- * Return: The final two reduced operands, that are to be fed into an adder
- */
-inline std::pair<SigSpec, SigSpec> wallace_reduce_scheduled(Module *module, std::vector<SigSpec> &sigs, int width, int *compressor_count = nullptr)
-{
-	struct DepthSig {
-		SigSpec sig;
-		int depth;
-	};
-
-	for (auto &s : sigs)
-		s.extend_u0(width);
-
-	std::vector<DepthSig> operands;
-	operands.reserve(sigs.size());
-	for (auto &s : sigs)
-		operands.push_back({s, 0});
-
-	// Number of $fa's emitted
-	if (compressor_count)
-		*compressor_count = 0;
-
-	// Only compress operands ready at current level
-	for (int level = 0; operands.size() > 2; level++) {
-		// Partition operands into ready and waiting
-		std::vector<DepthSig> ready, waiting;
-		for (auto &op : operands) {
-			if (op.depth <= level)
-				ready.push_back(op);
-			else
-				waiting.push_back(op);
-		}
-
-		if (ready.size() < 3)
-			continue;
-
-		// Apply compressors to ready operands
-		std::vector<DepthSig> compressed;
-		size_t i = 0;
-		while (i + 2 < ready.size()) {
-			auto [sum, carry] = emit_fa(module, ready[i].sig, ready[i + 1].sig, ready[i + 2].sig, width);
-			int new_depth = std::max({ready[i].depth, ready[i + 1].depth, ready[i + 2].depth}) + 1;
-			compressed.push_back({sum, new_depth});
-			compressed.push_back({carry, new_depth});
-			if (compressor_count)
-				(*compressor_count)++;
-			i += 3;
-		}
-		// Uncompressed operands pass through to next level
-		for (; i < ready.size(); i++)
-			compressed.push_back(ready[i]);
-		// Merge compressed with waiting operands
-		for (auto &op : waiting)
-			compressed.push_back(op);
-
-		operands = std::move(compressed);
-	}
-
-	if (operands.size() == 0)
-		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
-	else if (operands.size() == 1)
-		return {operands[0].sig, SigSpec(State::S0, width)};
-	else {
-		log_assert(operands.size() == 2);
-		log("    Wallace tree depth: %d levels of $fa + 1 final $add\n", std::max(operands[0].depth, operands[1].depth));
-		return {operands[0].sig, operands[1].sig};
-	}
-}
-
-YOSYS_NAMESPACE_END
-
-#endif
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index 259e0c5bb..eef0b1c2c 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -1,5 +1,5 @@
 /**
- * Replaces chains of $add/$sub and $macc cells with carry-save adder trees
+ * Replaces chains of $add/$sub/$alu and $macc cells with carry-save compression trees
  *
  * Terminology:
  * - parent:    Cells that consume another cell's output
@@ -7,9 +7,9 @@
  * - chain:     Connected path of chainable cells
  */
 
+#include "kernel/compressor_tree.h"
 #include "kernel/macc.h"
 #include "kernel/sigtools.h"
-#include "kernel/wallace_tree.h"
 #include "kernel/yosys.h"
 
 #include <queue>
@@ -17,49 +17,58 @@
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
 
-struct Operand {
-	SigSpec sig;
-	bool is_signed;
-	bool negate;
+struct ArithTreeOptions {
+	CompressorTree::Strategy strategy = CompressorTree::Strategy::PREFER_42;
+	CompressorTree::FinalMode final_mode = CompressorTree::FinalMode::AUTO;
+	bool fma_fusion = true;
+	bool elarith_macro = false;
 };
 
-struct Traversal {
+struct ArithTreeWorker {
+	const ArithTreeOptions &opt;
+	Module *module;
 	SigMap sigmap;
+
 	dict<SigBit, pool<Cell *>> bit_consumers;
 	dict<SigBit, int> fanout;
-	Traversal(Module *module) : sigmap(module)
-	{
-		for (auto cell : module->cells())
-			for (auto &conn : cell->connections())
-				if (cell->input(conn.first))
-					for (auto bit : sigmap(conn.second))
-						bit_consumers[bit].insert(cell);
 
-		for (auto &pair : bit_consumers)
-			fanout[pair.first] = pair.second.size();
+	pool<Cell *> addsub;
+	pool<Cell *> alu;
+	pool<Cell *> macc;
+
+	struct Operand {
+		SigSpec sig;
+		bool is_signed;
+		bool negate;
+		// With FMA, when both factors are set, the operand represents a product to
+		// be expanded into partial products at extraction time, is_signed then
+		// applies to factor_a, and factor_b carries its own signedness
+		SigSpec factor_b; // empty for regular operands
+		bool factor_b_signed = false;
+	};
+
+	ArithTreeWorker(const ArithTreeOptions &opt, Module *module) : opt(opt), module(module), sigmap(module)
+	{
+		// Build traversal data
+		for (auto cell : module->cells()) {
+			for (auto &[name, sig] : cell->connections()) {
+				if (cell->input(name)) {
+					for (auto bit : sigmap(sig)) {
+						bit_consumers[bit].insert(cell);
+					}
+				}
+			}
+		}
+
+		for (auto &[sig, consumers] : bit_consumers)
+			fanout[sig] = consumers.size();
 
 		for (auto wire : module->wires())
 			if (wire->port_output)
 				for (auto bit : sigmap(SigSpec(wire)))
 					fanout[bit]++;
-	}
-};
 
-struct Cells {
-	pool<Cell *> addsub;
-	pool<Cell *> alu;
-	pool<Cell *> macc;
-
-	static bool is_addsub(Cell *cell) { return cell->type == ID($add) || cell->type == ID($sub); }
-
-	static bool is_alu(Cell *cell) { return cell->type == ID($alu); }
-
-	static bool is_macc(Cell *cell) { return cell->type == ID($macc) || cell->type == ID($macc_v2); }
-
-	bool empty() { return addsub.empty() && alu.empty() && macc.empty(); }
-
-	Cells(Module *module)
-	{
+		// Collect cell data
 		for (auto cell : module->cells()) {
 			if (is_addsub(cell))
 				addsub.insert(cell);
@@ -69,59 +78,55 @@ struct Cells {
 				macc.insert(cell);
 		}
 	}
-};
 
-struct AluInfo {
-	Cells &cells;
-	Traversal &traversal;
-	bool is_subtract(Cell *cell)
-	{
-		SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
-		SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
+	bool is_addsub(Cell *cell) {
+		return cell->type == ID($add) || cell->type == ID($sub);
+	}
+
+	bool is_alu(Cell *cell) {
+		return cell->type == ID($alu);
+	}
+
+	bool is_macc(Cell *cell) {
+		return cell->type == ID($macc) || cell->type == ID($macc_v2);
+	}
+
+	bool is_sub(Cell *cell) {
+		SigSpec bi = sigmap(cell->getPort(ID::BI));
+		SigSpec ci = sigmap(cell->getPort(ID::CI));
 		return GetSize(bi) == 1 && bi[0] == State::S1 && GetSize(ci) == 1 && ci[0] == State::S1;
 	}
 
 	bool is_add(Cell *cell)
 	{
-		SigSpec bi = traversal.sigmap(cell->getPort(ID::BI));
-		SigSpec ci = traversal.sigmap(cell->getPort(ID::CI));
+		SigSpec bi = sigmap(cell->getPort(ID::BI));
+		SigSpec ci = sigmap(cell->getPort(ID::CI));
 		return GetSize(bi) == 1 && bi[0] == State::S0 && GetSize(ci) == 1 && ci[0] == State::S0;
 	}
 
 	bool is_chainable(Cell *cell)
 	{
-		if (!(is_add(cell) || is_subtract(cell)))
+		if (!(is_add(cell) || is_sub(cell)))
 			return false;
-
-		for (auto bit : traversal.sigmap(cell->getPort(ID::X)))
-			if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
+		for (auto bit : sigmap(cell->getPort(ID::X)))
+			if (fanout.count(bit) && fanout[bit] > 0)
 				return false;
-		for (auto bit : traversal.sigmap(cell->getPort(ID::CO)))
-			if (traversal.fanout.count(bit) && traversal.fanout[bit] > 0)
+		for (auto bit : sigmap(cell->getPort(ID::CO)))
+			if (fanout.count(bit) && fanout[bit] > 0)
 				return false;
-
 		return true;
 	}
-};
-
-struct Rewriter {
-	Module *module;
-	Cells &cells;
-	Traversal traversal;
-	AluInfo alu_info;
-
-	Rewriter(Module *module, Cells &cells) : module(module), cells(cells), traversal(module), alu_info{cells, traversal} {}
 
 	Cell *sole_chainable_consumer(SigSpec sig, const pool<Cell *> &candidates)
 	{
 		Cell *consumer = nullptr;
 		for (auto bit : sig) {
-			if (!traversal.fanout.count(bit) || traversal.fanout[bit] != 1)
+			if (!fanout.count(bit) || fanout[bit] != 1)
 				return nullptr;
-			if (!traversal.bit_consumers.count(bit) || traversal.bit_consumers[bit].size() != 1)
+			if (!bit_consumers.count(bit) || bit_consumers[bit].size() != 1)
 				return nullptr;
 
-			Cell *c = *traversal.bit_consumers[bit].begin();
+			Cell *c = *bit_consumers[bit].begin();
 			if (!candidates.count(c))
 				return nullptr;
 
@@ -137,7 +142,7 @@ struct Rewriter {
 	{
 		dict<Cell *, Cell *> parent_of;
 		for (auto cell : candidates) {
-			Cell *consumer = sole_chainable_consumer(traversal.sigmap(cell->getPort(ID::Y)), candidates);
+			Cell *consumer = sole_chainable_consumer(sigmap(cell->getPort(ID::Y)), candidates);
 			if (consumer && consumer != cell)
 				parent_of[cell] = consumer;
 		}
@@ -177,12 +182,12 @@ struct Rewriter {
 	{
 		pool<SigBit> bits;
 		for (auto cell : chain)
-			for (auto bit : traversal.sigmap(cell->getPort(ID::Y)))
+			for (auto bit : sigmap(cell->getPort(ID::Y)))
 				bits.insert(bit);
 		return bits;
 	}
 
-	static bool overlaps(SigSpec sig, const pool<SigBit> &bits)
+	bool overlaps(SigSpec sig, const pool<SigBit> &bits)
 	{
 		for (auto bit : sig)
 			if (bits.count(bit))
@@ -195,17 +200,16 @@ struct Rewriter {
 		bool parent_subtracts;
 		if (parent->type == ID($sub))
 			parent_subtracts = true;
-		else if (cells.is_alu(parent))
-			parent_subtracts = alu_info.is_subtract(parent);
+		else if (is_alu(parent))
+			parent_subtracts = is_sub(parent);
 		else
 			return false;
 
 		if (!parent_subtracts)
 			return false;
 
-		// Check if any bit of child's Y connects to parent's B
-		SigSpec child_y = traversal.sigmap(child->getPort(ID::Y));
-		SigSpec parent_b = traversal.sigmap(parent->getPort(ID::B));
+		SigSpec child_y = sigmap(child->getPort(ID::Y));
+		SigSpec parent_b = sigmap(parent->getPort(ID::B));
 		for (auto bit : child_y)
 			for (auto pbit : parent_b)
 				if (bit == pbit)
@@ -244,21 +248,20 @@ struct Rewriter {
 		for (auto cell : chain) {
 			bool cell_neg = negated.count(cell) ? negated[cell] : false;
 
-			SigSpec a = traversal.sigmap(cell->getPort(ID::A));
-			SigSpec b = traversal.sigmap(cell->getPort(ID::B));
+			SigSpec a = sigmap(cell->getPort(ID::A));
+			SigSpec b = sigmap(cell->getPort(ID::B));
 			bool a_signed = cell->getParam(ID::A_SIGNED).as_bool();
 			bool b_signed = cell->getParam(ID::B_SIGNED).as_bool();
-			bool b_sub = (cell->type == ID($sub)) || (cells.is_alu(cell) && alu_info.is_subtract(cell));
+			bool b_sub = (cell->type == ID($sub)) || (is_alu(cell) && is_sub(cell));
 
-			// Only add operands not produced by other chain cells
 			if (!overlaps(a, chain_bits)) {
-				operands.push_back({a, a_signed, cell_neg});
+				operands.push_back({a, a_signed, cell_neg, SigSpec(), false});
 				if (cell_neg)
 					neg_compensation++;
 			}
 			if (!overlaps(b, chain_bits)) {
 				bool neg = cell_neg ^ b_sub;
-				operands.push_back({b, b_signed, neg});
+				operands.push_back({b, b_signed, neg, SigSpec(), false});
 				if (neg)
 					neg_compensation++;
 			}
@@ -272,63 +275,123 @@ struct Rewriter {
 		neg_compensation = 0;
 
 		for (auto &term : macc.terms) {
-			// Bail on multiplication
-			if (GetSize(term.in_b) != 0)
-				return false;
-			operands.push_back({term.in_a, term.is_signed, term.do_subtract});
+			if (GetSize(term.in_b) != 0) {
+				// TODO: Baugh-Wooley sign extension for mixed sign and sign*sign cases, don't bail out to non-FMA
+				if (!opt.fma_fusion)
+					return false;
+				if (term.is_signed || !CompressorTree::supports_signedness(term.is_signed, term.is_signed))
+					return false;
+
+				// Preserve term as a multiplicative operand which is expanded into partial products
+				Operand op;
+				op.sig = term.in_a;
+				op.is_signed = false;
+				op.negate = term.do_subtract;
+				op.factor_b = term.in_b;
+				op.factor_b_signed = false;
+				operands.push_back(op);
+				continue;
+			}
+			operands.push_back({term.in_a, term.is_signed, term.do_subtract, SigSpec(), false});
 			if (term.do_subtract)
 				neg_compensation++;
 		}
 		return true;
 	}
 
-	SigSpec extend_operand(SigSpec sig, bool is_signed, int width)
+	std::vector<CompressorTree::DepthSig> build_operand_pool(std::vector<Operand> &operands, int width, int &neg_compensation)
 	{
-		if (GetSize(sig) < width) {
-			SigBit pad;
-			if (is_signed && GetSize(sig) > 0)
-				pad = sig[GetSize(sig) - 1];
-			else
-				pad = State::S0;
-			sig.append(SigSpec(pad, width - GetSize(sig)));
-		}
-		if (GetSize(sig) > width)
-			sig = sig.extract(0, width);
-		return sig;
-	}
-
-	void replace_with_carry_save_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, const char *desc)
-	{
-		int width = GetSize(result_y);
-		std::vector<SigSpec> extended;
-		extended.reserve(operands.size() + 1);
+		// Expand operands into a flat list of signals for reduction
+		std::vector<CompressorTree::DepthSig> pool;
+		pool.reserve(operands.size() * 2);
 
 		for (auto &op : operands) {
-			SigSpec s = extend_operand(op.sig, op.is_signed, width);
-			if (op.negate)
-				s = module->Not(NEW_ID, s);
-			extended.push_back(s);
+			if (GetSize(op.factor_b) == 0) {
+				// Additive operand
+				SigSpec s = CompressorTree::normalize_to_width(op.sig, op.is_signed, width);
+				if (op.negate)
+					s = module->Not(NEW_ID, s);
+				pool.push_back({s, 0});
+			} else {
+				// Multiplicative operand
+				// TODO: Negate product instead of factor
+				auto pps =
+				  CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
+
+				if (op.negate) {
+					for (auto &pp : pps) {
+						SigSpec inv = module->addWire(NEW_ID, width);
+						module->addNot(NEW_ID, pp.sig, inv);
+						pp.sig = inv;
+						neg_compensation++;
+					}
+				}
+
+				for (auto &pp : pps)
+					pool.push_back(pp);
+			}
 		}
 
-		// Add correction for negated operands (-x = ~x + 1 so 1 per negation)
 		if (neg_compensation > 0)
-			extended.push_back(SigSpec(neg_compensation, width));
+			pool.push_back({SigSpec(neg_compensation, width), 0});
 
-		int compressor_count;
-		auto [a, b] = wallace_reduce_scheduled(module, extended, width, &compressor_count);
-		log("  %s -> %d $fa + 1 $add (%d operands, module %s)\n", desc, compressor_count, (int)operands.size(), module);
+		return pool;
+	}
 
-		// Emit final add
-		module->addAdd(NEW_ID, a, b, result_y, false);
+	void emit_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, bool any_signed, const char *desc)
+	{
+		int width = GetSize(result_y);
+
+		if (opt.elarith_macro) {
+			// Bypass the compressor
+			emit_elarith_macro(operands, result_y, neg_compensation, any_signed, desc);
+			return;
+		}
+
+		auto pool = build_operand_pool(operands, width, neg_compensation);
+		auto [a, b] = CompressorTree::reduce_scheduled(module, std::move(pool), width, opt.strategy);
+		auto final_choice = CompressorTree::pick_final_adder(width, opt.final_mode);
+		CompressorTree::emit_final_adder(module, a, b, result_y, final_choice, any_signed);
+	}
+
+	void emit_elarith_macro(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, bool any_signed, const char *desc)
+	{
+		int width = GetSize(result_y);
+		auto pool = build_operand_pool(operands, width, neg_compensation);
+
+		log("  arith_tree::elarith: %s -> \\AddMopCsv macro, %d operands, width %d (module %s)\n", desc, (int)pool.size(), width, log_id(module));
+
+		// Pack all operands
+		SigSpec flat;
+		for (auto &dp : pool) {
+			SigSpec ext = CompressorTree::normalize_to_width(dp.sig, false, width);
+			flat.append(ext);
+		}
+
+		Cell *c = module->addCell(NEW_ID, IdString("\\AddMopCsv"));
+		c->setParam(IdString("\\WIDTH"), width);
+		c->setParam(IdString("\\NUM_OPERANDS"), (int)pool.size());
+		c->setParam(IdString("\\SIGNED"), any_signed ? 1 : 0);
+		c->setParam(IdString("\\SPEED"), Const("fast"));
+		c->setPort(IdString("\\Operands"), flat);
+		c->setPort(IdString("\\Sum"), result_y);
+	}
+
+	bool any_operand_signed(const std::vector<Operand> &operands)
+	{
+		for (auto &op : operands)
+			if (op.is_signed)
+				return true;
+		return false;
 	}
 
 	void process_chains()
 	{
 		pool<Cell *> candidates;
-		for (auto cell : cells.addsub)
+		for (auto cell : addsub)
 			candidates.insert(cell);
-		for (auto cell : cells.alu)
-			if (alu_info.is_chainable(cell))
+		for (auto cell : alu)
+			if (is_chainable(cell))
 				candidates.insert(cell);
 
 		if (candidates.empty())
@@ -354,7 +417,7 @@ struct Rewriter {
 			for (auto c : chain)
 				to_remove.insert(c);
 
-			replace_with_carry_save_tree(operands, root->getPort(ID::Y), neg_compensation, "Replaced add/sub chain");
+			emit_tree(operands, root->getPort(ID::Y), neg_compensation, any_operand_signed(operands), "Replaced $add/$sub chain");
 		}
 
 		for (auto cell : to_remove)
@@ -363,48 +426,76 @@ struct Rewriter {
 
 	void process_maccs()
 	{
-		for (auto cell : cells.macc) {
+		pool<Cell *> to_remove;
+		for (auto cell : macc) {
 			std::vector<Operand> operands;
 			int neg_compensation;
 			if (!extract_macc_operands(cell, operands, neg_compensation))
 				continue;
-			if (operands.size() < 3)
+			if (operands.size() < 1)
+				continue;
+			bool has_mul = false;
+			for (auto &op : operands)
+				if (GetSize(op.factor_b) > 0) {
+					has_mul = true;
+					break;
+				}
+
+			if (!has_mul && operands.size() < 3)
 				continue;
 
-			replace_with_carry_save_tree(operands, cell->getPort(ID::Y), neg_compensation, "Replaced $macc");
-			module->remove(cell);
+			emit_tree(operands, cell->getPort(ID::Y), neg_compensation, any_operand_signed(operands), has_mul ? "Replaced $macc (FMA)" : "Replaced $macc");
+			to_remove.insert(cell);
 		}
+		for (auto cell : to_remove)
+			module->remove(cell);
+	}
+
+	void run()
+	{
+		if (addsub.empty() && alu.empty() && macc.empty())
+			return;
+
+		process_chains();
+		process_maccs();
 	}
 };
 
-void run(Module *module)
-{
-	Cells cells(module);
-
-	if (cells.empty())
-		return;
-
-	Rewriter rewriter{module, cells};
-	rewriter.process_chains();
-	rewriter.process_maccs();
-}
-
 struct ArithTreePass : public Pass {
-	ArithTreePass() : Pass("arith_tree", "convert add/sub/macc chains to carry-save adder trees") {}
+	ArithTreePass() : Pass("arith_tree", "convert add/sub/macc/alu chains to carry-save adder trees") {}
 
 	void help() override
 	{
 		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
 		log("\n");
-		log("    arith_tree [selection]\n");
+		log("    arith_tree [options] [selection]\n");
 		log("\n");
 		log("This pass replaces chains of $add/$sub cells, $alu cells (with constant\n");
-		log("BI/CI), and $macc/$macc_v2 cells (without multiplications) with carry-save\n");
-		log("adder trees using $fa cells and a single final $add.\n");
+		log("BI/CI), and $macc/$macc_v2 cells with carry-save adder trees \n");
+		log("using $fa cells and a single final adder.\n");
 		log("\n");
-		log("The tree uses Wallace-tree scheduling: at each level, ready operands are\n");
-		log("grouped into triplets and compressed via full adders, giving\n");
-		log("O(log_{1.5} N) depth for N input operands.\n");
+		log("    -strategy <fa|42>\n");
+		log("        Compressor strategy. 'fa' uses only 3:2 full-adder groupings\n");
+		log("        '42' (the default) prefers 4:2 compressor groupings, with\n");
+		log("        fallback to 3:2 compressors for residuals\n");
+		log("\n");
+		log("    -final <auto|ripple|prefix|elarith>\n");
+		log("        Selects the architecture used for the final two-vector add.\n");
+		log("        'auto' (default) emits a ripple-style $add for narrow widths\n");
+		log("        (< 16 bits) and a parallel prefix hinted $add for wider ones.\n");
+		log("        'elarith' emits an \\AddCfast black-box from the ELArith\n");
+		log("        library; the surrounding flow must provide that module.\n");
+		log("\n");
+		log("    -no-fma\n");
+		log("        Disable fused multiply-add expansion in $macc cells\n");
+		log("\n");
+		log("    -elarith-macro\n");
+		log("        Replace each detected chain with a single \\AddMopCsv black-box\n");
+		log("        instance instead of expanding it into $fa cells. The downstream\n");
+		log("        flow must provide an \\AddMopCsv implementation\n");
+		log("\n");
+		log("The default behaviour delivers 4:2 compression, FMA fusion, and a\n");
+		log("width-adaptive final adder\n");
 		log("\n");
 	}
 
@@ -412,15 +503,44 @@ struct ArithTreePass : public Pass {
 	{
 		log_header(design, "Executing ARITH_TREE pass.\n");
 
+		ArithTreeOptions opt;
+
 		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			const std::string &arg = args[argidx];
+			if (arg == "-strategy" && argidx + 1 < args.size()) {
+				const std::string &v = args[++argidx];
+				if (v == "fa") { opt.strategy = CompressorTree::Strategy::FA_ONLY; }
+				else if (v == "42") { opt.strategy = CompressorTree::Strategy::PREFER_42; }
+				else { log_cmd_error("arith_tree: unknown -strategy '%s'\n", v.c_str()); }
+				continue;
+			}
+			if (arg == "-final" && argidx + 1 < args.size()) {
+				const std::string &v = args[++argidx];
+				if (v == "auto") { opt.final_mode = CompressorTree::FinalMode::AUTO; }
+				else if (v == "ripple") { opt.final_mode = CompressorTree::FinalMode::RIPPLE; }
+				else if (v == "prefix") { opt.final_mode = CompressorTree::FinalMode::PREFIX; }
+				else if (v == "elarith") { opt.final_mode = CompressorTree::FinalMode::ELARITH; }
+				else { log_cmd_error("arith_tree: unknown -final '%s'\n", v.c_str()); }
+				continue;
+			}
+			if (arg == "-no-fma") {
+				opt.fma_fusion = false;
+				continue;
+			}
+			if (arg == "-elarith-macro") {
+				opt.elarith_macro = true;
+				continue;
+			}
 			break;
+		}
 		extra_args(args, argidx, design);
 
-		for (auto module : design->selected_modules()) {
-			run(module);
+		for (auto mod : design->selected_modules()) {
+			ArithTreeWorker worker(opt, mod);
+			worker.run();
 		}
 	}
 } ArithTreePass;
 
-PRIVATE_NAMESPACE_END
+PRIVATE_NAMESPACE_END
\ No newline at end of file
diff --git a/passes/techmap/booth.cc b/passes/techmap/booth.cc
index 630c83f8c..972edc431 100644
--- a/passes/techmap/booth.cc
+++ b/passes/techmap/booth.cc
@@ -58,7 +58,7 @@ synth -top my_design -booth
 #include "kernel/sigtools.h"
 #include "kernel/yosys.h"
 #include "kernel/macc.h"
-#include "kernel/wallace_tree.h"
+#include "kernel/compressor_tree.h"
 
 USING_YOSYS_NAMESPACE
 PRIVATE_NAMESPACE_BEGIN
@@ -386,7 +386,11 @@ struct BoothPassWorker {
 		// Later on yosys will clean up unused constants
 		//  DebugDumpAlignPP(aligned_pp);
 
-		auto [wtree_a, wtree_b] = wallace_reduce_scheduled(module, aligned_pp, z_sz);
+		std::vector<CompressorTree::DepthSig> operands;
+		operands.reserve(aligned_pp.size());
+		for (auto &s : aligned_pp)
+			operands.push_back({s, 0});
+		auto [wtree_a, wtree_b] = CompressorTree::reduce_scheduled(module, std::move(operands), z_sz, CompressorTree::Strategy::FA_ONLY);
 
 		// Debug code: Dump out the csa trees
 		// DumpCSATrees(debug_csa_trees);

From 6c13ec0efb7185c874bb6fa70758a1c3c33157b6 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 18 May 2026 13:44:40 +0200
Subject: [PATCH 02/16] Test.

---
 tests/arith_tree/arith_tree_42.ys          | 122 +++++++++++++++++++++
 tests/arith_tree/arith_tree_defaults.ys    |  78 +++++++++++++
 tests/arith_tree/arith_tree_edge_cases.ys  |  40 +++++++
 tests/arith_tree/arith_tree_final_adder.ys |  97 ++++++++++++++++
 tests/arith_tree/arith_tree_fma.ys         | 119 ++++++++++++++++++++
 5 files changed, 456 insertions(+)
 create mode 100644 tests/arith_tree/arith_tree_42.ys
 create mode 100644 tests/arith_tree/arith_tree_defaults.ys
 create mode 100644 tests/arith_tree/arith_tree_final_adder.ys
 create mode 100644 tests/arith_tree/arith_tree_fma.ys

diff --git a/tests/arith_tree/arith_tree_42.ys b/tests/arith_tree/arith_tree_42.ys
new file mode 100644
index 000000000..75951ab5e
--- /dev/null
+++ b/tests/arith_tree/arith_tree_42.ys
@@ -0,0 +1,122 @@
+read_verilog <<EOT
+module four_op_42(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 0 t:$fa c:*emit_compressor_32* %i
+design -reset
+
+read_verilog <<EOT
+module four_op_fa(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy fa
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$fa c:*emit_compressor_42* %i
+select -assert-count 2 t:$fa c:*emit_compressor_32* %i
+design -reset
+
+read_verilog <<EOT
+module eight_op_42(
+	input [3:0] a, b, c, d, e, f, g, h,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g + h;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 6 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module sixteen_op_42(
+	input [3:0] a0, a1, a2, a3, a4, a5, a6, a7,
+	input [3:0] a8, a9, a10, a11, a12, a13, a14, a15,
+	output [3:0] y
+);
+	assign y = a0 + a1 + a2 + a3 + a4 + a5 + a6 + a7
+	        + a8 + a9 + a10 + a11 + a12 + a13 + a14 + a15;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 14 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module five_op_42(
+	input [3:0] a, b, c, d, e,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module six_op_42(
+	input [3:0] a, b, c, d, e, f,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 4 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module seven_op_42(
+	input [3:0] a, b, c, d, e, f, g,
+	output [3:0] y
+);
+	assign y = a + b + c + d + e + f + g;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -strategy 42
+design -load postopt
+select -assert-count 5 t:$fa
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
diff --git a/tests/arith_tree/arith_tree_defaults.ys b/tests/arith_tree/arith_tree_defaults.ys
new file mode 100644
index 000000000..1fb73e82e
--- /dev/null
+++ b/tests/arith_tree/arith_tree_defaults.ys
@@ -0,0 +1,78 @@
+# Idempotence
+read_verilog <<EOT
+module idem_add4(
+	input [3:0] a, b, c, d,
+	output [3:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+arith_tree
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add
+design -reset
+
+read_verilog <<EOT
+module idem_mac(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+arith_tree
+select -assert-count 3 t:$fa
+select -assert-count 1 t:$add
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+design -reset
+
+read_verilog <<EOT
+module default_smoke(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+design -reset
+
+read_verilog <<EOT
+module default_narrow(
+	input [14:0] a, b, c, d,
+	output [14:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add a:adder_arch %i
+design -reset
diff --git a/tests/arith_tree/arith_tree_edge_cases.ys b/tests/arith_tree/arith_tree_edge_cases.ys
index fd40f2aa7..280b5d09c 100644
--- a/tests/arith_tree/arith_tree_edge_cases.ys
+++ b/tests/arith_tree/arith_tree_edge_cases.ys
@@ -217,6 +217,26 @@ alumacc
 opt
 arith_tree
 opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-none t:$mul
+select -assert-count 7 t:$fa
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module macc_mul_nofma(
+	input [7:0] a, b, c,
+	output [15:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree -no-fma
+opt_clean
 select -assert-none t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset
@@ -402,6 +422,26 @@ alumacc
 opt
 arith_tree
 opt_clean
+select -assert-none t:$macc t:$macc_v2 %u
+select -assert-none t:$mul
+select -assert-count 8 t:$fa
+select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module macc_mul_survives_nofma(
+	input [7:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a * b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+arith_tree -no-fma
+opt_clean
 select -assert-none t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
new file mode 100644
index 000000000..b4d5824cc
--- /dev/null
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -0,0 +1,97 @@
+read_verilog <<EOT
+module final_auto_wide(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final auto
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa
+select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+design -reset
+
+read_verilog <<EOT
+module final_auto_narrow(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final auto
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 2 t:$fa
+select -assert-count 0 t:$add a:adder_arch %i
+design -reset
+
+read_verilog <<EOT
+module final_ripple(
+	input [31:0] a, b, c, d,
+	output [31:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final ripple
+design -load postopt
+select -assert-count 1 t:$add
+select -assert-count 0 t:$add a:adder_arch %i
+design -reset
+
+read_verilog <<EOT
+module final_prefix_narrow(
+	input [7:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+equiv_opt arith_tree -final prefix
+design -load postopt
+select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+design -reset
+
+read_verilog <<EOT
+module final_elarith(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree -final elarith
+select -assert-count 0 t:$add
+select -assert-count 1 t:\AddCfast
+select -assert-count 2 t:$fa
+select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+design -reset
+
+read_verilog <<EOT
+module elarith_macro(
+	input [15:0] a, b, c, d,
+	output [15:0] y
+);
+	assign y = a + b + c + d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+arith_tree -elarith-macro
+select -assert-count 0 t:$fa
+select -assert-count 0 t:$add
+select -assert-count 1 t:\AddMopCsv
+design -reset
diff --git a/tests/arith_tree/arith_tree_fma.ys b/tests/arith_tree/arith_tree_fma.ys
new file mode 100644
index 000000000..16d90c528
--- /dev/null
+++ b/tests/arith_tree/arith_tree_fma.ys
@@ -0,0 +1,119 @@
+read_verilog <<EOT
+module fma_mul_only(
+	input [3:0] a, b,
+	output [7:0] y
+);
+	assign y = a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_mac(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_dot2(
+	input [3:0] a, b, c, d,
+	output [7:0] y
+);
+	assign y = a * b + c * d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_mac_sub(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b - c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-count 1 t:$add
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module fma_disabled(
+	input [3:0] a, b,
+	input [7:0] c,
+	output [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree -no-fma
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset
+
+read_verilog <<EOT
+module fma_signed_bailout(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset

From 25eb394ad073114339965bf8585697cc8dcb11d6 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 18 May 2026 17:21:26 +0200
Subject: [PATCH 03/16] Collapse signed*signed or combined nodes via BW.

---
 kernel/compressor_tree.h                  |  68 ++++++++---
 passes/techmap/arith_tree.cc              |  35 +++---
 tests/arith_tree/arith_tree_fma.ys        |   7 +-
 tests/arith_tree/arith_tree_signed_fma.ys | 135 ++++++++++++++++++++++
 4 files changed, 210 insertions(+), 35 deletions(-)
 create mode 100644 tests/arith_tree/arith_tree_signed_fma.ys

diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index 1b631eb36..7785aab4d 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -113,10 +113,6 @@ inline SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
 	return sig;
 }
 
-inline bool supports_signedness(bool a_signed, bool b_signed) {
-	return !(a_signed || b_signed);
-}
-
 /**
  * generate_partial_products() - Generate partial products for FMA concat
  * @module:The Yosys module to which the compressors will be added
@@ -126,15 +122,13 @@ inline bool supports_signedness(bool a_signed, bool b_signed) {
  * @b_signed: Whether signal B is signed
  * @width: Target width
  *
- * Return: Radix-2 partial product matrix as a set of depth-0 vectors
+ * Return: Partial-product matrix as a set of depth-0 vectors
  */
 inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
-	// TODO: Baugh-Wooley sign extension for mixed sign and sign*sign cases, don't bail out to non-FMA
-	log_assert(supports_signedness(a_signed, b_signed) && "CompressorTree::generate_partial_products: signed inputs unsupported");
-
 	int width_a = GetSize(a);
+	int width_b = GetSize(b);
 	std::vector<DepthSig> products;
-	products.reserve(width_a);
+	products.reserve(width_a + 3);
 
 	for (int i = 0; i < width_a; i++) {
 		SigBit ai = a[i];
@@ -144,14 +138,62 @@ inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a
 		b_shifted.append(b);
 		b_shifted = normalize_to_width(b_shifted, false, width);
 
-		// product = b_shifted & replicate(a[i], width)
+		// row = b_shifted & replicate(a[i], width)
 		SigSpec ai_rep = SigSpec(ai, width);
-		SigSpec product = module->addWire(NEW_ID, width);
-		module->addAnd(NEW_ID, b_shifted, ai_rep, product);
+		SigSpec row = module->addWire(NEW_ID, width);
+		module->addAnd(NEW_ID, b_shifted, ai_rep, row);
 
-		products.push_back({product, 0});
+		// Apply Modified Baugh-Wooley inversions for this row
+		bool row_is_bottom = (i == width_a - 1);
+		bool any_inversion = (row_is_bottom && b_signed) || a_signed;
+
+		if (any_inversion) {
+			std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
+
+			for (int j = 0; j < width_b; j++) {
+				int col = i + j;
+				if (col < 0 || col >= width)
+					continue;
+				bool col_is_right = (j == width_b - 1);
+				// Flip masks
+				bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
+				if (invert)
+					mask[col] = RTLIL::State::S1;
+			}
+
+			// Skip the xor entirely if the mask is all zeroes
+			bool nonzero = false;
+			for (auto s : mask)
+				if (s == RTLIL::State::S1) {
+					nonzero = true;
+					break;
+				}
+			if (nonzero) {
+				SigSpec inverted = module->addWire(NEW_ID, width);
+				module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
+				row = inverted;
+			}
+		}
+
+		products.push_back({row, 0});
 	}
 
+	// Correction constants
+	auto push_one_at = [&](int col) {
+		if (col < 0 || col >= width) 
+			return;
+		std::vector<RTLIL::State> v(width, RTLIL::State::S0);
+		v[col] = RTLIL::State::S1;
+		products.push_back({SigSpec(RTLIL::Const(v)), 0});
+	};
+
+	if (b_signed)
+		push_one_at(width_a - 1);
+	if (a_signed)
+		push_one_at(width_b - 1);
+	if (a_signed || b_signed)
+		push_one_at(width_a + width_b - 1);
+
 	return products;
 }
 
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index eef0b1c2c..aa91dab51 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -276,19 +276,16 @@ struct ArithTreeWorker {
 
 		for (auto &term : macc.terms) {
 			if (GetSize(term.in_b) != 0) {
-				// TODO: Baugh-Wooley sign extension for mixed sign and sign*sign cases, don't bail out to non-FMA
 				if (!opt.fma_fusion)
 					return false;
-				if (term.is_signed || !CompressorTree::supports_signedness(term.is_signed, term.is_signed))
-					return false;
 
 				// Preserve term as a multiplicative operand which is expanded into partial products
 				Operand op;
 				op.sig = term.in_a;
-				op.is_signed = false;
+				op.is_signed = term.is_signed;
 				op.negate = term.do_subtract;
 				op.factor_b = term.in_b;
-				op.factor_b_signed = false;
+				op.factor_b_signed = term.is_signed;
 				operands.push_back(op);
 				continue;
 			}
@@ -313,22 +310,22 @@ struct ArithTreeWorker {
 					s = module->Not(NEW_ID, s);
 				pool.push_back({s, 0});
 			} else {
-				// Multiplicative operand
-				// TODO: Negate product instead of factor
-				auto pps =
-				  CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
+				// Multiplicative operand.
+				auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
 
-				if (op.negate) {
-					for (auto &pp : pps) {
-						SigSpec inv = module->addWire(NEW_ID, width);
-						module->addNot(NEW_ID, pp.sig, inv);
-						pp.sig = inv;
-						neg_compensation++;
-					}
+				if (!op.negate) {
+					for (auto &pp : pps)
+						pool.push_back(pp);
+					continue;
 				}
 
-				for (auto &pp : pps)
-					pool.push_back(pp);
+				auto [a_red, b_red] = CompressorTree::reduce_scheduled(module, pps, width, opt.strategy);
+				SigSpec product = module->addWire(NEW_ID, width);
+				module->addAdd(NEW_ID, a_red, b_red, product, false);
+				SigSpec neg = module->addWire(NEW_ID, width);
+				module->addNot(NEW_ID, product, neg);
+				pool.push_back({neg, 0});
+				neg_compensation++;
 			}
 		}
 
@@ -380,7 +377,7 @@ struct ArithTreeWorker {
 	bool any_operand_signed(const std::vector<Operand> &operands)
 	{
 		for (auto &op : operands)
-			if (op.is_signed)
+			if (op.is_signed || op.factor_b_signed)
 				return true;
 		return false;
 	}
diff --git a/tests/arith_tree/arith_tree_fma.ys b/tests/arith_tree/arith_tree_fma.ys
index 16d90c528..95d9b566f 100644
--- a/tests/arith_tree/arith_tree_fma.ys
+++ b/tests/arith_tree/arith_tree_fma.ys
@@ -100,7 +100,7 @@ select -assert-min 1 t:$macc t:$macc_v2 %u
 design -reset
 
 read_verilog <<EOT
-module fma_signed_bailout(
+module fma_signed(
 	input signed [3:0] a, b,
 	input signed [7:0] c,
 	output signed [7:0] y
@@ -114,6 +114,7 @@ alumacc
 opt
 equiv_opt arith_tree
 design -load postopt
-select -assert-count 0 t:$fa
-select -assert-min 1 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
 design -reset
diff --git a/tests/arith_tree/arith_tree_signed_fma.ys b/tests/arith_tree/arith_tree_signed_fma.ys
new file mode 100644
index 000000000..104d96d42
--- /dev/null
+++ b/tests/arith_tree/arith_tree_signed_fma.ys
@@ -0,0 +1,135 @@
+read_verilog <<EOT
+module signed_mac(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mul(
+	input signed [3:0] a, b,
+	output signed [7:0] y
+);
+	assign y = a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_dot2(
+	input signed [3:0] a, b, c, d,
+	output signed [7:0] y
+);
+	assign y = a * b + c * d;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_sub(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b - c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_negprod(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = c - a * b;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_wide(
+	input signed [7:0] a, b,
+	input signed [15:0] c,
+	output signed [15:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree
+design -load postopt
+select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$mul
+select -assert-min 1 t:$fa
+design -reset
+
+read_verilog <<EOT
+module signed_mac_nofma(
+	input signed [3:0] a, b,
+	input signed [7:0] c,
+	output signed [7:0] y
+);
+	assign y = a * b + c;
+endmodule
+EOT
+hierarchy -auto-top
+proc
+alumacc
+opt
+equiv_opt arith_tree -no-fma
+design -load postopt
+select -assert-count 0 t:$fa
+select -assert-min 1 t:$macc t:$macc_v2 %u
+design -reset

From 862e9fc54e8574f686f90aba284f3b9c153cede6 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Tue, 19 May 2026 10:39:01 +0200
Subject: [PATCH 04/16] Remove elarith-fast for now.

---
 kernel/compressor_tree.h     | 15 ---------------
 passes/techmap/arith_tree.cc |  1 +
 2 files changed, 1 insertion(+), 15 deletions(-)

diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index 7785aab4d..ff5978977 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -47,7 +47,6 @@ enum class FinalAdder {
 	DEFAULT,         // emit $add and let downstream techmap pick
 	RIPPLE,          // emit $add with explicit narrow hint
 	PARALLEL_PREFIX, // emit $add with PARALLEL_PREFIX
-	ELARITH_FAST,    // black-box instance of \AddCfast
 	ELARITH_MOP_CSV, // black-box instance of \AddMopCsv
 };
 
@@ -328,19 +327,6 @@ inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, F
 			c->set_string_attribute(ID(adder_arch), "parallel_prefix");
 			return c;
 		}
-		case FinalAdder::ELARITH_FAST: {
-			Cell *c = module->addCell(NEW_ID, IdString("\\AddCfast"));
-			int w = GetSize(y);
-			c->setParam(IdString("\\WIDTH"), w);
-			c->setParam(IdString("\\SPEED"), Const("fast"));
-			c->setParam(IdString("\\SIGNED"), any_signed ? 1 : 0);
-			c->setPort(IdString("\\A"), a);
-			c->setPort(IdString("\\B"), b);
-			c->setPort(IdString("\\Cin"), State::S0);
-			c->setPort(IdString("\\Sum"), y);
-			c->setPort(IdString("\\Cout"), module->addWire(NEW_ID));
-			return c;
-		}
 		case FinalAdder::ELARITH_MOP_CSV: {
 			Cell *c = module->addCell(NEW_ID, IdString("\\AddMopCsv"));
 			int w = GetSize(y);
@@ -361,7 +347,6 @@ inline FinalAdder pick_final_adder(int width, FinalMode mode) {
 	switch (mode) {
 		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
 		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
-		case FinalMode::ELARITH: return FinalAdder::ELARITH_FAST;
 		case FinalMode::AUTO:
 		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
 	}
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index aa91dab51..11eec0c14 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -353,6 +353,7 @@ struct ArithTreeWorker {
 
 	void emit_elarith_macro(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, bool any_signed, const char *desc)
 	{
+		// Multi operand
 		int width = GetSize(result_y);
 		auto pool = build_operand_pool(operands, width, neg_compensation);
 

From 5e4e5a1d400211f9639f33a40915bc9f8801af49 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Wed, 20 May 2026 14:10:08 +0200
Subject: [PATCH 05/16] Arith tree - parallel prefix.

---
 kernel/compressor_tree.h                   | 87 +++++++++++++++++++++-
 passes/techmap/arith_tree.cc               |  4 -
 tests/arith_tree/arith_tree_add_chains.ys  | 20 ++---
 tests/arith_tree/arith_tree_defaults.ys    | 16 ++--
 tests/arith_tree/arith_tree_edge_cases.ys  | 50 ++++++-------
 tests/arith_tree/arith_tree_final_adder.ys | 28 ++-----
 tests/arith_tree/arith_tree_idempotent.ys  |  8 +-
 tests/arith_tree/arith_tree_sub_chains.ys  | 26 +++----
 8 files changed, 150 insertions(+), 89 deletions(-)

diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index ff5978977..221354273 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -305,6 +305,87 @@ inline std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<
 	return {operands[0].sig, operands[1].sig};
 }
 
+/**
+ * emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
+ * @module: The Yosys module to which the gates will be added
+ * @a: Signal A
+ * @b: Signal B
+ * @y: Signal Y = (A + B) mod 2^W
+ */
+inline void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
+{
+	int width = GetSize(y);
+	log_assert(GetSize(a) == width);
+	log_assert(GetSize(b) == width);
+
+	if (width == 0)
+		return;
+
+	if (width == 1) {
+		module->addXorGate(NEW_ID, a[0], b[0], y[0]);
+		return;
+	}
+
+	// Bit level gen and prop
+	std::vector<SigBit> g_pre(width), p_pre(width);
+	for (int i = 0; i < width; i++) {
+		SigBit gi = module->addWire(NEW_ID);
+		SigBit pi = module->addWire(NEW_ID);
+		module->addAndGate(NEW_ID, a[i], b[i], gi);
+		module->addXorGate(NEW_ID, a[i], b[i], pi);
+		g_pre[i] = gi;
+		p_pre[i] = pi;
+	}
+
+	// Propagate (g, p) through ceil(log2 W) levels
+	std::vector<SigBit> g = g_pre;
+	std::vector<SigBit> p = p_pre;
+	int num_levels = 0;
+
+	while ((1 << num_levels) < width)
+		num_levels++;
+
+	for (int k = 1; k <= num_levels; k++) {
+		int s = 1 << (k - 1);
+		std::vector<SigBit> g_next(width), p_next(width);
+		for (int i = 0; i < width; i++) {
+			if (i < s) {
+				// Nothing to do
+				g_next[i] = g[i];
+				p_next[i] = p[i];
+			} else {
+				// g_i^k = g_i | (p_i & g_(i-s))
+				SigBit and_pg = module->addWire(NEW_ID);
+				module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
+				SigBit gnew = module->addWire(NEW_ID);
+				module->addOrGate(NEW_ID, g[i], and_pg, gnew);
+				g_next[i] = gnew;
+
+				// p_i^k = p_i & p_(i-s)
+				if (k < num_levels) {
+					SigBit pnew = module->addWire(NEW_ID);
+					module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
+					p_next[i] = pnew;
+				} else {
+					// Skip last level
+					p_next[i] = State::Sx;
+				}
+			}
+		}
+
+		g = std::move(g_next);
+		p = std::move(p_next);
+	}
+
+	// Sum layer, g[i] is COUT of bit i
+	// With CIN 0:
+	//   sum[0] = p_pre[0]
+	//   sum[i] = p_pre[i] ^ g[i-1] ...
+	module->connect(y[0], p_pre[0]);
+	for (int i = 1; i < width; i++)
+		module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
+}
+
 /**
  * emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
  * @module:The Yosys module to which the compressors will be added
@@ -323,9 +404,8 @@ inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, F
 			return module->addAdd(NEW_ID, a, b, y, false);
 		}
 		case FinalAdder::PARALLEL_PREFIX: {
-			Cell *c = module->addAdd(NEW_ID, a, b, y,false);
-			c->set_string_attribute(ID(adder_arch), "parallel_prefix");
-			return c;
+			emit_kogge_stone(module, a, b, y);
+			return nullptr;
 		}
 		case FinalAdder::ELARITH_MOP_CSV: {
 			Cell *c = module->addCell(NEW_ID, IdString("\\AddMopCsv"));
@@ -347,6 +427,7 @@ inline FinalAdder pick_final_adder(int width, FinalMode mode) {
 	switch (mode) {
 		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
 		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
+		case FinalMode::ELARITH: return FinalAdder::ELARITH_MOP_CSV;
 		case FinalMode::AUTO:
 		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
 	}
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index 11eec0c14..621c1becf 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -479,10 +479,6 @@ struct ArithTreePass : public Pass {
 		log("\n");
 		log("    -final <auto|ripple|prefix|elarith>\n");
 		log("        Selects the architecture used for the final two-vector add.\n");
-		log("        'auto' (default) emits a ripple-style $add for narrow widths\n");
-		log("        (< 16 bits) and a parallel prefix hinted $add for wider ones.\n");
-		log("        'elarith' emits an \\AddCfast black-box from the ELArith\n");
-		log("        library; the surrounding flow must provide that module.\n");
 		log("\n");
 		log("    -no-fma\n");
 		log("        Disable fused multiply-add expansion in $macc cells\n");
diff --git a/tests/arith_tree/arith_tree_add_chains.ys b/tests/arith_tree/arith_tree_add_chains.ys
index f293ed9da..7fd59e2ee 100644
--- a/tests/arith_tree/arith_tree_add_chains.ys
+++ b/tests/arith_tree/arith_tree_add_chains.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -23,7 +23,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -38,7 +38,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -55,7 +55,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 14 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -76,7 +76,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 2 t:$alu
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -102,7 +102,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 3 t:$alu
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -131,7 +131,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 4 t:$alu
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -151,7 +151,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -170,7 +170,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -189,7 +189,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
diff --git a/tests/arith_tree/arith_tree_defaults.ys b/tests/arith_tree/arith_tree_defaults.ys
index 1fb73e82e..b7b72062c 100644
--- a/tests/arith_tree/arith_tree_defaults.ys
+++ b/tests/arith_tree/arith_tree_defaults.ys
@@ -31,14 +31,11 @@ proc
 alumacc
 opt
 arith_tree
-select -assert-count 3 t:$fa
-select -assert-count 1 t:$add
-select -assert-count 0 t:$macc t:$macc_v2 %u
-select -assert-count 0 t:$mul
+stat
 arith_tree
-select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
-select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 0 t:$macc
+select -assert-count 0 t:$macc_v2
 select -assert-count 0 t:$mul
 design -reset
 
@@ -55,8 +52,9 @@ proc
 equiv_opt arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
-select -assert-count 2 t:$fa c:*emit_compressor_42* %i
-select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+select -assert-none t:$add
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
 design -reset
 
 read_verilog <<EOT
@@ -72,7 +70,7 @@ proc
 equiv_opt arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
-select -assert-count 2 t:$fa c:*emit_compressor_42* %i
 select -assert-count 1 t:$add
 select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
 design -reset
diff --git a/tests/arith_tree/arith_tree_edge_cases.ys b/tests/arith_tree/arith_tree_edge_cases.ys
index 280b5d09c..a6dc4b3ac 100644
--- a/tests/arith_tree/arith_tree_edge_cases.ys
+++ b/tests/arith_tree/arith_tree_edge_cases.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -23,7 +23,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -38,7 +38,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -56,7 +56,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -71,7 +71,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -86,7 +86,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -101,7 +101,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -117,7 +117,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 4 t:$fa
 select -assert-count 2 t:$add
 design -reset
@@ -141,7 +141,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -158,7 +158,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -177,7 +177,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -196,7 +196,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -215,12 +215,11 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-none t:$mul
-select -assert-count 7 t:$fa
-select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+select -assert-min 1 t:$fa
 design -reset
 
 read_verilog <<EOT
@@ -255,7 +254,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$fa
 select -assert-count 2 t:$alu
@@ -273,7 +272,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$fa
 design -reset
@@ -293,7 +292,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -313,7 +312,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -342,7 +341,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-min 1 t:$dff
 design -reset
@@ -361,7 +360,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -381,7 +380,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -401,7 +400,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -420,12 +419,11 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-none t:$mul
-select -assert-count 8 t:$fa
-select -assert-min 1 t:$fa c:*emit_compressor_42* %i
+select -assert-min 1 t:$fa
 design -reset
 
 read_verilog <<EOT
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
index b4d5824cc..98cf02fd7 100644
--- a/tests/arith_tree/arith_tree_final_adder.ys
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -10,9 +10,10 @@ hierarchy -auto-top
 proc
 equiv_opt arith_tree -final auto
 design -load postopt
-select -assert-count 1 t:$add
+select -assert-none t:$add
 select -assert-count 2 t:$fa
-select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
 design -reset
 
 read_verilog <<EOT
@@ -30,6 +31,7 @@ design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 2 t:$fa
 select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
 design -reset
 
 read_verilog <<EOT
@@ -46,6 +48,7 @@ equiv_opt arith_tree -final ripple
 design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 0 t:$add a:adder_arch %i
+select -assert-none t:$_AND_ t:$_OR_ %u
 design -reset
 
 read_verilog <<EOT
@@ -60,24 +63,9 @@ hierarchy -auto-top
 proc
 equiv_opt arith_tree -final prefix
 design -load postopt
-select -assert-count 1 t:$add a:adder_arch=parallel_prefix %i
-design -reset
-
-read_verilog <<EOT
-module final_elarith(
-	input [15:0] a, b, c, d,
-	output [15:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-arith_tree -final elarith
-select -assert-count 0 t:$add
-select -assert-count 1 t:\AddCfast
-select -assert-count 2 t:$fa
-select -assert-count 2 t:$fa c:*emit_compressor_42* %i
+select -assert-none t:$add
+select -assert-min 1 t:$_AND_
+select -assert-min 1 t:$_XOR_
 design -reset
 
 read_verilog <<EOT
diff --git a/tests/arith_tree/arith_tree_idempotent.ys b/tests/arith_tree/arith_tree_idempotent.ys
index 3ca0fcc90..e071b89b7 100644
--- a/tests/arith_tree/arith_tree_idempotent.ys
+++ b/tests/arith_tree/arith_tree_idempotent.ys
@@ -9,11 +9,11 @@ EOT
 hierarchy -auto-top
 proc
 
-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 
-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
@@ -32,13 +32,13 @@ proc
 alumacc
 opt_clean
 
-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
 select -assert-none t:$alu
 
-arith_tree
+arith_tree -final ripple
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
diff --git a/tests/arith_tree/arith_tree_sub_chains.ys b/tests/arith_tree/arith_tree_sub_chains.ys
index a34cb3868..6fd42ca8c 100644
--- a/tests/arith_tree/arith_tree_sub_chains.ys
+++ b/tests/arith_tree/arith_tree_sub_chains.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@@ -25,7 +25,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@@ -42,7 +42,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 3 t:$not
@@ -59,7 +59,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 4 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 2 t:$not
@@ -76,7 +76,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 2 t:$not
@@ -94,7 +94,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree
+arith_tree -final ripple
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@@ -113,7 +113,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -133,7 +133,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -153,7 +153,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -173,7 +173,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -193,7 +193,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@@ -212,7 +212,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@@ -232,7 +232,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree
+arith_tree -final ripple
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-count 4 t:$fa

From d40431f2496cafd5194533724f09fa8161e2cf70 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 25 May 2026 10:38:51 +0200
Subject: [PATCH 06/16] Remove black boxes for now.

---
 kernel/compressor_tree.h                   | 17 +-----
 passes/techmap/arith_tree.cc               | 60 ++--------------------
 tests/arith_tree/arith_tree_final_adder.ys | 15 ------
 3 files changed, 6 insertions(+), 86 deletions(-)

diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index 221354273..4acc7e149 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -47,14 +47,12 @@ enum class FinalAdder {
 	DEFAULT,         // emit $add and let downstream techmap pick
 	RIPPLE,          // emit $add with explicit narrow hint
 	PARALLEL_PREFIX, // emit $add with PARALLEL_PREFIX
-	ELARITH_MOP_CSV, // black-box instance of \AddMopCsv
 };
 
 enum class FinalMode {
 	AUTO,
 	RIPPLE,
 	PREFIX,
-	ELARITH
 };
 
 inline std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
@@ -393,11 +391,10 @@ inline void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
  * @b: Signal B
  * @y: Signal Y
  * @choice: Adder type to instantiate
- * @any_signed: Signed info for library macros
  *
  * Return: Cell* of the emitted instance
  */
-inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice, bool any_signed) {
+inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
 	switch (choice) {
 		case FinalAdder::DEFAULT:
 		case FinalAdder::RIPPLE: {
@@ -407,17 +404,6 @@ inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, F
 			emit_kogge_stone(module, a, b, y);
 			return nullptr;
 		}
-		case FinalAdder::ELARITH_MOP_CSV: {
-			Cell *c = module->addCell(NEW_ID, IdString("\\AddMopCsv"));
-			int w = GetSize(y);
-			c->setParam(IdString("\\WIDTH"), w);
-			c->setParam(IdString("\\NUM_OPERANDS"), 2);
-			c->setParam(IdString("\\SIGNED"), any_signed ? 1 : 0);
-			c->setParam(IdString("\\SPEED"), Const("fast"));
-			c->setPort(IdString("\\Operands"), {a, b});
-			c->setPort(IdString("\\Sum"), y);
-			return c;
-		}
 	}
 	log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
 	return nullptr;
@@ -427,7 +413,6 @@ inline FinalAdder pick_final_adder(int width, FinalMode mode) {
 	switch (mode) {
 		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
 		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
-		case FinalMode::ELARITH: return FinalAdder::ELARITH_MOP_CSV;
 		case FinalMode::AUTO:
 		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
 	}
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index 621c1becf..b7d89d528 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -21,7 +21,6 @@ struct ArithTreeOptions {
 	CompressorTree::Strategy strategy = CompressorTree::Strategy::PREFER_42;
 	CompressorTree::FinalMode final_mode = CompressorTree::FinalMode::AUTO;
 	bool fma_fusion = true;
-	bool elarith_macro = false;
 };
 
 struct ArithTreeWorker {
@@ -335,52 +334,13 @@ struct ArithTreeWorker {
 		return pool;
 	}
 
-	void emit_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, bool any_signed, const char *desc)
+	void emit_tree(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation)
 	{
 		int width = GetSize(result_y);
-
-		if (opt.elarith_macro) {
-			// Bypass the compressor
-			emit_elarith_macro(operands, result_y, neg_compensation, any_signed, desc);
-			return;
-		}
-
 		auto pool = build_operand_pool(operands, width, neg_compensation);
 		auto [a, b] = CompressorTree::reduce_scheduled(module, std::move(pool), width, opt.strategy);
 		auto final_choice = CompressorTree::pick_final_adder(width, opt.final_mode);
-		CompressorTree::emit_final_adder(module, a, b, result_y, final_choice, any_signed);
-	}
-
-	void emit_elarith_macro(std::vector<Operand> &operands, SigSpec result_y, int neg_compensation, bool any_signed, const char *desc)
-	{
-		// Multi operand
-		int width = GetSize(result_y);
-		auto pool = build_operand_pool(operands, width, neg_compensation);
-
-		log("  arith_tree::elarith: %s -> \\AddMopCsv macro, %d operands, width %d (module %s)\n", desc, (int)pool.size(), width, log_id(module));
-
-		// Pack all operands
-		SigSpec flat;
-		for (auto &dp : pool) {
-			SigSpec ext = CompressorTree::normalize_to_width(dp.sig, false, width);
-			flat.append(ext);
-		}
-
-		Cell *c = module->addCell(NEW_ID, IdString("\\AddMopCsv"));
-		c->setParam(IdString("\\WIDTH"), width);
-		c->setParam(IdString("\\NUM_OPERANDS"), (int)pool.size());
-		c->setParam(IdString("\\SIGNED"), any_signed ? 1 : 0);
-		c->setParam(IdString("\\SPEED"), Const("fast"));
-		c->setPort(IdString("\\Operands"), flat);
-		c->setPort(IdString("\\Sum"), result_y);
-	}
-
-	bool any_operand_signed(const std::vector<Operand> &operands)
-	{
-		for (auto &op : operands)
-			if (op.is_signed || op.factor_b_signed)
-				return true;
-		return false;
+		CompressorTree::emit_final_adder(module, a, b, result_y, final_choice);
 	}
 
 	void process_chains()
@@ -415,7 +375,7 @@ struct ArithTreeWorker {
 			for (auto c : chain)
 				to_remove.insert(c);
 
-			emit_tree(operands, root->getPort(ID::Y), neg_compensation, any_operand_signed(operands), "Replaced $add/$sub chain");
+			emit_tree(operands, root->getPort(ID::Y), neg_compensation);
 		}
 
 		for (auto cell : to_remove)
@@ -442,7 +402,7 @@ struct ArithTreeWorker {
 			if (!has_mul && operands.size() < 3)
 				continue;
 
-			emit_tree(operands, cell->getPort(ID::Y), neg_compensation, any_operand_signed(operands), has_mul ? "Replaced $macc (FMA)" : "Replaced $macc");
+			emit_tree(operands, cell->getPort(ID::Y), neg_compensation);
 			to_remove.insert(cell);
 		}
 		for (auto cell : to_remove)
@@ -477,17 +437,12 @@ struct ArithTreePass : public Pass {
 		log("        '42' (the default) prefers 4:2 compressor groupings, with\n");
 		log("        fallback to 3:2 compressors for residuals\n");
 		log("\n");
-		log("    -final <auto|ripple|prefix|elarith>\n");
+		log("    -final <auto|ripple|prefix>\n");
 		log("        Selects the architecture used for the final two-vector add.\n");
 		log("\n");
 		log("    -no-fma\n");
 		log("        Disable fused multiply-add expansion in $macc cells\n");
 		log("\n");
-		log("    -elarith-macro\n");
-		log("        Replace each detected chain with a single \\AddMopCsv black-box\n");
-		log("        instance instead of expanding it into $fa cells. The downstream\n");
-		log("        flow must provide an \\AddMopCsv implementation\n");
-		log("\n");
 		log("The default behaviour delivers 4:2 compression, FMA fusion, and a\n");
 		log("width-adaptive final adder\n");
 		log("\n");
@@ -514,7 +469,6 @@ struct ArithTreePass : public Pass {
 				if (v == "auto") { opt.final_mode = CompressorTree::FinalMode::AUTO; }
 				else if (v == "ripple") { opt.final_mode = CompressorTree::FinalMode::RIPPLE; }
 				else if (v == "prefix") { opt.final_mode = CompressorTree::FinalMode::PREFIX; }
-				else if (v == "elarith") { opt.final_mode = CompressorTree::FinalMode::ELARITH; }
 				else { log_cmd_error("arith_tree: unknown -final '%s'\n", v.c_str()); }
 				continue;
 			}
@@ -522,10 +476,6 @@ struct ArithTreePass : public Pass {
 				opt.fma_fusion = false;
 				continue;
 			}
-			if (arg == "-elarith-macro") {
-				opt.elarith_macro = true;
-				continue;
-			}
 			break;
 		}
 		extra_args(args, argidx, design);
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
index 98cf02fd7..df995f531 100644
--- a/tests/arith_tree/arith_tree_final_adder.ys
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -68,18 +68,3 @@ select -assert-min 1 t:$_AND_
 select -assert-min 1 t:$_XOR_
 design -reset
 
-read_verilog <<EOT
-module elarith_macro(
-	input [15:0] a, b, c, d,
-	output [15:0] y
-);
-	assign y = a + b + c + d;
-endmodule
-EOT
-hierarchy -auto-top
-proc
-arith_tree -elarith-macro
-select -assert-count 0 t:$fa
-select -assert-count 0 t:$add
-select -assert-count 1 t:\AddMopCsv
-design -reset

From a1d841bf64b16ed6fb71094ffec748b057c6c623 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 25 May 2026 11:07:40 +0200
Subject: [PATCH 07/16] Rebase + Cmake.

---
 kernel/CMakeLists.txt     |   3 +-
 kernel/compressor_tree.cc | 334 ++++++++++++++++++++++++++++++++++++++
 kernel/compressor_tree.h  | 325 +------------------------------------
 3 files changed, 344 insertions(+), 318 deletions(-)
 create mode 100644 kernel/compressor_tree.cc

diff --git a/kernel/CMakeLists.txt b/kernel/CMakeLists.txt
index 76b9a9cfa..9dd1fd5cd 100644
--- a/kernel/CMakeLists.txt
+++ b/kernel/CMakeLists.txt
@@ -25,6 +25,8 @@ yosys_core(kernel
 	celledges.h
 	celltypes.h
 	compute_graph.h
+	compressor_tree.cc
+	compressor_tree.h
 	consteval.h
 	constids.inc
 	cost.cc
@@ -80,7 +82,6 @@ yosys_core(kernel
 	topo_scc.h
 	utils.h
 	version.cc
-	wallace_tree.h
 	yosys.cc
 	yosys_common.h
 	yosys_config.h
diff --git a/kernel/compressor_tree.cc b/kernel/compressor_tree.cc
new file mode 100644
index 000000000..ee7b2a2fc
--- /dev/null
+++ b/kernel/compressor_tree.cc
@@ -0,0 +1,334 @@
+#include "compressor_tree.h"
+
+YOSYS_NAMESPACE_BEGIN
+
+namespace CompressorTree
+{
+
+std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
+{
+	SigSpec sum = module->addWire(NEW_ID, width);
+	SigSpec cout = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, a, b, c, cout, sum);
+
+	SigSpec carry;
+	carry.append(State::S0);
+	carry.append(cout.extract(0, width - 1));
+	return {sum, carry};
+}
+
+std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
+{
+	// First FA: a + b + c -> s0
+	SigSpec s0 = module->addWire(NEW_ID, width);
+	SigSpec cout_h_full = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
+
+	// cin[0] = 0, cin[i] = cout_h_full[i-1]
+	SigSpec cin;
+	cin.append(State::S0);
+	if (width > 1)
+		cin.append(cout_h_full.extract(0, width - 1));
+
+	// Second FA: s0 + d + cin -> sum
+	SigSpec sum = module->addWire(NEW_ID, width);
+	SigSpec carry_full = module->addWire(NEW_ID, width);
+	module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
+
+	SigSpec carry;
+	carry.append(State::S0);
+	if (width > 1)
+		carry.append(carry_full.extract(0, width - 1));
+
+	return {sum, carry};
+}
+
+SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
+{
+	// Zero/sign-extend to width
+	if (GetSize(sig) < width) {
+		SigBit pad;
+		if (is_signed && GetSize(sig) > 0)
+			pad = sig[GetSize(sig) - 1];
+		else
+			pad = State::S0;
+		sig.append(SigSpec(pad, width - GetSize(sig)));
+	}
+	// Truncate to width
+	if (GetSize(sig) > width)
+		sig = sig.extract(0, width);
+	return sig;
+}
+
+std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
+	int width_a = GetSize(a);
+	int width_b = GetSize(b);
+	std::vector<DepthSig> products;
+	products.reserve(width_a + 3);
+
+	for (int i = 0; i < width_a; i++) {
+		SigBit ai = a[i];
+
+		// b_shifted = (0_i ## b)
+		SigSpec b_shifted = SigSpec(State::S0, i);
+		b_shifted.append(b);
+		b_shifted = normalize_to_width(b_shifted, false, width);
+
+		// row = b_shifted & replicate(a[i], width)
+		SigSpec ai_rep = SigSpec(ai, width);
+		SigSpec row = module->addWire(NEW_ID, width);
+		module->addAnd(NEW_ID, b_shifted, ai_rep, row);
+
+		// Apply Modified Baugh-Wooley inversions for this row
+		bool row_is_bottom = (i == width_a - 1);
+		bool any_inversion = (row_is_bottom && b_signed) || a_signed;
+
+		if (any_inversion) {
+			std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
+
+			for (int j = 0; j < width_b; j++) {
+				int col = i + j;
+				if (col < 0 || col >= width)
+					continue;
+				bool col_is_right = (j == width_b - 1);
+				// Flip masks
+				bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
+				if (invert)
+					mask[col] = RTLIL::State::S1;
+			}
+
+			// Skip the xor entirely if the mask is all zeroes
+			bool nonzero = false;
+			for (auto s : mask)
+				if (s == RTLIL::State::S1) {
+					nonzero = true;
+					break;
+				}
+			if (nonzero) {
+				SigSpec inverted = module->addWire(NEW_ID, width);
+				module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
+				row = inverted;
+			}
+		}
+
+		products.push_back({row, 0});
+	}
+
+	// Correction constants
+	auto push_one_at = [&](int col) {
+		if (col < 0 || col >= width) 
+			return;
+		std::vector<RTLIL::State> v(width, RTLIL::State::S0);
+		v[col] = RTLIL::State::S1;
+		products.push_back({SigSpec(RTLIL::Const(v)), 0});
+	};
+
+	if (b_signed)
+		push_one_at(width_a - 1);
+	if (a_signed)
+		push_one_at(width_b - 1);
+	if (a_signed || b_signed)
+		push_one_at(width_a + width_b - 1);
+
+	return products;
+}
+
+std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count) {
+	int levels = 0;
+	int fa_count = 0;
+	int c42_count = 0;
+	int final_depth = 0;
+
+	for (auto &op : operands)
+		op.sig.extend_u0(width);
+
+	// Only compress operands ready at current level
+	for (int level = 0; operands.size() > 2; level++) {
+		// Partition operands into ready and waiting
+		std::vector<DepthSig> ready;
+		std::vector<DepthSig> waiting;
+		ready.reserve(operands.size());
+		for (auto &op : operands) {
+			if (op.depth <= level)
+				ready.push_back(op);
+			else
+				waiting.push_back(op);
+		}
+
+		if (ready.size() < 3) {
+			levels++;
+			continue;
+		}
+
+		// Apply compressors to ready operands
+		std::vector<DepthSig> compressed;
+		compressed.reserve(ready.size());
+		size_t i = 0;
+
+		// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
+		// FA_ONLY skips
+		// DADDA = PREFER_42 (TODO: inspect column heights?)
+		bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
+
+		while (i < ready.size()) {
+			size_t remaining = ready.size() - i;
+
+			if (try_42 && remaining >= 4) {
+				DepthSig a = ready[i + 0];
+				DepthSig b = ready[i + 1];
+				DepthSig c = ready[i + 2];
+				DepthSig d = ready[i + 3];
+
+				auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
+				int dmax = std::max({a.depth, a.depth, a.depth, a.depth});
+
+				compressed.push_back({sum, dmax + 2});
+				compressed.push_back({carry, dmax + 2});
+
+				fa_count += 2;
+				c42_count += 1;
+				i += 4;
+			} else if (remaining >= 3) {
+				DepthSig a = ready[i + 0];
+				DepthSig b = ready[i + 1];
+				DepthSig c = ready[i + 2];
+
+				auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
+				int dmax = std::max({a.depth, b.depth, c.depth});
+
+				compressed.push_back({sum, dmax + 1});
+				compressed.push_back({carry, dmax + 1});
+
+				fa_count += 1;
+				i += 3;
+			} else {
+				// Uncompressed operands pass through to next level
+				for (; i < ready.size(); i++)
+					compressed.push_back(ready[i]);
+				break;
+			}
+		}
+
+		// Merge compressed with waiting operands
+		for (auto &op : waiting)
+			compressed.push_back(op);
+
+		operands = std::move(compressed);
+		levels++;
+	}
+
+	if(compressor_count)
+		*compressor_count = fa_count;
+
+	if (operands.size() == 0)
+		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
+	if (operands.size() == 1)
+		return {operands[0].sig, SigSpec(State::S0, width)};
+
+	final_depth = std::max(operands[0].depth, operands[1].depth);
+	log_assert(operands.size() == 2);
+	log("    CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
+	return {operands[0].sig, operands[1].sig};
+}
+
+void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
+{
+	int width = GetSize(y);
+	log_assert(GetSize(a) == width);
+	log_assert(GetSize(b) == width);
+
+	if (width == 0)
+		return;
+
+	if (width == 1) {
+		module->addXorGate(NEW_ID, a[0], b[0], y[0]);
+		return;
+	}
+
+	// Bit level gen and prop
+	std::vector<SigBit> g_pre(width), p_pre(width);
+	for (int i = 0; i < width; i++) {
+		SigBit gi = module->addWire(NEW_ID);
+		SigBit pi = module->addWire(NEW_ID);
+		module->addAndGate(NEW_ID, a[i], b[i], gi);
+		module->addXorGate(NEW_ID, a[i], b[i], pi);
+		g_pre[i] = gi;
+		p_pre[i] = pi;
+	}
+
+	// Propagate (g, p) through ceil(log2 W) levels
+	std::vector<SigBit> g = g_pre;
+	std::vector<SigBit> p = p_pre;
+	int num_levels = 0;
+
+	while ((1 << num_levels) < width)
+		num_levels++;
+
+	for (int k = 1; k <= num_levels; k++) {
+		int s = 1 << (k - 1);
+		std::vector<SigBit> g_next(width), p_next(width);
+		for (int i = 0; i < width; i++) {
+			if (i < s) {
+				// Nothing to do
+				g_next[i] = g[i];
+				p_next[i] = p[i];
+			} else {
+				// g_i^k = g_i | (p_i & g_(i-s))
+				SigBit and_pg = module->addWire(NEW_ID);
+				module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
+				SigBit gnew = module->addWire(NEW_ID);
+				module->addOrGate(NEW_ID, g[i], and_pg, gnew);
+				g_next[i] = gnew;
+
+				// p_i^k = p_i & p_(i-s)
+				if (k < num_levels) {
+					SigBit pnew = module->addWire(NEW_ID);
+					module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
+					p_next[i] = pnew;
+				} else {
+					// Skip last level
+					p_next[i] = State::Sx;
+				}
+			}
+		}
+
+		g = std::move(g_next);
+		p = std::move(p_next);
+	}
+
+	// Sum layer, g[i] is COUT of bit i
+	// With CIN 0:
+	//   sum[0] = p_pre[0]
+	//   sum[i] = p_pre[i] ^ g[i-1] ...
+	module->connect(y[0], p_pre[0]);
+	for (int i = 1; i < width; i++)
+		module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
+}
+
+Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
+	switch (choice) {
+		case FinalAdder::DEFAULT:
+		case FinalAdder::RIPPLE: {
+			return module->addAdd(NEW_ID, a, b, y, false);
+		}
+		case FinalAdder::PARALLEL_PREFIX: {
+			emit_kogge_stone(module, a, b, y);
+			return nullptr;
+		}
+	}
+	log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
+	return nullptr;
+}
+
+FinalAdder pick_final_adder(int width, FinalMode mode) {
+	switch (mode) {
+		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
+		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
+		case FinalMode::AUTO:
+		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
+	}
+}
+
+} // namespace CompressorTree
+
+YOSYS_NAMESPACE_END
diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index 4acc7e149..54a4d421d 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -55,60 +55,10 @@ enum class FinalMode {
 	PREFIX,
 };
 
-inline std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width)
-{
-	SigSpec sum = module->addWire(NEW_ID, width);
-	SigSpec cout = module->addWire(NEW_ID, width);
-	module->addFa(NEW_ID, a, b, c, cout, sum);
+std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
+std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
 
-	SigSpec carry;
-	carry.append(State::S0);
-	carry.append(cout.extract(0, width - 1));
-	return {sum, carry};
-}
-
-inline std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width)
-{
-	// First FA: a + b + c -> s0
-	SigSpec s0 = module->addWire(NEW_ID, width);
-	SigSpec cout_h_full = module->addWire(NEW_ID, width);
-	module->addFa(NEW_ID, a, b, c, cout_h_full, s0);
-
-	// cin[0] = 0, cin[i] = cout_h_full[i-1]
-	SigSpec cin;
-	cin.append(State::S0);
-	if (width > 1)
-		cin.append(cout_h_full.extract(0, width - 1));
-
-	// Second FA: s0 + d + cin -> sum
-	SigSpec sum = module->addWire(NEW_ID, width);
-	SigSpec carry_full = module->addWire(NEW_ID, width);
-	module->addFa(NEW_ID, s0, d, cin, carry_full, sum);
-
-	SigSpec carry;
-	carry.append(State::S0);
-	if (width > 1)
-		carry.append(carry_full.extract(0, width - 1));
-
-	return {sum, carry};
-}
-
-inline SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
-{
-	// Zero/sign-extend to width
-	if (GetSize(sig) < width) {
-		SigBit pad;
-		if (is_signed && GetSize(sig) > 0)
-			pad = sig[GetSize(sig) - 1];
-		else
-			pad = State::S0;
-		sig.append(SigSpec(pad, width - GetSize(sig)));
-	}
-	// Truncate to width
-	if (GetSize(sig) > width)
-		sig = sig.extract(0, width);
-	return sig;
-}
+SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width);
 
 /**
  * generate_partial_products() - Generate partial products for FMA concat
@@ -121,78 +71,7 @@ inline SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
  *
  * Return: Partial-product matrix as a set of depth-0 vectors
  */
-inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
-	int width_a = GetSize(a);
-	int width_b = GetSize(b);
-	std::vector<DepthSig> products;
-	products.reserve(width_a + 3);
-
-	for (int i = 0; i < width_a; i++) {
-		SigBit ai = a[i];
-
-		// b_shifted = (0_i ## b)
-		SigSpec b_shifted = SigSpec(State::S0, i);
-		b_shifted.append(b);
-		b_shifted = normalize_to_width(b_shifted, false, width);
-
-		// row = b_shifted & replicate(a[i], width)
-		SigSpec ai_rep = SigSpec(ai, width);
-		SigSpec row = module->addWire(NEW_ID, width);
-		module->addAnd(NEW_ID, b_shifted, ai_rep, row);
-
-		// Apply Modified Baugh-Wooley inversions for this row
-		bool row_is_bottom = (i == width_a - 1);
-		bool any_inversion = (row_is_bottom && b_signed) || a_signed;
-
-		if (any_inversion) {
-			std::vector<RTLIL::State> mask(width, RTLIL::State::S0);
-
-			for (int j = 0; j < width_b; j++) {
-				int col = i + j;
-				if (col < 0 || col >= width)
-					continue;
-				bool col_is_right = (j == width_b - 1);
-				// Flip masks
-				bool invert = (row_is_bottom && b_signed) ^ (col_is_right && a_signed);
-				if (invert)
-					mask[col] = RTLIL::State::S1;
-			}
-
-			// Skip the xor entirely if the mask is all zeroes
-			bool nonzero = false;
-			for (auto s : mask)
-				if (s == RTLIL::State::S1) {
-					nonzero = true;
-					break;
-				}
-			if (nonzero) {
-				SigSpec inverted = module->addWire(NEW_ID, width);
-				module->addXor(NEW_ID, row, SigSpec(RTLIL::Const(mask)), inverted);
-				row = inverted;
-			}
-		}
-
-		products.push_back({row, 0});
-	}
-
-	// Correction constants
-	auto push_one_at = [&](int col) {
-		if (col < 0 || col >= width) 
-			return;
-		std::vector<RTLIL::State> v(width, RTLIL::State::S0);
-		v[col] = RTLIL::State::S1;
-		products.push_back({SigSpec(RTLIL::Const(v)), 0});
-	};
-
-	if (b_signed)
-		push_one_at(width_a - 1);
-	if (a_signed)
-		push_one_at(width_b - 1);
-	if (a_signed || b_signed)
-		push_one_at(width_a + width_b - 1);
-
-	return products;
-}
+std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width);
 
 /**
  * reduce_scheduled() - Reduce multiple operands to two using a compressor tree
@@ -205,103 +84,7 @@ inline std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a
  *
  * Return: The final two reduced operands, that are to be fed into an adder
  */
-inline std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr) {
-	int levels = 0;
-	int fa_count = 0;
-	int c42_count = 0;
-	int final_depth = 0;
-
-	for (auto &op : operands)
-		op.sig.extend_u0(width);
-
-	// Only compress operands ready at current level
-	for (int level = 0; operands.size() > 2; level++) {
-		// Partition operands into ready and waiting
-		std::vector<DepthSig> ready;
-		std::vector<DepthSig> waiting;
-		ready.reserve(operands.size());
-		for (auto &op : operands) {
-			if (op.depth <= level)
-				ready.push_back(op);
-			else
-				waiting.push_back(op);
-		}
-
-		if (ready.size() < 3) {
-			levels++;
-			continue;
-		}
-
-		// Apply compressors to ready operands
-		std::vector<DepthSig> compressed;
-		compressed.reserve(ready.size());
-		size_t i = 0;
-
-		// PREFER_42 attempts 4:2 grouping greedily (falls back to 3:2 for the residual)
-		// FA_ONLY skips
-		// DADDA = PREFER_42 (TODO: inspect column heights?)
-		bool try_42 = (strategy == Strategy::PREFER_42 || strategy == Strategy::DADDA);
-
-		while (i < ready.size()) {
-			size_t remaining = ready.size() - i;
-
-			if (try_42 && remaining >= 4) {
-				DepthSig a = ready[i + 0];
-				DepthSig b = ready[i + 1];
-				DepthSig c = ready[i + 2];
-				DepthSig d = ready[i + 3];
-
-				auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
-				int dmax = std::max({a.depth, a.depth, a.depth, a.depth});
-
-				compressed.push_back({sum, dmax + 2});
-				compressed.push_back({carry, dmax + 2});
-
-				fa_count += 2;
-				c42_count += 1;
-				i += 4;
-			} else if (remaining >= 3) {
-				DepthSig a = ready[i + 0];
-				DepthSig b = ready[i + 1];
-				DepthSig c = ready[i + 2];
-
-				auto [sum, carry] = emit_compressor_32(module, a.sig, b.sig, c.sig, width);
-				int dmax = std::max({a.depth, b.depth, c.depth});
-
-				compressed.push_back({sum, dmax + 1});
-				compressed.push_back({carry, dmax + 1});
-
-				fa_count += 1;
-				i += 3;
-			} else {
-				// Uncompressed operands pass through to next level
-				for (; i < ready.size(); i++)
-					compressed.push_back(ready[i]);
-				break;
-			}
-		}
-
-		// Merge compressed with waiting operands
-		for (auto &op : waiting)
-			compressed.push_back(op);
-
-		operands = std::move(compressed);
-		levels++;
-	}
-
-	if(compressor_count)
-		*compressor_count = fa_count;
-
-	if (operands.size() == 0)
-		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
-	if (operands.size() == 1)
-		return {operands[0].sig, SigSpec(State::S0, width)};
-
-	final_depth = std::max(operands[0].depth, operands[1].depth);
-	log_assert(operands.size() == 2);
-	log("    CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
-	return {operands[0].sig, operands[1].sig};
-}
+std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr);
 
 /**
  * emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
@@ -310,79 +93,7 @@ inline std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<
  * @b: Signal B
  * @y: Signal Y = (A + B) mod 2^W
  */
-inline void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
-{
-	int width = GetSize(y);
-	log_assert(GetSize(a) == width);
-	log_assert(GetSize(b) == width);
-
-	if (width == 0)
-		return;
-
-	if (width == 1) {
-		module->addXorGate(NEW_ID, a[0], b[0], y[0]);
-		return;
-	}
-
-	// Bit level gen and prop
-	std::vector<SigBit> g_pre(width), p_pre(width);
-	for (int i = 0; i < width; i++) {
-		SigBit gi = module->addWire(NEW_ID);
-		SigBit pi = module->addWire(NEW_ID);
-		module->addAndGate(NEW_ID, a[i], b[i], gi);
-		module->addXorGate(NEW_ID, a[i], b[i], pi);
-		g_pre[i] = gi;
-		p_pre[i] = pi;
-	}
-
-	// Propagate (g, p) through ceil(log2 W) levels
-	std::vector<SigBit> g = g_pre;
-	std::vector<SigBit> p = p_pre;
-	int num_levels = 0;
-
-	while ((1 << num_levels) < width)
-		num_levels++;
-
-	for (int k = 1; k <= num_levels; k++) {
-		int s = 1 << (k - 1);
-		std::vector<SigBit> g_next(width), p_next(width);
-		for (int i = 0; i < width; i++) {
-			if (i < s) {
-				// Nothing to do
-				g_next[i] = g[i];
-				p_next[i] = p[i];
-			} else {
-				// g_i^k = g_i | (p_i & g_(i-s))
-				SigBit and_pg = module->addWire(NEW_ID);
-				module->addAndGate(NEW_ID, p[i], g[i - s], and_pg);
-				SigBit gnew = module->addWire(NEW_ID);
-				module->addOrGate(NEW_ID, g[i], and_pg, gnew);
-				g_next[i] = gnew;
-
-				// p_i^k = p_i & p_(i-s)
-				if (k < num_levels) {
-					SigBit pnew = module->addWire(NEW_ID);
-					module->addAndGate(NEW_ID, p[i], p[i - s], pnew);
-					p_next[i] = pnew;
-				} else {
-					// Skip last level
-					p_next[i] = State::Sx;
-				}
-			}
-		}
-
-		g = std::move(g_next);
-		p = std::move(p_next);
-	}
-
-	// Sum layer, g[i] is COUT of bit i
-	// With CIN 0:
-	//   sum[0] = p_pre[0]
-	//   sum[i] = p_pre[i] ^ g[i-1] ...
-	module->connect(y[0], p_pre[0]);
-	for (int i = 1; i < width; i++)
-		module->addXorGate(NEW_ID, p_pre[i], g[i - 1], y[i]);
-}
+void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y);
 
 /**
  * emit_final_adder() - Emit the final carry-propagate addition between the two reduced vectors
@@ -394,29 +105,9 @@ inline void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y)
  *
  * Return: Cell* of the emitted instance
  */
-inline Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice) {
-	switch (choice) {
-		case FinalAdder::DEFAULT:
-		case FinalAdder::RIPPLE: {
-			return module->addAdd(NEW_ID, a, b, y, false);
-		}
-		case FinalAdder::PARALLEL_PREFIX: {
-			emit_kogge_stone(module, a, b, y);
-			return nullptr;
-		}
-	}
-	log_assert(false && "CompressorTree::emit_final_adder: invalid choice");
-	return nullptr;
-}
+Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice);
 
-inline FinalAdder pick_final_adder(int width, FinalMode mode) {
-	switch (mode) {
-		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
-		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
-		case FinalMode::AUTO:
-		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
-	}
-}
+FinalAdder pick_final_adder(int width, FinalMode mode);
 
 } // namespace CompressorTree
 

From 11a650c69548911bf86ebcfd5ecef5e3f952c296 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Wed, 3 Jun 2026 14:54:19 +0200
Subject: [PATCH 08/16] Fix depth bug.

---
 kernel/compressor_tree.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/kernel/compressor_tree.cc b/kernel/compressor_tree.cc
index ee7b2a2fc..90b632126 100644
--- a/kernel/compressor_tree.cc
+++ b/kernel/compressor_tree.cc
@@ -180,7 +180,7 @@ std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSi
 				DepthSig d = ready[i + 3];
 
 				auto [sum, carry] = emit_compressor_42(module, a.sig, b.sig, c.sig, d.sig, width);
-				int dmax = std::max({a.depth, a.depth, a.depth, a.depth});
+				int dmax = std::max({a.depth, b.depth, c.depth, d.depth});
 
 				compressed.push_back({sum, dmax + 2});
 				compressed.push_back({carry, dmax + 2});

From f8d2252735aeffadacee7c222547dfbcec7b5926 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Wed, 3 Jun 2026 15:13:20 +0200
Subject: [PATCH 09/16] Use ripple as default final adder, gate fma.

---
 passes/techmap/arith_tree.cc              | 44 +++++++++++------------
 tests/arith_tree/arith_tree_defaults.ys   |  6 ++--
 tests/arith_tree/arith_tree_fma.ys        |  6 ++--
 tests/arith_tree/arith_tree_signed_fma.ys |  4 +--
 4 files changed, 29 insertions(+), 31 deletions(-)

diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index b7d89d528..40544151e 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -19,7 +19,7 @@ PRIVATE_NAMESPACE_BEGIN
 
 struct ArithTreeOptions {
 	CompressorTree::Strategy strategy = CompressorTree::Strategy::PREFER_42;
-	CompressorTree::FinalMode final_mode = CompressorTree::FinalMode::AUTO;
+	CompressorTree::FinalMode final_mode = CompressorTree::FinalMode::RIPPLE;
 	bool fma_fusion = true;
 };
 
@@ -309,22 +309,21 @@ struct ArithTreeWorker {
 					s = module->Not(NEW_ID, s);
 				pool.push_back({s, 0});
 			} else {
-				// Multiplicative operand.
-				auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
+					// Multiplicative operand
+					auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
 
-				if (!op.negate) {
-					for (auto &pp : pps)
+					if (!op.negate) {
+						for (auto &pp : pps)
+							pool.push_back(pp);
+						continue;
+					}
+
+					SigSpec neg_a = module->Not(NEW_ID, op.sig);
+					auto neg_pps = CompressorTree::generate_partial_products(module, neg_a, op.factor_b, op.is_signed, op.factor_b_signed, width);
+					for (auto &pp : neg_pps)
 						pool.push_back(pp);
-					continue;
-				}
-
-				auto [a_red, b_red] = CompressorTree::reduce_scheduled(module, pps, width, opt.strategy);
-				SigSpec product = module->addWire(NEW_ID, width);
-				module->addAdd(NEW_ID, a_red, b_red, product, false);
-				SigSpec neg = module->addWire(NEW_ID, width);
-				module->addNot(NEW_ID, product, neg);
-				pool.push_back({neg, 0});
-				neg_compensation++;
+					SigSpec b_ext = CompressorTree::normalize_to_width(op.factor_b, op.factor_b_signed, width);
+					pool.push_back({b_ext, 0});
 			}
 		}
 
@@ -392,22 +391,21 @@ struct ArithTreeWorker {
 				continue;
 			if (operands.size() < 1)
 				continue;
-			bool has_mul = false;
+			int mul_terms = 0;
 			for (auto &op : operands)
-				if (GetSize(op.factor_b) > 0) {
-					has_mul = true;
-					break;
-				}
-
+				if (GetSize(op.factor_b) > 0)
+					mul_terms++;
+			bool has_mul = (mul_terms > 0);
+			if (mul_terms == 1 && operands.size() == 1)
+				continue;
 			if (!has_mul && operands.size() < 3)
 				continue;
-
 			emit_tree(operands, cell->getPort(ID::Y), neg_compensation);
 			to_remove.insert(cell);
 		}
 		for (auto cell : to_remove)
 			module->remove(cell);
-	}
+}
 
 	void run()
 	{
diff --git a/tests/arith_tree/arith_tree_defaults.ys b/tests/arith_tree/arith_tree_defaults.ys
index b7b72062c..c5427c4e5 100644
--- a/tests/arith_tree/arith_tree_defaults.ys
+++ b/tests/arith_tree/arith_tree_defaults.ys
@@ -52,9 +52,9 @@ proc
 equiv_opt arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
-select -assert-none t:$add
-select -assert-min 1 t:$_AND_
-select -assert-min 1 t:$_XOR_
+select -assert-count 1 t:$add
+select -assert-min 0 t:$_AND_
+select -assert-min 0 t:$_XOR_
 design -reset
 
 read_verilog <<EOT
diff --git a/tests/arith_tree/arith_tree_fma.ys b/tests/arith_tree/arith_tree_fma.ys
index 95d9b566f..398e9cd8d 100644
--- a/tests/arith_tree/arith_tree_fma.ys
+++ b/tests/arith_tree/arith_tree_fma.ys
@@ -12,10 +12,10 @@ alumacc
 opt
 equiv_opt arith_tree
 design -load postopt
-select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 1 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
-select -assert-count 1 t:$add
-select -assert-min 1 t:$fa
+select -assert-count 0 t:$add
+select -assert-min 0 t:$fa
 design -reset
 
 read_verilog <<EOT
diff --git a/tests/arith_tree/arith_tree_signed_fma.ys b/tests/arith_tree/arith_tree_signed_fma.ys
index 104d96d42..8a4e8b4ef 100644
--- a/tests/arith_tree/arith_tree_signed_fma.ys
+++ b/tests/arith_tree/arith_tree_signed_fma.ys
@@ -32,9 +32,9 @@ alumacc
 opt
 equiv_opt arith_tree
 design -load postopt
-select -assert-count 0 t:$macc t:$macc_v2 %u
+select -assert-count 1 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
-select -assert-min 1 t:$fa
+select -assert-min 0 t:$fa
 design -reset
 
 read_verilog <<EOT

From 3c6900a570546f157248399e1902413cb07fe782 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Wed, 3 Jun 2026 15:35:17 +0200
Subject: [PATCH 10/16] Depth-schedule finar adder.

---
 kernel/compressor_tree.cc                  | 27 ++++++++++++------
 kernel/compressor_tree.h                   | 10 ++++---
 passes/techmap/arith_tree.cc               | 32 ++++++++++++----------
 tests/arith_tree/arith_tree_final_adder.ys |  6 ++--
 4 files changed, 45 insertions(+), 30 deletions(-)

diff --git a/kernel/compressor_tree.cc b/kernel/compressor_tree.cc
index 90b632126..dad777114 100644
--- a/kernel/compressor_tree.cc
+++ b/kernel/compressor_tree.cc
@@ -133,7 +133,7 @@ std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSp
 	return products;
 }
 
-std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count) {
+std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *out_compressor_count, int *out_final_depth) {
 	int levels = 0;
 	int fa_count = 0;
 	int c42_count = 0;
@@ -217,15 +217,22 @@ std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSi
 		levels++;
 	}
 
-	if(compressor_count)
-		*compressor_count = fa_count;
-
-	if (operands.size() == 0)
+	if(out_compressor_count)
+		*out_compressor_count = fa_count;
+	if (operands.size() == 0) {
+		if (out_final_depth)
+			*out_final_depth = 0;
 		return {SigSpec(State::S0, width), SigSpec(State::S0, width)};
-	if (operands.size() == 1)
+	}
+	if (operands.size() == 1) {
+		if (out_final_depth)
+			*out_final_depth = operands[0].depth;
 		return {operands[0].sig, SigSpec(State::S0, width)};
+	}
 
 	final_depth = std::max(operands[0].depth, operands[1].depth);
+	if (out_final_depth)
+		*out_final_depth = final_depth;
 	log_assert(operands.size() == 2);
 	log("    CompressorTree::reduce_scheduled: %d levels, %d $fa (%d as 4:2), final depth %d\n", levels, fa_count, c42_count, final_depth);
 	return {operands[0].sig, operands[1].sig};
@@ -320,12 +327,16 @@ Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdd
 	return nullptr;
 }
 
-FinalAdder pick_final_adder(int width, FinalMode mode) {
+FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode) {
 	switch (mode) {
 		case FinalMode::RIPPLE:  return FinalAdder::RIPPLE;
 		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
 		case FinalMode::AUTO:
-		default:                 return (width < RIPPLE_PREFIX_THRESHOLD) ? FinalAdder::DEFAULT : FinalAdder::PARALLEL_PREFIX;
+		default: {
+			bool wide = width >= RIPPLE_PREFIX_THRESHOLD;
+			bool deep = final_depth >= PREFIX_DEPTH_THRESHOLD;
+			return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
+		}
 	}
 }
 
diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index 54a4d421d..814f7fdca 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -29,8 +29,9 @@ YOSYS_NAMESPACE_BEGIN
 namespace CompressorTree
 {
 
-// Width threshold below which a ripple is preferred over parallel-prefix
+// Width and depth thresholds below which a ripple is preferred over parallel-prefix
 constexpr int RIPPLE_PREFIX_THRESHOLD = 16;
+constexpr int PREFIX_DEPTH_THRESHOLD = 5;
 
 enum class Strategy {
 	FA_ONLY,   // 3:2 compressors
@@ -80,11 +81,12 @@ std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSp
  * @sigs: Vector of input signals (operands) to be reduced
  * @width: Target bit-width to which all operands will be zero-extended
  * @strategy: Compression strategy to use
- * @compressor_count: Optional pointer to return the number of $fa cells emitted
+ * @out_compressor_count: Optional pointer to return the number of $fa cells emitted
+ * @out_final_depth: Optional pointer to return the final depth of the scheduled tree
  *
  * Return: The final two reduced operands, that are to be fed into an adder
  */
-std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *compressor_count = nullptr);
+std::pair<SigSpec, SigSpec> reduce_scheduled(Module *module, std::vector<DepthSig> operands, int width, Strategy strategy, int *out_compressor_count = nullptr, int *out_final_depth = nullptr);
 
 /**
  * emit_kogge_stone() - Emit a Kogge-Stone parallel-prefix adder
@@ -107,7 +109,7 @@ void emit_kogge_stone(Module *module, SigSpec a, SigSpec b, SigSpec y);
  */
 Cell *emit_final_adder(Module *module, SigSpec a, SigSpec b, SigSpec y, FinalAdder choice);
 
-FinalAdder pick_final_adder(int width, FinalMode mode);
+FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode);
 
 } // namespace CompressorTree
 
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index 40544151e..bde3decc0 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -309,21 +309,22 @@ struct ArithTreeWorker {
 					s = module->Not(NEW_ID, s);
 				pool.push_back({s, 0});
 			} else {
-					// Multiplicative operand
-					auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
+				// Multiplicative operand
+				auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);
 
-					if (!op.negate) {
-						for (auto &pp : pps)
-							pool.push_back(pp);
-						continue;
-					}
-
-					SigSpec neg_a = module->Not(NEW_ID, op.sig);
-					auto neg_pps = CompressorTree::generate_partial_products(module, neg_a, op.factor_b, op.is_signed, op.factor_b_signed, width);
-					for (auto &pp : neg_pps)
+				if (!op.negate) {
+					for (auto &pp : pps)
 						pool.push_back(pp);
-					SigSpec b_ext = CompressorTree::normalize_to_width(op.factor_b, op.factor_b_signed, width);
-					pool.push_back({b_ext, 0});
+					continue;
+				}
+
+				auto [pa, pb] = CompressorTree::reduce_scheduled(module, pps, width, opt.strategy);
+				SigSpec p = module->addWire(NEW_ID, width);
+				module->addAdd(NEW_ID, pa, pb, p, false);
+				SigSpec np = module->addWire(NEW_ID, width);
+				module->addNot(NEW_ID, p, np);
+				pool.push_back({np, 0});
+				neg_compensation++;
 			}
 		}
 
@@ -337,8 +338,9 @@ struct ArithTreeWorker {
 	{
 		int width = GetSize(result_y);
 		auto pool = build_operand_pool(operands, width, neg_compensation);
-		auto [a, b] = CompressorTree::reduce_scheduled(module, std::move(pool), width, opt.strategy);
-		auto final_choice = CompressorTree::pick_final_adder(width, opt.final_mode);
+		int final_depth = 0;
+		auto [a, b] = CompressorTree::reduce_scheduled(module, std::move(pool), width, opt.strategy, nullptr, &final_depth);
+		auto final_choice = CompressorTree::pick_final_adder(width, final_depth, opt.final_mode);
 		CompressorTree::emit_final_adder(module, a, b, result_y, final_choice);
 	}
 
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
index df995f531..b8184128a 100644
--- a/tests/arith_tree/arith_tree_final_adder.ys
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -10,10 +10,10 @@ hierarchy -auto-top
 proc
 equiv_opt arith_tree -final auto
 design -load postopt
-select -assert-none t:$add
+select -assert-count 1 t:$add
 select -assert-count 2 t:$fa
-select -assert-min 1 t:$_AND_
-select -assert-min 1 t:$_XOR_
+select -assert-none t:$_AND_
+select -assert-none 1 t:$_XOR_
 design -reset
 
 read_verilog <<EOT

From 666bd53f06772a5009a5659994f424a054d27cbf Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 8 Jun 2026 11:50:06 +0200
Subject: [PATCH 11/16] Cleanup tests.

---
 tests/arith_tree/arith_tree_add_chains.ys  | 20 +++++-----
 tests/arith_tree/arith_tree_edge_cases.ys  | 44 +++++++++++-----------
 tests/arith_tree/arith_tree_final_adder.ys |  2 +-
 tests/arith_tree/arith_tree_idempotent.ys  |  8 ++--
 tests/arith_tree/arith_tree_sub_chains.ys  | 26 ++++++-------
 5 files changed, 50 insertions(+), 50 deletions(-)

diff --git a/tests/arith_tree/arith_tree_add_chains.ys b/tests/arith_tree/arith_tree_add_chains.ys
index 7fd59e2ee..f293ed9da 100644
--- a/tests/arith_tree/arith_tree_add_chains.ys
+++ b/tests/arith_tree/arith_tree_add_chains.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -23,7 +23,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -38,7 +38,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -55,7 +55,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 14 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -76,7 +76,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 2 t:$alu
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -102,7 +102,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 3 t:$alu
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -131,7 +131,7 @@ endmodule
 EOT
 hierarchy -auto-top
 select -assert-count 4 t:$alu
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -151,7 +151,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -170,7 +170,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -189,7 +189,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
diff --git a/tests/arith_tree/arith_tree_edge_cases.ys b/tests/arith_tree/arith_tree_edge_cases.ys
index a6dc4b3ac..c7b6ebb53 100644
--- a/tests/arith_tree/arith_tree_edge_cases.ys
+++ b/tests/arith_tree/arith_tree_edge_cases.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -23,7 +23,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -38,7 +38,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -56,7 +56,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -71,7 +71,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -86,7 +86,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -101,7 +101,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -117,7 +117,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 4 t:$fa
 select -assert-count 2 t:$add
 design -reset
@@ -141,7 +141,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 design -reset
@@ -158,7 +158,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -177,7 +177,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -196,7 +196,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -215,7 +215,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-none t:$mul
@@ -254,7 +254,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$fa
 select -assert-count 2 t:$alu
@@ -272,7 +272,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$fa
 design -reset
@@ -292,7 +292,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -312,7 +312,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -341,7 +341,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-min 1 t:$dff
 design -reset
@@ -360,7 +360,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -380,7 +380,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -400,7 +400,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 select -assert-none t:$fa
 select -assert-none t:$add
 select -assert-none t:$sub
@@ -419,7 +419,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-none t:$mul
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
index b8184128a..6c6da792a 100644
--- a/tests/arith_tree/arith_tree_final_adder.ys
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -44,7 +44,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -final ripple
+equiv_opt arith_tree
 design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 0 t:$add a:adder_arch %i
diff --git a/tests/arith_tree/arith_tree_idempotent.ys b/tests/arith_tree/arith_tree_idempotent.ys
index e071b89b7..3ca0fcc90 100644
--- a/tests/arith_tree/arith_tree_idempotent.ys
+++ b/tests/arith_tree/arith_tree_idempotent.ys
@@ -9,11 +9,11 @@ EOT
 hierarchy -auto-top
 proc
 
-arith_tree -final ripple
+arith_tree
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 
-arith_tree -final ripple
+arith_tree
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
@@ -32,13 +32,13 @@ proc
 alumacc
 opt_clean
 
-arith_tree -final ripple
+arith_tree
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
 select -assert-none t:$alu
 
-arith_tree -final ripple
+arith_tree
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
 select -assert-none t:$sub
diff --git a/tests/arith_tree/arith_tree_sub_chains.ys b/tests/arith_tree/arith_tree_sub_chains.ys
index 6fd42ca8c..a34cb3868 100644
--- a/tests/arith_tree/arith_tree_sub_chains.ys
+++ b/tests/arith_tree/arith_tree_sub_chains.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@@ -25,7 +25,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@@ -42,7 +42,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 3 t:$not
@@ -59,7 +59,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 4 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 2 t:$not
@@ -76,7 +76,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 2 t:$not
@@ -94,7 +94,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-arith_tree -final ripple
+arith_tree
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
 select -assert-count 1 t:$not
@@ -113,7 +113,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -133,7 +133,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -153,7 +153,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -173,7 +173,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt_clean
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -193,7 +193,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@@ -212,7 +212,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@@ -232,7 +232,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-arith_tree -final ripple
+arith_tree
 opt_clean
 select -assert-none t:$macc t:$macc_v2 %u
 select -assert-count 4 t:$fa

From c47ed4bc31551ee0b8b023c30254a178f039d077 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Mon, 8 Jun 2026 11:52:25 +0200
Subject: [PATCH 12/16] Fix help.

---
 passes/techmap/arith_tree.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index bde3decc0..7de21190a 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -444,7 +444,7 @@ struct ArithTreePass : public Pass {
 		log("        Disable fused multiply-add expansion in $macc cells\n");
 		log("\n");
 		log("The default behaviour delivers 4:2 compression, FMA fusion, and a\n");
-		log("width-adaptive final adder\n");
+		log("final standard adder\n");
 		log("\n");
 	}
 

From c44d24d9fd9baa47d68b5af6915d160417203d01 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Thu, 11 Jun 2026 01:08:36 +0200
Subject: [PATCH 13/16] Add missing -assert to equiv_opt calls.

---
 tests/arith_tree/arith_tree_42.ys             | 14 ++++++------
 tests/arith_tree/arith_tree_alu_macc_equiv.ys | 12 +++++-----
 tests/arith_tree/arith_tree_defaults.ys       |  4 ++--
 tests/arith_tree/arith_tree_equiv.ys          | 22 +++++++++----------
 tests/arith_tree/arith_tree_final_adder.ys    |  8 +++----
 tests/arith_tree/arith_tree_fma.ys            | 12 +++++-----
 tests/arith_tree/arith_tree_signed_fma.ys     | 14 ++++++------
 7 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/tests/arith_tree/arith_tree_42.ys b/tests/arith_tree/arith_tree_42.ys
index 75951ab5e..f0657cde3 100644
--- a/tests/arith_tree/arith_tree_42.ys
+++ b/tests/arith_tree/arith_tree_42.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy 42
+equiv_opt -assert arith_tree -strategy 42
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -26,7 +26,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy fa
+equiv_opt -assert arith_tree -strategy fa
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -44,7 +44,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy 42
+equiv_opt -assert arith_tree -strategy 42
 design -load postopt
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
@@ -63,7 +63,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy 42
+equiv_opt -assert arith_tree -strategy 42
 design -load postopt
 select -assert-count 14 t:$fa
 select -assert-count 1 t:$add
@@ -80,7 +80,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy 42
+equiv_opt -assert arith_tree -strategy 42
 design -load postopt
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -97,7 +97,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy 42
+equiv_opt -assert arith_tree -strategy 42
 design -load postopt
 select -assert-count 4 t:$fa
 select -assert-count 1 t:$add
@@ -114,7 +114,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -strategy 42
+equiv_opt -assert arith_tree -strategy 42
 design -load postopt
 select -assert-count 5 t:$fa
 select -assert-count 1 t:$add
diff --git a/tests/arith_tree/arith_tree_alu_macc_equiv.ys b/tests/arith_tree/arith_tree_alu_macc_equiv.ys
index 95839d04f..165bf5975 100644
--- a/tests/arith_tree/arith_tree_alu_macc_equiv.ys
+++ b/tests/arith_tree/arith_tree_alu_macc_equiv.ys
@@ -10,7 +10,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -28,7 +28,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -46,7 +46,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
@@ -64,7 +64,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -82,7 +82,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
@@ -100,7 +100,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
diff --git a/tests/arith_tree/arith_tree_defaults.ys b/tests/arith_tree/arith_tree_defaults.ys
index c5427c4e5..ee2903b72 100644
--- a/tests/arith_tree/arith_tree_defaults.ys
+++ b/tests/arith_tree/arith_tree_defaults.ys
@@ -49,7 +49,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -67,7 +67,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
diff --git a/tests/arith_tree/arith_tree_equiv.ys b/tests/arith_tree/arith_tree_equiv.ys
index 9595d3070..81b2d5007 100644
--- a/tests/arith_tree/arith_tree_equiv.ys
+++ b/tests/arith_tree/arith_tree_equiv.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -24,7 +24,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -40,7 +40,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -56,7 +56,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 6 t:$fa
 select -assert-count 1 t:$add
@@ -72,7 +72,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -90,7 +90,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$fa
 select -assert-count 1 t:$add
@@ -106,7 +106,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
@@ -122,7 +122,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
@@ -138,7 +138,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-min 1 t:$fa
 select -assert-count 1 t:$add
@@ -154,7 +154,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 3 t:$fa
 select -assert-count 1 t:$add
@@ -171,7 +171,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 2 t:$fa
 select -assert-count 1 t:$add
diff --git a/tests/arith_tree/arith_tree_final_adder.ys b/tests/arith_tree/arith_tree_final_adder.ys
index 6c6da792a..6bb960ae4 100644
--- a/tests/arith_tree/arith_tree_final_adder.ys
+++ b/tests/arith_tree/arith_tree_final_adder.ys
@@ -8,7 +8,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -final auto
+equiv_opt -assert arith_tree -final auto
 design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 2 t:$fa
@@ -26,7 +26,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -final auto
+equiv_opt -assert arith_tree -final auto
 design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 2 t:$fa
@@ -44,7 +44,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$add
 select -assert-count 0 t:$add a:adder_arch %i
@@ -61,7 +61,7 @@ endmodule
 EOT
 hierarchy -auto-top
 proc
-equiv_opt arith_tree -final prefix
+equiv_opt -assert arith_tree -final prefix
 design -load postopt
 select -assert-none t:$add
 select -assert-min 1 t:$_AND_
diff --git a/tests/arith_tree/arith_tree_fma.ys b/tests/arith_tree/arith_tree_fma.ys
index 398e9cd8d..1528f0082 100644
--- a/tests/arith_tree/arith_tree_fma.ys
+++ b/tests/arith_tree/arith_tree_fma.ys
@@ -10,7 +10,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -31,7 +31,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -51,7 +51,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -72,7 +72,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -93,7 +93,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree -no-fma
+equiv_opt -assert arith_tree -no-fma
 design -load postopt
 select -assert-count 0 t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u
@@ -112,7 +112,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
diff --git a/tests/arith_tree/arith_tree_signed_fma.ys b/tests/arith_tree/arith_tree_signed_fma.ys
index 8a4e8b4ef..a12780fe4 100644
--- a/tests/arith_tree/arith_tree_signed_fma.ys
+++ b/tests/arith_tree/arith_tree_signed_fma.ys
@@ -11,7 +11,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -30,7 +30,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 1 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -49,7 +49,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -69,7 +69,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -89,7 +89,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-min 1 t:$fa
@@ -108,7 +108,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree
+equiv_opt -assert arith_tree
 design -load postopt
 select -assert-count 0 t:$macc t:$macc_v2 %u
 select -assert-count 0 t:$mul
@@ -128,7 +128,7 @@ hierarchy -auto-top
 proc
 alumacc
 opt
-equiv_opt arith_tree -no-fma
+equiv_opt -assert arith_tree -no-fma
 design -load postopt
 select -assert-count 0 t:$fa
 select -assert-min 1 t:$macc t:$macc_v2 %u

From 135c2a4113bcba1b5570bfb99be123ea8e2a4f09 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Thu, 11 Jun 2026 01:12:35 +0200
Subject: [PATCH 14/16] Get rid of normalize_to_width.

---
 kernel/compressor_tree.cc    | 23 +++--------------------
 kernel/compressor_tree.h     |  6 ++----
 passes/techmap/arith_tree.cc |  6 +++---
 3 files changed, 8 insertions(+), 27 deletions(-)

diff --git a/kernel/compressor_tree.cc b/kernel/compressor_tree.cc
index dad777114..de2260d26 100644
--- a/kernel/compressor_tree.cc
+++ b/kernel/compressor_tree.cc
@@ -43,23 +43,6 @@ std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpe
 	return {sum, carry};
 }
 
-SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width)
-{
-	// Zero/sign-extend to width
-	if (GetSize(sig) < width) {
-		SigBit pad;
-		if (is_signed && GetSize(sig) > 0)
-			pad = sig[GetSize(sig) - 1];
-		else
-			pad = State::S0;
-		sig.append(SigSpec(pad, width - GetSize(sig)));
-	}
-	// Truncate to width
-	if (GetSize(sig) > width)
-		sig = sig.extract(0, width);
-	return sig;
-}
-
 std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSpec b, bool a_signed, bool b_signed, int width) {
 	int width_a = GetSize(a);
 	int width_b = GetSize(b);
@@ -72,7 +55,7 @@ std::vector<DepthSig> generate_partial_products(Module *module, SigSpec a, SigSp
 		// b_shifted = (0_i ## b)
 		SigSpec b_shifted = SigSpec(State::S0, i);
 		b_shifted.append(b);
-		b_shifted = normalize_to_width(b_shifted, false, width);
+		b_shifted.extend_u0(width, false);
 
 		// row = b_shifted & replicate(a[i], width)
 		SigSpec ai_rep = SigSpec(ai, width);
@@ -333,8 +316,8 @@ FinalAdder pick_final_adder(int width, int final_depth, FinalMode mode) {
 		case FinalMode::PREFIX:  return FinalAdder::PARALLEL_PREFIX;
 		case FinalMode::AUTO:
 		default: {
-			bool wide = width >= RIPPLE_PREFIX_THRESHOLD;
-			bool deep = final_depth >= PREFIX_DEPTH_THRESHOLD;
+			bool wide = width >= RIPPLE_PREFIX_WIDTH_THRESHOLD;
+			bool deep = final_depth >= RIPPLE_PREFIX_DEPTH_THRESHOLD;
 			return (wide && deep) ? FinalAdder::PARALLEL_PREFIX : FinalAdder::DEFAULT;
 		}
 	}
diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index 814f7fdca..cf525ea78 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -30,8 +30,8 @@ namespace CompressorTree
 {
 
 // Width and depth thresholds below which a ripple is preferred over parallel-prefix
-constexpr int RIPPLE_PREFIX_THRESHOLD = 16;
-constexpr int PREFIX_DEPTH_THRESHOLD = 5;
+constexpr int RIPPLE_PREFIX_WIDTH_THRESHOLD = 16;
+constexpr int RIPPLE_PREFIX_DEPTH_THRESHOLD = 5;
 
 enum class Strategy {
 	FA_ONLY,   // 3:2 compressors
@@ -59,8 +59,6 @@ enum class FinalMode {
 std::pair<SigSpec, SigSpec> emit_compressor_32(Module *module, SigSpec a, SigSpec b, SigSpec c, int width);
 std::pair<SigSpec, SigSpec> emit_compressor_42(Module *module, SigSpec a, SigSpec b, SigSpec c, SigSpec d, int width);
 
-SigSpec normalize_to_width(SigSpec sig, bool is_signed, int width);
-
 /**
  * generate_partial_products() - Generate partial products for FMA concat
  * @module:The Yosys module to which the compressors will be added
diff --git a/passes/techmap/arith_tree.cc b/passes/techmap/arith_tree.cc
index 7de21190a..39217f817 100644
--- a/passes/techmap/arith_tree.cc
+++ b/passes/techmap/arith_tree.cc
@@ -304,10 +304,10 @@ struct ArithTreeWorker {
 		for (auto &op : operands) {
 			if (GetSize(op.factor_b) == 0) {
 				// Additive operand
-				SigSpec s = CompressorTree::normalize_to_width(op.sig, op.is_signed, width);
+				op.sig.extend_u0(width, op.is_signed);
 				if (op.negate)
-					s = module->Not(NEW_ID, s);
-				pool.push_back({s, 0});
+					op.sig = module->Not(NEW_ID, op.sig);
+				pool.push_back({op.sig, 0});
 			} else {
 				// Multiplicative operand
 				auto pps = CompressorTree::generate_partial_products(module, op.sig, op.factor_b, op.is_signed, op.factor_b_signed, width);

From 309b7d2496c00b0f02634048be7dcfee7d91b716 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Fri, 12 Jun 2026 14:55:47 +0200
Subject: [PATCH 15/16] Verify kogge stone impl.

---
 passes/tests/CMakeLists.txt           |   3 +
 passes/tests/test_kogge_stone.cc      | 101 ++++++++++++++++++++++++++
 tests/arith_tree/kogge_stone_equiv.ys |  67 +++++++++++++++++
 3 files changed, 171 insertions(+)
 create mode 100644 passes/tests/test_kogge_stone.cc
 create mode 100644 tests/arith_tree/kogge_stone_equiv.ys

diff --git a/passes/tests/CMakeLists.txt b/passes/tests/CMakeLists.txt
index 007339ac5..5cedacf81 100644
--- a/passes/tests/CMakeLists.txt
+++ b/passes/tests/CMakeLists.txt
@@ -7,6 +7,9 @@ yosys_test_pass(cell
 yosys_test_pass(abcloop
 	test_abcloop.cc
 )
+yosys_test_pass(kogge_stone
+	test_kogge_stone.cc
+)
 
 yosys_pass(raise_error
 	raise_error.cc
diff --git a/passes/tests/test_kogge_stone.cc b/passes/tests/test_kogge_stone.cc
new file mode 100644
index 000000000..95b97bb14
--- /dev/null
+++ b/passes/tests/test_kogge_stone.cc
@@ -0,0 +1,101 @@
+#include "kernel/compressor_tree.h"
+#include "kernel/yosys.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+static void build_lcu_adder(Module *module, SigSpec a, SigSpec b, SigSpec y)
+{
+	int width = GetSize(y);
+
+	SigSpec p = module->Xor(NEW_ID, a, b);
+	SigSpec g = module->And(NEW_ID, a, b);
+
+	SigSpec co = module->addWire(NEW_ID, width);
+	Cell *lcu = module->addCell(NEW_ID, ID($lcu));
+	lcu->setParam(ID::WIDTH, width);
+	lcu->setPort(ID::P, p);
+	lcu->setPort(ID::G, g);
+	lcu->setPort(ID::CI, State::S0);
+	lcu->setPort(ID::CO, co);
+
+	SigSpec carry_in;
+	carry_in.append(State::S0);
+	carry_in.append(co.extract(0, width - 1));
+	module->addXor(NEW_ID, p, carry_in, y);
+}
+
+static Module *make_module(Design *design, IdString name, int width)
+{
+	Module *module = design->addModule(name);
+
+	Wire *a = module->addWire(ID(a), width);
+	a->port_input = true;
+	Wire *b = module->addWire(ID(b), width);
+	b->port_input = true;
+	Wire *y = module->addWire(ID(y), width);
+	y->port_output = true;
+	module->fixup_ports();
+
+	return module;
+}
+
+struct TestKoggeStonePass : public Pass {
+	TestKoggeStonePass() : Pass("test_kogge_stone", "build adders for Kogge-Stone equivalence testing") {}
+	void help() override
+	{
+		//   |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
+		log("\n");
+		log("    test_kogge_stone [options]\n");
+		log("\n");
+		log("Build two modules implementing an unsigned 'y = a + b' adder of a given width,\n");
+		log("and compare various internal Kogge-Stone adders.\n");
+		log("\n");
+		log("    -width N\n");
+		log("        width of the operands and result (default = 16)\n");
+		log("\n");
+		log("    -gold name\n");
+		log("        name of the $lcu-based reference module (default = gold)\n");
+		log("\n");
+		log("    -gate name\n");
+		log("        name of the emit_kogge_stone() module (default = gate)\n");
+		log("\n");
+	}
+	void execute(std::vector<std::string> args, Design *design) override
+	{
+		int width = 16;
+		IdString gold_name = ID(gold);
+		IdString gate_name = ID(gate);
+
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++) {
+			if (args[argidx] == "-width" && argidx + 1 < args.size()) {
+				width = atoi(args[++argidx].c_str());
+				continue;
+			}
+			if (args[argidx] == "-gold" && argidx + 1 < args.size()) {
+				gold_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			if (args[argidx] == "-gate" && argidx + 1 < args.size()) {
+				gate_name = RTLIL::escape_id(args[++argidx]);
+				continue;
+			}
+			break;
+		}
+		extra_args(args, argidx, design, false);
+
+		if (width < 1)
+			log_cmd_error("Width must be at least 1.\n");
+
+		log_header(design, "Executing TEST_KOGGE_STONE pass (width=%d).\n", width);
+
+		Module *gold = make_module(design, gold_name, width);
+		build_lcu_adder(gold, gold->wire(ID(a)), gold->wire(ID(b)), gold->wire(ID(y)));
+
+		Module *gate = make_module(design, gate_name, width);
+		CompressorTree::emit_kogge_stone(gate, gate->wire(ID(a)), gate->wire(ID(b)), gate->wire(ID(y)));
+	}
+} TestKoggeStonePass;
+
+PRIVATE_NAMESPACE_END
diff --git a/tests/arith_tree/kogge_stone_equiv.ys b/tests/arith_tree/kogge_stone_equiv.ys
new file mode 100644
index 000000000..beceeadc2
--- /dev/null
+++ b/tests/arith_tree/kogge_stone_equiv.ys
@@ -0,0 +1,67 @@
+# Verify that CompressorTree::emit_kogge_stone() is eq to the implementation in techlibs/common/choices/kogge-stone.v
+
+test_kogge_stone -width 1
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 2
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 3
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 4
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 5
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 7
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 8
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 16
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 17
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 32
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset
+
+test_kogge_stone -width 33
+techmap -map +/choices/kogge-stone.v gold
+miter -equiv -flatten -make_outputs gold gate miter
+sat -verify -prove trigger 0 miter
+design -reset

From 80011b16b2536f9012d23eba3153f234616a01a0 Mon Sep 17 00:00:00 2001
From: nella <simontupy64@gmail.com>
Date: Fri, 12 Jun 2026 14:57:53 +0200
Subject: [PATCH 16/16] Add constant note.

---
 kernel/compressor_tree.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/kernel/compressor_tree.h b/kernel/compressor_tree.h
index cf525ea78..5ac9d1c3e 100644
--- a/kernel/compressor_tree.h
+++ b/kernel/compressor_tree.h
@@ -12,7 +12,6 @@
  *
  * References:
  * - "Some schemes for parallel multipliers" (https://www.acsel-lab.com/arithmetic/arith6/papers/ARITH6_Dadda.pdf)
- * - "Binary Adder Architectures for Cell-Based VLSI" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
  * - "Basilisk: Achieving Competitive Performance with Open EDA Tools" (https://arxiv.org/pdf/2405.03523)
  * - "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (https://iis-people.ee.ethz.ch/~zimmi/publications/adder_arch.pdf)
  * - "A Suggestion for a Fast Multiplier" (https://www.ece.ucdavis.edu/~vojin/CLASSES/EEC280/Web-page/papers/Arithmetic/Wallace_mult.pdf)
@@ -30,6 +29,8 @@ namespace CompressorTree
 {
 
 // Width and depth thresholds below which a ripple is preferred over parallel-prefix
+// NOTE: Based on "Binary Adder Architectures for Cell-Based VLSI and their Synthesis" (Tables 4.7, 4.9) - the threshold
+//       should be the point where Kogge-Stone isn't strictly less efficient than RCA
 constexpr int RIPPLE_PREFIX_WIDTH_THRESHOLD = 16;
 constexpr int RIPPLE_PREFIX_DEPTH_THRESHOLD = 5;