diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index f06e25d52..66f16de4f 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -215,6 +215,7 @@ struct MemoryMapWorker
 
 		int count_static = 0;
 
+		TwineSearch wire_search(&design->twines);
 		for (int i = 0; i < mem.size; i++)
 		{
 			int addr = i + mem.start_offset;
@@ -259,7 +260,7 @@ struct MemoryMapWorker
 				c->setPort(TW::D, w_in);
 
 				std::string w_out_name = stringf("%s[%d]", mem.memid.str(), addr);
-				if (module->wire(TwineSearch(&design->twines).find(w_out_name)) != nullptr)
+				if (module->wire(wire_search.find(w_out_name)) != nullptr)
 					w_out_name = genid(mem.memid, "", addr, "$q");
 
 				RTLIL::Wire *w_out = module->addWire(design->twines.add(std::string{w_out_name}), mem.width);