diff --git a/tests/check_mem/sub_addr.sv b/tests/check_mem/sub_addr.sv
index cc4cb3ba3..025bdc881 100644
--- a/tests/check_mem/sub_addr.sv
+++ b/tests/check_mem/sub_addr.sv
@@ -6,7 +6,7 @@ input [7:0] wdata;
 output reg [7:0] rdata;
 input [3:0] wen;
 
-reg [7:0] mem [0:3] = {8'h01, 8'h23, 8'h45, 8'h67};
+reg [7:0] mem [0:3];
 
 integer i;
 always @(posedge clk) begin
@@ -15,18 +15,4 @@ always @(posedge clk) begin
 	rdata <= mem[addr];
 end
 
-always @(posedge clk) begin
-	// not sure how to verify this one without SBY
-	// or alternatively, how to replicate the problematic sub addressing without the read&write
-	assume (wen == 0);
-	assert (mem[0][7:4] == 4'h0);
-	assert (mem[0][3:0] == 4'h1);
-	assert (mem[1][7:4] == 4'h2);
-	assert (mem[1][3:0] == 4'h3);
-	assert (mem[2][7:4] == 4'h4);
-	assert (mem[2][3:0] == 4'h5);
-	assert (mem[3][7:4] == 4'h6);
-	assert (mem[3][3:0] == 4'h7);
-end
-
 endmodule